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46 lines
1.2 KiB
Systemverilog
46 lines
1.2 KiB
Systemverilog
// Copyright (c) 2023-2025 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// common is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`ifndef INC_RST_SYNC_SV
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`define INC_RST_SYNC_SV
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module rst_sync #(
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parameter int STAGE = 3
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) (
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input logic clk_i,
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input logic rst_n_i,
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output logic rst_n_o
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);
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logic [STAGE-1:0] s_rst_sync;
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for (genvar i = 0; i < STAGE; i++) begin
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if (i == 0) begin : RST_SYNC_0_BLOCK
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dffr #(1) u_sync_dffr (
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clk_i,
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rst_n_i,
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1'b1,
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s_rst_sync[0]
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);
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end else begin : RST_SYNC_N0_BLOCK
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dffr #(1) u_sync_dffr (
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clk_i,
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rst_n_i,
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s_rst_sync[i-1],
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s_rst_sync[i]
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);
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end
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end
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assign rst_n_o = s_rst_sync[STAGE-1];
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endmodule
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`endif
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