maksyuki
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f39676db34
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fix: add name to the unname block
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2025-04-13 22:32:00 +08:00 |
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maksyuki
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13c470c91b
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docs: modify author email
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2025-04-12 14:59:51 +08:00 |
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maksyuki
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00a94402d5
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feat: add regfield module
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2025-03-11 16:23:19 +08:00 |
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maksyuki
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a1c120a17d
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chore: fix setting to config sv header
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2025-03-09 16:47:52 +08:00 |
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maksyuki
|
804a1bbb34
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chore: change copyright info on the file header
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2025-03-09 15:44:53 +08:00 |
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maksyuki
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bc7dbbbedb
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chore: mv setting name to config
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2024-12-14 21:50:18 +08:00 |
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maksyuki
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72f9bb2392
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feat: add x prop checker module
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2024-12-14 21:42:08 +08:00 |
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maksyuki
|
1bf2d680e6
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chore: modify license holder to author name
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2024-12-14 16:28:14 +08:00 |
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maksyuki
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d8fd7af63f
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chore: mv common components to the utils dir
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2024-12-14 15:57:36 +08:00 |
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maksyuki
|
181315300a
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fix: fix no trg bug in div == 0
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2024-10-18 12:26:45 +08:00 |
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maksyuki
|
08b2c0e43d
|
feat: rewrite the static clk even div module
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2024-10-16 18:37:12 +08:00 |
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maksyuki
|
9bf54c4ca3
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style: adjust port pos
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2024-10-16 14:40:09 +08:00 |
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maksyuki
|
e77d47dd25
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fix: mv axlen to the std format according to TRM
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2024-10-15 11:16:16 +08:00 |
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maksyuki
|
26761d32d9
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feat: add fir and sec clk trg ports
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2024-10-14 16:34:52 +08:00 |
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maksyuki
|
6b8c7496ad
|
feat: add clk init to the clk int div module
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2024-10-14 09:27:51 +08:00 |
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maksyuki
|
7ed073a606
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feat: add div hdshk signal to reset the clk init value
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2024-10-08 17:09:37 +08:00 |
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maksyuki
|
77dfb126a2
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chore: mv axi4 slv fsm to the specific ip path
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2024-09-28 17:03:40 +08:00 |
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maksyuki
|
5ddf8a8706
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style: simplify the fsm impl of axi4
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2024-09-28 16:50:16 +08:00 |
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maksyuki
|
009c59a644
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feat: add apb4 axi4 master class
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2024-09-27 15:43:12 +08:00 |
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maksyuki
|
4fe68b845a
|
feat: add clk cnt output port
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2024-09-26 13:36:52 +08:00 |
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maksyuki
|
088e540ef7
|
style: add specific params to the define marco
|
2024-09-10 09:37:24 +08:00 |
|
maksyuki
|
a06b29da8c
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fix: add bug tag to the stream fifo module
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2024-09-09 14:17:48 +08:00 |
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maksyuki
|
14b0662631
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style: add specific to the regfile module
|
2024-09-07 14:56:23 +08:00 |
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maksyuki
|
7b779506d7
|
syle: add named to the generate blocks
|
2024-09-07 11:28:56 +08:00 |
|
maksyuki
|
236a471c85
|
feat: add hor and ver osc pad model
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2024-09-06 20:43:08 +08:00 |
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maksyuki
|
393f3c914e
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fix: use high active for the pad io high signal
|
2024-09-06 20:24:09 +08:00 |
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maksyuki
|
733af0ee2a
|
feat: add simple pull-up and down gpio pad model
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2024-09-06 19:57:57 +08:00 |
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maksyuki
|
be837477db
|
style: add specific params to the backend impl marco
|
2024-09-06 16:20:22 +08:00 |
|
maksyuki
|
ac5ccade08
|
feat: replace reg delay value to the marcro define
|
2024-08-16 12:19:31 +08:00 |
|
maksyuki
|
a8af6b3359
|
feat: add clk gen to the clk div int module
|
2024-08-16 12:16:06 +08:00 |
|
maksyuki
|
f7b97b6983
|
docs: modify div val comment
|
2024-07-10 21:11:07 +08:00 |
|
maksyuki
|
e587d9f8d2
|
feat: use marco to replace the reg delay params
|
2024-07-09 22:39:46 +08:00 |
|
maksyuki
|
9fb0adc18f
|
feat: simplify the even div clk module impl
|
2024-07-09 22:26:47 +08:00 |
|
maksyuki
|
1c5487437d
|
feat: add global setting config header
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2024-06-27 10:12:18 +08:00 |
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maksyuki
|
2a5504d669
|
fix: fix multi driver bugs
|
2024-06-21 23:45:17 +08:00 |
|
maksyuki
|
ca5ef52991
|
feat: add axi4 slv fsm and addr gen moduels
|
2024-06-21 23:16:46 +08:00 |
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maksyuki
|
0999985294
|
feat: add bytes width log marco
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2024-06-21 23:16:25 +08:00 |
|
maksyuki
|
cd0472e2ba
|
feat: split rfe signals to single
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2024-06-17 17:50:31 +08:00 |
|
maksyuki
|
a8b664be47
|
feat: add sync edge det module
|
2024-06-17 14:18:33 +08:00 |
|
maksyuki
|
a0d2efbf75
|
feat: add name block to the regfile bit mask
|
2024-05-27 20:55:28 +08:00 |
|
maksyuki
|
07cc2e64ef
|
fix: add inc header for regfile module
|
2024-05-27 15:43:15 +08:00 |
|
maksyuki
|
e5370dd73d
|
feat: add stream fifo and data bytes def
|
2024-05-21 23:27:08 +08:00 |
|
maksyuki
|
eb65a03b26
|
feat: add cdc rst ctrl module
|
2024-05-01 13:11:57 +08:00 |
|
maksyuki
|
863da81b43
|
fix: fix a err inc marcro define
|
2024-04-22 19:50:13 +08:00 |
|
maksyuki
|
ba2494e83d
|
fix: fix some typos
|
2024-02-19 16:17:00 +08:00 |
|
maksyuki
|
ebe2a2e683
|
feat: add spill reg module
|
2024-02-19 15:53:59 +08:00 |
|
maksyuki
|
0eb80328ad
|
feat: add src and dst module impl
|
2024-02-19 15:01:53 +08:00 |
|
maksyuki
|
f8649cdf5c
|
fix: fix err rd ref data bit strb bug
|
2024-02-01 17:02:13 +08:00 |
|
maksyuki
|
3656e4b4b5
|
fix: fix error strb calc and rd mask calc
|
2024-02-01 16:05:54 +08:00 |
|
maksyuki
|
43bb8df67c
|
feat: add init cdc async fifo impl
|
2024-01-31 19:30:12 +08:00 |
|
maksyuki
|
5d8a44cc03
|
fix: fix ar and aw channel len num bug
|
2024-01-31 19:29:44 +08:00 |
|
maksyuki
|
81a51add70
|
feat: modify axi4 bfm and helper class
|
2024-01-29 10:40:17 +08:00 |
|
maksyuki
|
35885246d2
|
feat: add sync det and multi byte shift support
|
2024-01-22 14:34:44 +08:00 |
|
maksyuki
|
5543efe6e3
|
feat: add rd oper task and id check logic
|
2024-01-16 15:01:01 +08:00 |
|
maksyuki
|
01fdf3cff6
|
feat: add #1 delay to the dff
|
2024-01-16 15:00:29 +08:00 |
|
maksyuki
|
3c9aa9b8db
|
feat: add write channel impl
|
2024-01-16 10:39:09 +08:00 |
|
maksyuki
|
b143dc731c
|
fix: fix err wstrb width
|
2024-01-16 10:38:40 +08:00 |
|
maksyuki
|
66abd7206d
|
feat: rm err wid and add new define macro
|
2024-01-15 17:18:10 +08:00 |
|
maksyuki
|
f336943e3c
|
feat: add sync edge det module
|
2024-01-13 15:05:33 +08:00 |
|
maksyuki
|
c5e61ce45d
|
feat: adjust reg dir macro pos
|
2024-01-13 10:28:18 +08:00 |
|
maksyuki
|
079468e54f
|
feat: add input type support
|
2024-01-11 20:17:05 +08:00 |
|
maksyuki
|
efae3d8243
|
feat: add shift register module
|
2024-01-11 13:06:03 +08:00 |
|
maksyuki
|
d6c37bf30c
|
feat: modify axi4 bfm impl
|
2024-01-02 20:42:03 +08:00 |
|
maksyuki
|
9cfd7c8053
|
docs: add buffer depth set statement
|
2024-01-01 15:15:39 +08:00 |
|
maksyuki
|
a0b5e8b518
|
docs: add lfsr dev statement
|
2023-12-31 21:03:17 +08:00 |
|
maksyuki
|
7bb66db9c9
|
chore: modify load register name
|
2023-12-29 20:40:06 +08:00 |
|
maksyuki
|
637906f89a
|
feat: modify axi4 if, regilfe and axi4 test class impl
|
2023-12-28 20:30:33 +08:00 |
|
maksyuki
|
fd2a5ffe6e
|
chore: mv axi header define into interface dir
|
2023-12-28 20:26:04 +08:00 |
|
maksyuki
|
a68ac3503a
|
chore: add qos and regin default val
|
2023-12-28 19:10:58 +08:00 |
|
maksyuki
|
b9e1e513db
|
chore: remove unused note
|
2023-12-27 18:47:48 +08:00 |
|
maksyuki
|
d2d5b518aa
|
feat: mv 32bit into 64bit data width
|
2023-12-26 19:25:41 +08:00 |
|
maksyuki
|
32fffb4f8f
|
feat: add pll sim model impl
|
2023-12-26 19:24:50 +08:00 |
|
maksyuki
|
ebf00076fb
|
feat: add pll module
|
2023-12-22 20:12:26 +08:00 |
|
maksyuki
|
92083615e4
|
chore: add include macro and fix typos
|
2023-12-22 20:12:06 +08:00 |
|
maksyuki
|
a4a24cd52e
|
feat: add load register model
|
2023-12-08 20:15:43 +08:00 |
|
maksyuki
|
92dfd2baac
|
chore: use two-dis array to rewrite the ram model
|
2023-11-28 19:59:31 +08:00 |
|
maksyuki
|
de4bf02d99
|
feat: add axi4 master bfm model
|
2023-11-28 19:58:49 +08:00 |
|
maksyuki
|
d3279d9671
|
fix: fix a bit width and cnt num check logic
|
2023-11-27 15:11:29 +08:00 |
|
maksyuki
|
fa057cfc42
|
feat: add include macro to the gpio pad define
|
2023-11-27 11:01:17 +08:00 |
|
maksyuki
|
5b23989c11
|
fix: fix a hdshk signal init err
|
2023-11-25 16:55:08 +08:00 |
|
maksyuki
|
84d8582da5
|
chore: add include macro and fix typos
|
2023-11-25 10:55:40 +08:00 |
|
maksyuki
|
a5fbf17947
|
feat: add fe and re only edge det module
|
2023-11-25 10:55:04 +08:00 |
|
maksyuki
|
7ec4ae2977
|
chore: add include macro and modify reset val
|
2023-11-25 10:54:21 +08:00 |
|
maksyuki
|
69acd226f3
|
fix: fix a comment and MSB input err
|
2023-11-23 09:51:17 +08:00 |
|
maksyuki
|
38c9770368
|
feat: add cdc sync det module
|
2023-11-20 19:39:28 +08:00 |
|
maksyuki
|
2ba7611cb0
|
feat: modify clk div and counter modules
|
2023-11-20 19:39:02 +08:00 |
|
maksyuki
|
4ee600b546
|
feat: add parameter to the clk div
|
2023-11-19 22:38:00 +08:00 |
|
maksyuki
|
ef969c4aec
|
chore: add dynamic statement to the all tasks
|
2023-11-19 15:53:44 +08:00 |
|
maksyuki
|
c00ce997a6
|
feat: add #1 delay to the registers
|
2023-11-18 20:21:03 +08:00 |
|
maksyuki
|
57f6539232
|
feat: extern edge det to multi bits
|
2023-11-17 21:37:14 +08:00 |
|
maksyuki
|
f6ff7c29f8
|
feat: add log level to the helper rd check task
|
2023-11-17 17:38:36 +08:00 |
|
maksyuki
|
d22a72eb21
|
feat: add wr and rd check tasks
|
2023-11-17 14:36:30 +08:00 |
|
maksyuki
|
0ce8e7eb33
|
chore: add logging switch to the helper module
|
2023-11-16 20:56:06 +08:00 |
|
maksyuki
|
bb9dc07c38
|
feat: remove unused tasks
|
2023-11-16 11:48:06 +08:00 |
|
maksyuki
|
85090b8d15
|
feat: add apb4 master and test base class
|
2023-11-15 22:07:24 +08:00 |
|
maksyuki
|
e90187c26b
|
chore: modify helper print level
|
2023-11-15 22:06:47 +08:00 |
|
maksyuki
|
f015fd15d8
|
feat: modify apb4 interface and model impl
|
2023-11-15 22:05:31 +08:00 |
|
maksyuki
|
7b6fb4b610
|
feat: use helper to rewrite module
|
2023-11-15 11:31:54 +08:00 |
|
maksyuki
|
78c75c76f0
|
feat: add print and cmp check tasks
|
2023-11-15 10:47:21 +08:00 |
|
maksyuki
|
fc9796094b
|
feat: add verif helper class
|
2023-11-14 19:41:37 +08:00 |
|