feat: enhance AXI4 and RIBP interfaces with burst support and address generation

- Added burst handling to the AXI42RAM and AXI42RIBP modules, including support for fixed, increment, and wrap burst types.
- Introduced address generation logic for read and write operations based on burst parameters.
- Updated the AXI4 interconnect to validate burst types and lengths, ensuring compatibility with the AXI4 protocol.
- Modified the SDRAM controller and testbench to accommodate the new burst handling features.
- Enhanced test cases to verify the correct behavior of burst transactions and address patterns.
- Adjusted memory map and topology tests to reflect changes in the SDRAM size and interface connections.

tests/test_axi4.py

@@ -33,6 +33,7 @@ def test_axi42ribp_supports_bursts_backpressure_and_errors(tmp_path: Path) -> No
             str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"),
             str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
             str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
+            str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_addr_gen.sv"),
             str(ROOT / "rtl/mini/top/axi42ribp_burst.sv"),
             str(ROOT / "tests/rtl/axi42ribp_burst_tb.sv"),
             "-Mdir",