admin/retroSoC
1
0 Fork 0
mirror of https://github.com/retroSoC/retroSoC.git synced 2026-11-04 22:32:36 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #140 from retroSoC/dev

Browse Source 
Dev
This commit is contained in:
Yuchi Miao authored and GitHub committed 2025-12-26 23:11:32 +08:00
2 parents f6028bbeee 83d170cb03
commit 06cf17affa
18 files changed
+567 -69
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

Makefile
+2 -1
View File
@@ -90,7 +90,8 @@ ifeq ($(SOC), MINI)
endif
ifeq ($(SYNTH), YOSYS)
DEF_LIST += +define+SYNTHESIS #HACK: for some core
#HACK: for some core
DEF_LIST += +define+SYNTHESIS
$(info SYNTH DEF_LIST: $(DEF_LIST))
$(file > $(RTL_PATH)/filelist/def.fl, $(DEF_LIST))
include syn/yosys/yosys.mk
app/asm/hello.s
+103
View File
@@ -27,6 +27,108 @@ INTER_LOOP:
CHECK:
addi t1, t1, 1
ble t1, t2, APP_LOOP
# NEW ===========================
la a0, 0x0
la a1, 2000
WAIT_PSRAM_RESET:
lw t0, 0(a0)
addi a0, a0, 4
blt a0, a1, WAIT_PSRAM_RESET
LDSD_TEST:
jal ra, WRITE_8B_TEST
jal ra, READ_8B_TEST
jal ra, WRITE_16B_TEST
jal ra, READ_16B_TEST
jal ra, WRITE_32B_TEST
jal ra, READ_32B_TEST
j TEST_DONE
WRITE_8B_TEST:
li t0, 0x40000000
li t1, 0x40000010
li t2, 1
WR_8B_LOOP:
sb t2, 0(t0)
addi t2, t2, 1
addi t0, t0, 1
blt t0, t1, WR_8B_LOOP
ret
WRITE_16B_TEST:
li t0, 0x40000000
li t1, 0x40000010
li t2, 1
WR_16B_LOOP:
sh t2, 0(t0)
addi t2, t2, 1
addi t0, t0, 2
blt t0, t1, WR_16B_LOOP
ret
WRITE_32B_TEST:
li t0, 0x40000000
li t1, 0x40000010
li t2, 1
WR_32B_LOOP:
sw t2, 0(t0)
addi t2, t2, 1
addi t0, t0, 4
blt t0, t1, WR_32B_LOOP
ret
READ_8B_TEST:
li t0, 0x40000000
li t1, 0x40000010
li t2, 1
RD_8B_LOOP:
lb t3, 0(t0)
bne t2, t3, READ_ERROR
addi t0, t0, 1
addi t2, t2, 1
blt t0, t1, RD_8B_LOOP
ret
READ_16B_TEST:
li t0, 0x40000000
li t1, 0x40000010
li t2, 1
RD_16B_LOOP:
lh t3, 0(t0)
bne t2, t3, READ_ERROR
addi t0, t0, 2
addi t2, t2, 1
blt t0, t1, RD_16B_LOOP
ret
READ_32B_TEST:
li t0, 0x40000000
li t1, 0x40000010
li t2, 1
RD_32B_LOOP:
lw t3, 0(t0)
bne t2, t3, READ_ERROR
addi t0, t0, 4
addi t2, t2, 1
blt t0, t1, RD_32B_LOOP
ret
READ_ERROR:
j READ_ERROR
TEST_DONE:
la s0, msg_succ
li a0, 77
NEW_INTER_LOOP:
addi s0, s0, 1
jal ra, PUTC
lbu a0, 0(s0)
bnez a0, NEW_INTER_LOOP
END:
j END
@@ -38,3 +140,4 @@ PUTC:
.section .data
msg_hello: .string "Hello retroSoC!\n"
msg_luck: .string "Have a good luck!\n"
msg_succ: .string "Mem wr/rd test succ!\n"
crt/inc/firmware.h
+7
View File
@@ -139,6 +139,13 @@
#define reg_sysctrl_ipsel (*(volatile uint32_t*)0x1000B004)
#define reg_sysctrl_i2csel (*(volatile uint32_t*)0x1000B008)
#define reg_sysctrl_qspicsel (*(volatile uint32_t*)0x1000B00C)
// clint
#define reg_clint_clkdiv (*(volatile uint32_t*)0x1000C000)
#define reg_clint_mtimel (*(volatile uint32_t*)0x1000C004)
#define reg_clint_mtimeh (*(volatile uint32_t*)0x1000C008)
#define reg_clint_mtimecmpl (*(volatile uint32_t*)0x1000C00C)
#define reg_clint_mtimecmph (*(volatile uint32_t*)0x1000C010)
#define reg_clint_msip (*(volatile uint32_t*)0x1000C014)
// apb
// archinfo
#define reg_archinfo_sys (*(volatile uint32_t*)0x20000000)
crt/src/tinybooter.c
+2 -1
View File
@@ -45,7 +45,7 @@ void app_info() {
printf(" license: MulanPSL-2.0 license\n\n");
printf("Processor:\n");
printf(" CORE: %s\n", HW_CORE);
printf(" CORE: %s user id: %d\n", HW_CORE, reg_sysctrl_coresel);
printf(" ISA: %s\n", SW_ISA);
printf(" FREQ: %dMHz\n\n", CPU_FREQ);
@@ -70,6 +70,7 @@ void app_info() {
printf(" 1 x QSPI0 @0x%x\n", &reg_qspi0_mode);
printf(" 1 x DMA @0x%x\n", &reg_dma_mode);
printf(" 1 x SYSCTRL @0x%x\n", &reg_sysctrl_coresel);
printf(" 1 x CLINT @0x%x\n", &reg_clint_clkdiv);
printf(" 1 x ARCHINFO @0x%x\n", &reg_archinfo_sys);
printf(" 1 x RNG @0x%x\n", &reg_rng_ctrl);
printf(" 1 x UART1(ADV) @0x%x\n", &reg_uart1_lcr);
rtl/clusterip/setup.py
+1 -1
View File
@@ -4,7 +4,7 @@ import os
SCRIPT_DIR = os.path.dirname(os.path.abspath(__file__))
ip = ['archinfo', 'common', 'crc', 'i2c', 'ps2', 'pwm', 'rng', 'rtc', 'spi', 'timer', 'uart', 'wdg']
ip = ['archinfo', 'clint', 'common', 'crc', 'gpio', 'i2c', 'i2s', 'plic', 'ps2', 'pwm', 'rng', 'rtc', 'spi', 'timer', 'uart', 'wdg']
for v in ip:
# print(f'git clone git@github.com:retroSoC/{v}.git')
rtl/ip/native/ahbl2nmi.sv
+22 -20
View File
@@ -14,17 +14,17 @@ module ahbl2nmi (
nmi_if.master nmi
);
localparam TRANS_IDLE = 2'b00;
localparam TRANS_BUSY = 2'b01;
localparam TRANS_NONSEQ = 2'b10;
localparam TRANS_SEQ = 2'b11;
localparam AHBL_TRANS_IDLE = 2'b00;
localparam AHBL_TRANS_BUSY = 2'b01;
localparam AHBL_TRANS_NSEQ = 2'b10;
localparam AHBL_TRANS_SEQ = 2'b11;
localparam SIZE_BYTE = 3'b000;
localparam SIZE_HWORD = 3'b001;
localparam SIZE_WORD = 3'b010;
localparam AHBL_SIZE_BYTE = 3'b000;
localparam AHBL_SIZE_HWRD = 3'b001;
localparam AHBL_SIZE_WORD = 3'b010;
localparam RESP_OKAY = 1'b0;
localparam RESP_ERROR = 1'b1;
localparam AHBL_RESP_OKAY = 1'b0;
localparam AHBL_RESP_EROR = 1'b1;
localparam STATE_IDLE = 2'b00;
localparam STATE_DATA = 2'b01;
@@ -38,12 +38,13 @@ module ahbl2nmi (
logic [2:0] s_hsize_d, s_hsize_q;
// ahbl if
// NOTE: need to gurantee `ahbl.hready` and `ahbl.hrdata` sampled in same cycle
assign ahbl.hready = (s_fsm_q == STATE_IDLE) || nmi.ready;
assign ahbl.hresp = RESP_OKAY;
assign ahbl.hresp = AHBL_RESP_OKAY;
always_comb begin
ahbl.hrdata = '0;
unique case (s_hsize_q)
SIZE_BYTE: begin
AHBL_SIZE_BYTE: begin
unique case (s_haddr_q[1:0])
2'b00: ahbl.hrdata = {24'b0, nmi.rdata[7:0]};
2'b01: ahbl.hrdata = {24'b0, nmi.rdata[15:8]};
@@ -52,13 +53,13 @@ module ahbl2nmi (
default: ahbl.hrdata = {24'b0, nmi.rdata[7:0]};
endcase
end
SIZE_HWORD: begin
AHBL_SIZE_HWRD: begin
unique case (s_haddr_q[1])
1'b0: ahbl.hrdata = {16'b0, nmi.rdata[15:0]};
1'b1: ahbl.hrdata = {16'b0, nmi.rdata[31:16]};
endcase
end
SIZE_WORD: ahbl.hrdata = nmi.rdata;
AHBL_SIZE_WORD: ahbl.hrdata = nmi.rdata;
default: ahbl.hrdata = nmi.rdata;
endcase
end
@@ -71,7 +72,7 @@ module ahbl2nmi (
nmi.wdata = '0;
if (s_hwrite_q) begin
unique case (s_hsize_q)
SIZE_BYTE: begin
AHBL_SIZE_BYTE: begin
unique case (s_haddr_q[1:0])
2'b00: begin
nmi.wstrb = 4'b0001;
@@ -95,7 +96,7 @@ module ahbl2nmi (
end
endcase
end
SIZE_HWORD: begin
AHBL_SIZE_HWRD: begin
unique case (s_haddr_q[1])
1'b0: begin
nmi.wstrb = 4'b0011;
@@ -107,7 +108,7 @@ module ahbl2nmi (
end
endcase
end
SIZE_WORD: begin
AHBL_SIZE_WORD: begin
nmi.wstrb = 4'b1111;
nmi.wdata = ahbl.hwdata;
end
@@ -120,7 +121,7 @@ module ahbl2nmi (
end
// ahb.hready,
// ahb.hready,
always_comb begin
s_fsm_d = s_fsm_q;
s_haddr_d = s_haddr_q;
@@ -129,7 +130,7 @@ module ahbl2nmi (
unique case (s_fsm_q)
STATE_IDLE: begin
// just for no-burst ahbl
if (ahbl.htrans == TRANS_NONSEQ && ahbl.hburst == '0) begin
if (ahbl.htrans == AHBL_TRANS_NSEQ && ahbl.hburst == '0) begin
s_fsm_d = STATE_DATA;
s_haddr_d = ahbl.haddr;
s_hwrite_d = ahbl.hwrite;
@@ -138,7 +139,8 @@ module ahbl2nmi (
end
STATE_DATA: begin
if (~nmi.ready) s_fsm_d = STATE_WAIT;
else if (ahbl.htrans == TRANS_NONSEQ && ahbl.hburst == '0) begin
// nmi.ready == 1'b1
else if (ahbl.htrans == AHBL_TRANS_NSEQ && ahbl.hburst == '0) begin
s_fsm_d = STATE_DATA;
s_haddr_d = ahbl.haddr;
s_hwrite_d = ahbl.hwrite;
@@ -147,7 +149,7 @@ module ahbl2nmi (
end
STATE_WAIT: begin
if (nmi.ready) begin
if (ahbl.htrans == TRANS_NONSEQ && ahbl.hburst == '0) begin
if (ahbl.htrans == AHBL_TRANS_NSEQ && ahbl.hburst == '0) begin
s_fsm_d = STATE_DATA;
s_haddr_d = ahbl.haddr;
s_hwrite_d = ahbl.hwrite;
rtl/ip/native/clint.sv
+166
View File
@@ -0,0 +1,166 @@
// Copyright (c) 2023-2025 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef CLINT_DEF_SV
`define CLINT_DEF_SV
// verilog_format: off
`define NATV_CLINT_CLKDIV 8'h00
`define NATV_CLINT_MTIMEL 8'h04
`define NATV_CLINT_MTIMEH 8'h08
`define NATV_CLINT_MTIMECMPL 8'h0C
`define NATV_CLINT_MTIMECMPH 8'h10
`define NATV_CLINT_MSIP 8'h14
// verilog_format: on
`endif
interface simp_clint_if ();
logic tmr_irq_o;
logic sfr_irq_o;
modport dut(output tmr_irq_o, output sfr_irq_o);
endinterface
module nmi_clint (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
nmi_if.slave nmi,
simp_clint_if.dut clint
// verilog_format: on
);
logic s_nmi_wr_hdshk, s_nmi_rd_hdshk;
logic s_nmi_ready_d, s_nmi_ready_q;
logic s_nmi_rdata_en;
logic [31:0] s_nmi_rdata_d, s_nmi_rdata_q;
logic s_clint_clkdiv_en;
logic [7:0] s_clint_clkdiv_d, s_clint_clkdiv_q;
logic s_clint_mtime_en;
logic [63:0] s_clint_mtime_d, s_clint_mtime_q;
logic s_clint_mtimecmp_en;
logic [63:0] s_clint_mtimecmp_d, s_clint_mtimecmp_q;
logic s_clint_msip_en;
logic s_clint_msip_d, s_clint_msip_q;
// utils
logic [7:0] s_clk_cnt_d, s_clk_cnt_q;
assign s_nmi_wr_hdshk = nmi.valid && (~s_nmi_ready_q) && (|nmi.wstrb);
assign s_nmi_rd_hdshk = nmi.valid && (~s_nmi_ready_q) && (~(|nmi.wstrb));
assign nmi.ready = s_nmi_ready_q;
assign nmi.rdata = s_nmi_rdata_q;
assign clint.tmr_irq_o = s_clint_mtime_q >= s_clint_mtimecmp_q;
assign clint.sfr_irq_o = s_clint_msip_q;
assign s_clint_clkdiv_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_CLINT_CLKDIV;
assign s_clint_clkdiv_d = nmi.wdata[7:0];
dffer #(8) u_clint_clkdiv_dffer (
clk_i,
rst_n_i,
s_clint_clkdiv_en,
s_clint_clkdiv_d,
s_clint_clkdiv_q
);
always_comb begin
s_clk_cnt_d = s_clk_cnt_q;
if (s_clk_cnt_q == s_clint_clkdiv_q) begin
s_clk_cnt_d = '0;
end else begin
s_clk_cnt_d = s_clk_cnt_q + 1'b1;
end
end
dffr #(8) u_clk_cnt_dffr (
clk_i,
rst_n_i,
s_clk_cnt_d,
s_clk_cnt_q
);
assign s_clint_mtime_en = s_clk_cnt_q == s_clint_clkdiv_q;
assign s_clint_mtime_d = s_clint_mtime_q + 1'b1;
dffer #(64) u_clint_mtime_dffer (
clk_i,
rst_n_i,
s_clint_mtime_en,
s_clint_mtime_d,
s_clint_mtime_q
);
assign s_clint_mtimecmp_en = s_nmi_wr_hdshk && (nmi.addr[7:0] == `NATV_CLINT_MTIMECMPL || nmi.addr[7:0] == `NATV_CLINT_MTIMECMPH);
always_comb begin
s_clint_mtimecmp_d = s_clint_mtimecmp_q;
if (nmi.addr[7:0] == `NATV_CLINT_MTIMECMPL) begin
if (nmi.wstrb[0]) s_clint_mtimecmp_d[7:0] = nmi.wdata[7:0];
if (nmi.wstrb[1]) s_clint_mtimecmp_d[15:8] = nmi.wdata[15:8];
if (nmi.wstrb[2]) s_clint_mtimecmp_d[23:16] = nmi.wdata[23:16];
if (nmi.wstrb[3]) s_clint_mtimecmp_d[31:24] = nmi.wdata[31:24];
end else if (nmi.addr[7:0] == `NATV_CLINT_MTIMECMPH) begin
if (nmi.wstrb[0]) s_clint_mtimecmp_d[39:32] = nmi.wdata[7:0];
if (nmi.wstrb[1]) s_clint_mtimecmp_d[47:40] = nmi.wdata[15:8];
if (nmi.wstrb[2]) s_clint_mtimecmp_d[55:48] = nmi.wdata[23:16];
if (nmi.wstrb[3]) s_clint_mtimecmp_d[63:56] = nmi.wdata[31:24];
end
end
dfferh #(64) u_clint_mtimecmp_dfferh (
clk_i,
rst_n_i,
s_clint_mtimecmp_en,
s_clint_mtimecmp_d,
s_clint_mtimecmp_q
);
assign s_clint_msip_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_CLINT_MSIP;
assign s_clint_msip_d = nmi.wdata[0];
dffer #(1) u_clint_msip_dffer(
clk_i,
rst_n_i,
s_clint_msip_en,
s_clint_msip_d,
s_clint_msip_q
);
assign s_nmi_ready_d = nmi.valid && (~s_nmi_ready_q);
dffr #(1) u_nmi_ready_dffr (
clk_i,
rst_n_i,
s_nmi_ready_d,
s_nmi_ready_q
);
assign s_nmi_rdata_en = s_nmi_rd_hdshk;
always_comb begin
s_nmi_rdata_d = s_nmi_rdata_q;
unique case (nmi.addr[7:0])
`NATV_CLINT_CLKDIV: s_nmi_rdata_d = {24'd0, s_clint_clkdiv_q};
`NATV_CLINT_MTIMEL: s_nmi_rdata_d = s_clint_mtime_q[31:0];
`NATV_CLINT_MTIMEH: s_nmi_rdata_d = s_clint_mtime_q[63:32];
`NATV_CLINT_MTIMECMPL: s_nmi_rdata_d = s_clint_mtimecmp_q[31:0];
`NATV_CLINT_MTIMECMPH: s_nmi_rdata_d = s_clint_mtimecmp_q[63:32];
`NATV_CLINT_MSIP: s_nmi_rdata_d = {31'd0, s_clint_msip_q};
default: s_nmi_rdata_d = s_nmi_rdata_q;
endcase
end
dffer #(32) u_nmi_rdata_dffer (
clk_i,
rst_n_i,
s_nmi_rdata_en,
s_nmi_rdata_d,
s_nmi_rdata_q
);
endmodule
rtl/mini/csrc/Emulator.cpp
+1
View File
@@ -51,6 +51,7 @@ Emulator::Emulator(cxxopts::ParseResult &res)
flash_init(args.image.c_str());
dutPtr = new Vretrosoc_top;
dutPtr->core_sel_i = 0;
reset();
if (args.dumpWave)
rtl/mini/filelist/ip.fl
+1
View File
@@ -77,6 +77,7 @@
../../ip/native/dma_core.sv
../../ip/native/dma.sv
../../ip/native/sysctrl.sv
../../ip/native/clint.sv
../../ip/native/simple_timer.sv
../../ip/native/simple_uart.sv
../../ip/native/simple_gpio.sv
rtl/mini/script/software.mk
+1
View File
@@ -104,6 +104,7 @@ LDS_PATH := $(ROOT_PATH)/crt/flash_$(LINK_TYPE).lds
asm:
cd app/asm && make
cp -rf app/asm/hello-asm.flash .sw_build/retrosoc_fw.hex
cp -rf app/asm/hello-asm.bin .sw_build/retrosoc_fw.bin
firmware:
@mkdir -p .sw_build
rtl/mini/tb/retrosoc_tb.sv
+2 -1
View File
@@ -295,8 +295,9 @@ module retrosoc_tb;
$fsdbDumpfile("retrosoc_tb.fsdb");
$fsdbDumpvars(0);
$fsdbDumpMDA();
#398844962;
// #398844962;
// #867652;
#21149063;
// #1667652;
// #327820116;
// #327179489;
rtl/mini/top/ip_natv_wrapper.sv
+18 -2
View File
@@ -29,6 +29,7 @@ module ip_natv_wrapper (
qspi_if.dut qspi,
nmi_if.master dma_nmi,
sysctrl_if.dut sysctrl,
simp_clint_if.dut clint,
// irq
output logic [2:0] irq_o
// verilog_format: on
@@ -46,6 +47,7 @@ module ip_natv_wrapper (
nmi_if u_qspi_nmi_if ();
nmi_if u_dma_nmi_if ();
nmi_if u_sysctrl_nmi_if ();
nmi_if u_clint_nmi_if ();
dma_hw_trg_if u_dma_hw_trg_if ();
@@ -127,6 +129,11 @@ module ip_natv_wrapper (
assign u_sysctrl_nmi_if.wdata = nmi.wdata;
assign u_sysctrl_nmi_if.wstrb = nmi.wstrb;
assign u_clint_nmi_if.valid = nmi.valid && (nmi.addr[31:28] == `NATV_IP_START && nmi.addr[15:8] == `NMI_CLINT_START);
assign u_clint_nmi_if.addr = nmi.addr;
assign u_clint_nmi_if.wdata = nmi.wdata;
assign u_clint_nmi_if.wstrb = nmi.wstrb;
// verilog_format: off
assign nmi.ready = (u_gpio_nmi_if.valid & u_gpio_nmi_if.ready) |
(u_uart_nmi_if.valid & u_uart_nmi_if.ready) |
@@ -139,7 +146,8 @@ module ip_natv_wrapper (
(u_onewire_nmi_if.valid & u_onewire_nmi_if.ready) |
(u_qspi_nmi_if.valid & u_qspi_nmi_if.ready) |
(u_dma_nmi_if.valid & u_dma_nmi_if.ready) |
(u_sysctrl_nmi_if.valid & u_sysctrl_nmi_if.ready);
(u_sysctrl_nmi_if.valid & u_sysctrl_nmi_if.ready) |
(u_clint_nmi_if.valid & u_clint_nmi_if.ready);
assign nmi.rdata = ({32{(u_gpio_nmi_if.valid & u_gpio_nmi_if.ready)}} & u_gpio_nmi_if.rdata) |
({32{(u_uart_nmi_if.valid & u_uart_nmi_if.ready)}} & u_uart_nmi_if.rdata) |
@@ -152,7 +160,8 @@ module ip_natv_wrapper (
({32{(u_onewire_nmi_if.valid & u_onewire_nmi_if.ready)}} & u_onewire_nmi_if.rdata) |
({32{(u_qspi_nmi_if.valid & u_qspi_nmi_if.ready)}} & u_qspi_nmi_if.rdata) |
({32{(u_dma_nmi_if.valid & u_dma_nmi_if.ready)}} & u_dma_nmi_if.rdata) |
({32{(u_sysctrl_nmi_if.valid & u_sysctrl_nmi_if.ready)}} & u_sysctrl_nmi_if.rdata);
({32{(u_sysctrl_nmi_if.valid & u_sysctrl_nmi_if.ready)}} & u_sysctrl_nmi_if.rdata) |
({32{(u_clint_nmi_if.valid & u_clint_nmi_if.ready)}} & u_clint_nmi_if.rdata);
// verilog_format: on
assign irq_o[0] = uart.irq_o;
@@ -248,4 +257,11 @@ module ip_natv_wrapper (
.nmi (u_sysctrl_nmi_if),
.sysctrl(sysctrl)
);
nmi_clint u_nmi_clint (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.nmi (u_clint_nmi_if),
.clint (clint)
);
endmodule
rtl/mini/top/mmap_define.svh
+1
View File
@@ -40,6 +40,7 @@
`define NMI_QSPI_START 8'h90
`define NMI_DMA_START 8'hA0
`define NMI_SYSCTRL_START 8'hB0
`define NMI_CLINT_START 8'hC0
// APB IP REG ADDR
`define APB_ARCHINFO_START 8'h00
`define APB_RNG_START 8'h10
rtl/mini/top/retrosoc.sv
+9 -9
View File
@@ -54,6 +54,7 @@ module retrosoc (
qspi_if u_natv_qspi_if();
qspi_if u_apb_qspi_if();
sysctrl_if u_sysctrl_if();
simp_clint_if u_clint_if();
// verilog_format: on
// irq
@@ -89,15 +90,13 @@ module retrosoc (
assign qspi.spi_io_out_o = ~u_sysctrl_if.qspi_sel_o ? u_natv_qspi_if.spi_io_out_o : u_apb_qspi_if.spi_io_out_o;
assign qspi.irq_o = '0;
// PicoRV32 built-in interrupt
// 0 Timer Interrupt
// 1 EBREAK/ECALL or Illegal Instruction
// 2 BUS Error (Unalign Memory Access)
assign s_irq[4:0] = 5'd0;
assign s_irq[5] = extn_irq_i;
assign s_irq[8:6] = s_natv_irq;
assign s_irq[17:9] = s_apb_irq;
assign s_irq[31:18] = 14'd0;
// interrupt
assign s_irq[0] = u_clint_if.tmr_irq_o;
assign s_irq[1] = u_clint_if.sfr_irq_o;
assign s_irq[2] = extn_irq_i;
assign s_irq[5:3] = s_natv_irq;
assign s_irq[14:6] = s_apb_irq;
assign s_irq[31:15] = 17'd0;
// verilog_format: on
core_wrapper u_core_wrapper (
@@ -138,6 +137,7 @@ module retrosoc (
.qspi (u_natv_qspi_if),
.dma_nmi (u_dma_nmi_if),
.sysctrl (u_sysctrl_if),
.clint (u_clint_if),
.irq_o (s_natv_irq)
);
rtl/mini/top/user_core_top.sv
+31 -13
View File
@@ -24,7 +24,10 @@ module user_core_top (
// verilog_format: off
nmi_if u_user_1_nmi_if ();
nmi_if u_user_2_nmi_if ();
logic [31:0] s_user_1_irq, s_user_2_irq;
nmi_if u_user_3_nmi_if ();
logic [31:0] s_user_1_irq;
logic [31:0] s_user_2_irq;
logic [31:0] s_user_3_irq;
// ...
// verilog_format: on
always_comb begin
@@ -38,6 +41,9 @@ module user_core_top (
u_user_2_nmi_if.rdata = '0;
u_user_2_nmi_if.ready = '0;
s_user_2_irq = '0;
u_user_3_nmi_if.rdata = '0;
u_user_3_nmi_if.ready = '0;
s_user_3_irq = '0;
unique case (sel_i)
5'd1: begin
nmi.valid = u_user_1_nmi_if.valid;
@@ -57,6 +63,15 @@ module user_core_top (
u_user_2_nmi_if.ready = nmi.ready;
s_user_2_irq = irq_i;
end
5'd3: begin
nmi.valid = u_user_3_nmi_if.valid;
nmi.addr = u_user_3_nmi_if.addr;
nmi.wdata = u_user_3_nmi_if.wdata;
nmi.wstrb = u_user_3_nmi_if.wstrb;
u_user_3_nmi_if.rdata = nmi.rdata;
u_user_3_nmi_if.ready = nmi.ready;
s_user_3_irq = irq_i;
end
default: begin
nmi.valid = '0;
nmi.addr = '0;
@@ -68,6 +83,9 @@ module user_core_top (
u_user_2_nmi_if.rdata = '0;
u_user_2_nmi_if.ready = '0;
s_user_2_irq = '0;
u_user_3_nmi_if.rdata = '0;
u_user_3_nmi_if.ready = '0;
s_user_3_irq = '0;
end
endcase
end
@@ -80,18 +98,18 @@ module user_core_top (
.nmi (u_user_1_nmi_if)
);
// user_core_design_username2 #(2) u_user_core_design_username2 (
// .clk_i (clk_i),
// .rst_n_i(rst_n_i),
// .irq_i (s_user_2_irq),
// .nmi (u_user_2_nmi_if)
// );
user_core_design_username2 #(2) u_user_core_design_username2 (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.irq_i (s_user_2_irq),
.nmi (u_user_2_nmi_if)
);
// user_core_design_username2 #(3) u_user_core_design_username3 (
// .clk_i (clk_i),
// .rst_n_i(rst_n_i),
// .irq_i (s_user_2_irq),
// .nmi (u_user_2_nmi_if)
// );
user_core_design_username3 #(3) u_user_core_design_username3 (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.irq_i (s_user_3_irq),
.nmi (u_user_3_nmi_if)
);
endmodule
rtl/mini/vsrc/retrosoc_top.sv
+24 -21
View File
@@ -21,27 +21,30 @@
`timescale 1 ns / 1 ps
module retrosoc_top (
input wire ext_clk_i,
input wire rst_n_i
input wire ext_clk_i,
input wire rst_n_i,
input wire [4:0] core_sel_i
);
wire s_clk;
wire s_rst_n;
wire s_clk_bypass;
wire s_uart_tx;
wire s_psram_sck;
wire s_psram_nss0;
wire s_psram_dat0;
wire s_psram_dat1;
wire s_psram_dat2;
wire s_psram_dat3;
wire s_spfs_sck;
wire s_spfs_nss;
wire s_spfs_mosi;
wire s_spfs_miso;
wire s_clk;
wire s_rst_n;
wire [4:0] s_core_sel;
wire s_clk_bypass;
wire s_uart_tx;
wire s_psram_sck;
wire s_psram_nss0;
wire s_psram_dat0;
wire s_psram_dat1;
wire s_psram_dat2;
wire s_psram_dat3;
wire s_spfs_sck;
wire s_spfs_nss;
wire s_spfs_mosi;
wire s_spfs_miso;
assign s_clk = ext_clk_i;
assign s_rst_n = rst_n_i;
assign s_core_sel = core_sel_i;
assign s_clk_bypass = 1'b1;
retrosoc_asic u_retrosoc_asic (
.xi_i_pad (),
@@ -51,11 +54,11 @@ module retrosoc_top (
.tmr_capch_i_pad (),
.extn_irq_i_pad (),
`ifdef CORE_MDD
.core_sel_0_i_pad (),
.core_sel_1_i_pad (),
.core_sel_2_i_pad (),
.core_sel_3_i_pad (),
.core_sel_4_i_pad (),
.core_sel_0_i_pad (s_core_sel[0]),
.core_sel_1_i_pad (s_core_sel[1]),
.core_sel_2_i_pad (s_core_sel[2]),
.core_sel_3_i_pad (s_core_sel[3]),
.core_sel_4_i_pad (s_core_sel[4]),
`endif
`ifdef IP_MDD
.user_gpio_0_io_pad (),
sta/mini/retrosoc_gen2.sdc
+159
View File
@@ -0,0 +1,159 @@
set sdc_version 2.1
set_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm
###############################################################################
#
# Units
# capacitive_load_unit : 1 pF
# current_unit : 0.001 A
# resistance_unit : 1 kOhm
# time_unit : 1 ns
# voltage_unit : 1 V
###############################################################################
set_operating_conditions -analysis_type on_chip_variation -library [get_libs {ETSCA_N55_H7BH_DSS_PRCMAX_V1P0_T125.db:ETSCA_N55_H7BH_DSS_PRCMAX_V1P0_T125}]
###############################################################################
# Clock Related Information
###############################################################################
create_clock -name CLK_u_xtal_io_pad_u_P65_1233_PWE_XC -period 41.666668 -waveform { 0 20.833334 } [get_pins {u_xtal_io_pad.u_P65_1233_PWE/XC}]
set_clock_uncertainty -setup 0.2 [get_clocks {CLK_u_xtal_io_pad_u_P65_1233_PWE_XC}]
set_clock_uncertainty -hold 0.1 [get_clocks {CLK_u_xtal_io_pad_u_P65_1233_PWE_XC}]
create_clock -name CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C -period 10 -waveform { 0 5 } [get_pins {u_extclk_i_pad.u_P65_1233_PBMUX/C}]
set_clock_uncertainty -setup 0.2 [get_clocks {CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C}]
set_clock_uncertainty -hold 0.1 [get_clocks {CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C}]
create_clock -name CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y -period 41.666668 -waveform { 0 20.833334 } [get_pins {u_rcu.u_pll_clk_buf.u_BUFX0P7H7L/Y}]
set_clock_uncertainty -setup 0.2 [get_clocks {CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y}]
set_clock_uncertainty -hold 0.1 [get_clocks {CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y}]
create_clock -name u_audclk_i_pad.u_P65_1233_PBMUX_C -period 81.380 -waveform { 0 40.690 } [get_pins {u_audclk_i_pad.u_P65_1233_PBMUX/C}]
set_clock_uncertainty -setup 0.2 [get_clocks {u_audclk_i_pad.u_P65_1233_PBMUX_C}]
set_clock_uncertainty -hold 0.1 [get_clocks {u_audclk_i_pad.u_P65_1233_PBMUX_C}]
set_timing_derate -cell_delay -net_delay -late 1
set_timing_derate -net_delay -clock -early 0.95
set_timing_derate -net_delay -data -early 1
set_timing_derate -net_delay -clock -early 0.95
set_timing_derate -net_delay -data -early 1
set_timing_derate -cell_delay -clock -early 0.95
set_timing_derate -cell_delay -data -early 1
###############################################################################
# Derived Clock related information
###############################################################################
# create_generated_clock -name CLK_sys_clk_buf -source [get_pins {u_rcu.u_ext_clk_buf.u_BUFX0P7H7L/Y}] -divide_by 1 -add -master_clock [get_clocks {CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C}] [get_pins {u_rcu.u_sys_clk_buf.u_BUFX0P7H7L/Y}]
# set_clock_uncertainty -setup 0.2 [get_clocks {CLK_sys_clk_buf}]
# set_clock_uncertainty -hold 0.1 [get_clocks {CLK_sys_clk_buf}]
# create_generated_clock -name CLK_cust_qspi_spi_clk_o -source [get_pins {u_rcu.u_sys_clk_buf.u_BUFX0P7H7L/Y}] -divide_by 2 [get_ports {cust_qspi_spi_clk_o_pad}]
# set_clock_uncertainty -setup 0.2 [get_clocks {CLK_cust_qspi_spi_clk_o}]
# set_clock_uncertainty -hold 0.1 [get_clocks {CLK_cust_qspi_spi_clk_o}]
# create_generated_clock -name CLK_cust_spfs_clk_o -source [get_pins {u_rcu.u_sys_clk_buf.u_BUFX0P7H7L/Y}] -divide_by 2 [get_ports {cust_spfs_clk_o_pad}]
# set_clock_uncertainty -setup 0.2 [get_clocks {CLK_cust_spfs_clk_o}]
# set_clock_uncertainty -hold 0.1 [get_clocks {CLK_cust_spfs_clk_o}]
# create_generated_clock -name CLK_cust_psram_sclk_o -source [get_pins {u_rcu.u_sys_clk_buf.u_BUFX0P7H7L/Y}] -divide_by 2 [get_ports {cust_psram_sclk_o_pad}]
# set_clock_uncertainty -setup 0.2 [get_clocks {CLK_cust_psram_sclk_o}]
# set_clock_uncertainty -hold 0.1 [get_clocks {CLK_cust_psram_sclk_o}]
# set_clock_groups -asynchronous -name CLK_u_xtal_io_pad_u_P65_1233_PWE_XC_1 -group [get_clocks {CLK_u_xtal_io_pad_u_P65_1233_PWE_XC}] -group [get_clocks {CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C CLK_sys_clk_buf CLK_cust_qspi_spi_clk_o CLK_cust_psram_sclk_o CLK_cust_spfs_clk_o}] -group [get_clocks {CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y}]
###############################################################################
# Point to Point exceptions
###############################################################################
# group_path -name CLK_u_xtal_io_pad_u_P65_1233_PWE_XC_in2reg -from [get_ports {xi_i_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_rx_i_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_miso_i_pad}] -to [get_clocks {CLK_u_xtal_io_pad_u_P65_1233_PWE_XC}]
# group_path -name CLK_u_xtal_io_pad_u_P65_1233_PWE_XC_reg2out -from [get_clocks {CLK_u_xtal_io_pad_u_P65_1233_PWE_XC}] -to [get_ports {xo_o_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad sys_clkdiv4_o_pad uart_tx_o_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_tx_o_pad cust_uart_rx_i_pad cust_pwm_pwm_0_o_pad cust_pwm_pwm_1_o_pad cust_pwm_pwm_2_o_pad cust_pwm_pwm_3_o_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_spi_clk_o_pad cust_qspi_spi_csn_0_o_pad cust_qspi_spi_csn_1_o_pad cust_qspi_spi_csn_2_o_pad cust_qspi_spi_csn_3_o_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sclk_o_pad cust_psram_ce_o_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_clk_o_pad cust_spfs_cs_o_pad cust_spfs_mosi_o_pad cust_spfs_miso_i_pad}]
# group_path -name CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C_in2reg -from [get_ports {xi_i_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_rx_i_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_miso_i_pad}] -to [get_clocks {CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C}]
# group_path -name CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C_reg2out -from [get_clocks {CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C}] -to [get_ports {xo_o_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad sys_clkdiv4_o_pad uart_tx_o_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_tx_o_pad cust_uart_rx_i_pad cust_pwm_pwm_0_o_pad cust_pwm_pwm_1_o_pad cust_pwm_pwm_2_o_pad cust_pwm_pwm_3_o_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_spi_clk_o_pad cust_qspi_spi_csn_0_o_pad cust_qspi_spi_csn_1_o_pad cust_qspi_spi_csn_2_o_pad cust_qspi_spi_csn_3_o_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sclk_o_pad cust_psram_ce_o_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_clk_o_pad cust_spfs_cs_o_pad cust_spfs_mosi_o_pad cust_spfs_miso_i_pad}]
# group_path -name CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y_in2reg -from [get_ports {xi_i_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_rx_i_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_miso_i_pad}] -to [get_clocks {CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y}]
# group_path -name CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y_reg2out -from [get_clocks {CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y}] -to [get_ports {xo_o_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad sys_clkdiv4_o_pad uart_tx_o_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_tx_o_pad cust_uart_rx_i_pad cust_pwm_pwm_0_o_pad cust_pwm_pwm_1_o_pad cust_pwm_pwm_2_o_pad cust_pwm_pwm_3_o_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_spi_clk_o_pad cust_qspi_spi_csn_0_o_pad cust_qspi_spi_csn_1_o_pad cust_qspi_spi_csn_2_o_pad cust_qspi_spi_csn_3_o_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sclk_o_pad cust_psram_ce_o_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_clk_o_pad cust_spfs_cs_o_pad cust_spfs_mosi_o_pad cust_spfs_miso_i_pad}]
# group_path -name CLK_sys_clk_buf_in2reg -from [get_ports {xi_i_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_rx_i_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_miso_i_pad}] -to [get_clocks {CLK_sys_clk_buf}]
# group_path -name CLK_sys_clk_buf_reg2out -from [get_clocks {CLK_sys_clk_buf}] -to [get_ports {xo_o_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad sys_clkdiv4_o_pad uart_tx_o_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_tx_o_pad cust_uart_rx_i_pad cust_pwm_pwm_0_o_pad cust_pwm_pwm_1_o_pad cust_pwm_pwm_2_o_pad cust_pwm_pwm_3_o_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_spi_clk_o_pad cust_qspi_spi_csn_0_o_pad cust_qspi_spi_csn_1_o_pad cust_qspi_spi_csn_2_o_pad cust_qspi_spi_csn_3_o_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sclk_o_pad cust_psram_ce_o_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_clk_o_pad cust_spfs_cs_o_pad cust_spfs_mosi_o_pad cust_spfs_miso_i_pad}]
# group_path -name CLK_cust_qspi_spi_clk_o_in2reg -from [get_ports {xi_i_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_rx_i_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_miso_i_pad}] -to [get_clocks {CLK_cust_qspi_spi_clk_o}]
# group_path -name CLK_cust_qspi_spi_clk_o_reg2out -from [get_clocks {CLK_cust_qspi_spi_clk_o}] -to [get_ports {xo_o_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad sys_clkdiv4_o_pad uart_tx_o_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_tx_o_pad cust_uart_rx_i_pad cust_pwm_pwm_0_o_pad cust_pwm_pwm_1_o_pad cust_pwm_pwm_2_o_pad cust_pwm_pwm_3_o_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_spi_clk_o_pad cust_qspi_spi_csn_0_o_pad cust_qspi_spi_csn_1_o_pad cust_qspi_spi_csn_2_o_pad cust_qspi_spi_csn_3_o_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sclk_o_pad cust_psram_ce_o_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_clk_o_pad cust_spfs_cs_o_pad cust_spfs_mosi_o_pad cust_spfs_miso_i_pad}]
# group_path -name CLK_cust_psram_sclk_o_in2reg -from [get_ports {xi_i_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_rx_i_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_miso_i_pad}] -to [get_clocks {CLK_cust_psram_sclk_o}]
# group_path -name CLK_cust_psram_sclk_o_reg2out -from [get_clocks {CLK_cust_psram_sclk_o}] -to [get_ports {xo_o_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad sys_clkdiv4_o_pad uart_tx_o_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_tx_o_pad cust_uart_rx_i_pad cust_pwm_pwm_0_o_pad cust_pwm_pwm_1_o_pad cust_pwm_pwm_2_o_pad cust_pwm_pwm_3_o_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_spi_clk_o_pad cust_qspi_spi_csn_0_o_pad cust_qspi_spi_csn_1_o_pad cust_qspi_spi_csn_2_o_pad cust_qspi_spi_csn_3_o_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sclk_o_pad cust_psram_ce_o_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_clk_o_pad cust_spfs_cs_o_pad cust_spfs_mosi_o_pad cust_spfs_miso_i_pad}]
# group_path -name CLK_cust_spfs_clk_o_in2reg -from [get_ports {xi_i_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_rx_i_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_miso_i_pad}] -to [get_clocks {CLK_cust_spfs_clk_o}]
# group_path -name CLK_cust_spfs_clk_o_reg2out -from [get_clocks {CLK_cust_spfs_clk_o}] -to [get_ports {xo_o_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad sys_clkdiv4_o_pad uart_tx_o_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_tx_o_pad cust_uart_rx_i_pad cust_pwm_pwm_0_o_pad cust_pwm_pwm_1_o_pad cust_pwm_pwm_2_o_pad cust_pwm_pwm_3_o_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_spi_clk_o_pad cust_qspi_spi_csn_0_o_pad cust_qspi_spi_csn_1_o_pad cust_qspi_spi_csn_2_o_pad cust_qspi_spi_csn_3_o_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sclk_o_pad cust_psram_ce_o_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_clk_o_pad cust_spfs_cs_o_pad cust_spfs_mosi_o_pad cust_spfs_miso_i_pad}]
# group_path -name all_in2out -from [get_ports {xi_i_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_rx_i_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_miso_i_pad}] -to [get_ports {xo_o_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad sys_clkdiv4_o_pad uart_tx_o_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_tx_o_pad cust_uart_rx_i_pad cust_pwm_pwm_0_o_pad cust_pwm_pwm_1_o_pad cust_pwm_pwm_2_o_pad cust_pwm_pwm_3_o_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_spi_clk_o_pad cust_qspi_spi_csn_0_o_pad cust_qspi_spi_csn_1_o_pad cust_qspi_spi_csn_2_o_pad cust_qspi_spi_csn_3_o_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sclk_o_pad cust_psram_ce_o_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_clk_o_pad cust_spfs_cs_o_pad cust_spfs_mosi_o_pad cust_spfs_miso_i_pad}]
# set_case_analysis 1 [get_pins {u_rcu.u_sys_mux.u_MUX2X0P5H7L/S0}]
# set_load -pin_load 8 [get_ports {xo_o_pad}]
# set_load -pin_load 8 [get_ports {extclk_i_pad}]
# set_load -pin_load 8 [get_ports {pll_cfg_0_i_pad}]
# set_load -pin_load 8 [get_ports {pll_cfg_1_i_pad}]
# set_load -pin_load 8 [get_ports {pll_cfg_2_i_pad}]
# set_load -pin_load 8 [get_ports {clk_bypass_i_pad}]
# set_load -pin_load 8 [get_ports {ext_rst_n_i_pad}]
# set_load -pin_load 8 [get_ports {sys_clkdiv4_o_pad}]
# set_load -pin_load 8 [get_ports {uart_tx_o_pad}]
# set_load -pin_load 8 [get_ports {uart_rx_i_pad}]
# set_load -pin_load 8 [get_ports {gpio_0_io_pad}]
# set_load -pin_load 8 [get_ports {gpio_1_io_pad}]
# set_load -pin_load 8 [get_ports {gpio_2_io_pad}]
# set_load -pin_load 8 [get_ports {gpio_3_io_pad}]
# set_load -pin_load 8 [get_ports {gpio_4_io_pad}]
# set_load -pin_load 8 [get_ports {gpio_5_io_pad}]
# set_load -pin_load 8 [get_ports {gpio_6_io_pad}]
# set_load -pin_load 8 [get_ports {gpio_7_io_pad}]
# set_load -pin_load 8 [get_ports {gpio_8_io_pad}]
# set_load -pin_load 8 [get_ports {gpio_9_io_pad}]
# set_load -pin_load 8 [get_ports {gpio_10_io_pad}]
# set_load -pin_load 8 [get_ports {gpio_11_io_pad}]
# set_load -pin_load 8 [get_ports {gpio_12_io_pad}]
# set_load -pin_load 8 [get_ports {gpio_13_io_pad}]
# set_load -pin_load 8 [get_ports {gpio_14_io_pad}]
# set_load -pin_load 8 [get_ports {gpio_15_io_pad}]
# set_load -pin_load 8 [get_ports {irq_pin_i_pad}]
# set_load -pin_load 8 [get_ports {cust_uart_tx_o_pad}]
# set_load -pin_load 8 [get_ports {cust_uart_rx_i_pad}]
# set_load -pin_load 8 [get_ports {cust_pwm_pwm_0_o_pad}]
# set_load -pin_load 8 [get_ports {cust_pwm_pwm_1_o_pad}]
# set_load -pin_load 8 [get_ports {cust_pwm_pwm_2_o_pad}]
# set_load -pin_load 8 [get_ports {cust_pwm_pwm_3_o_pad}]
# set_load -pin_load 8 [get_ports {cust_ps2_ps2_clk_i_pad}]
# set_load -pin_load 8 [get_ports {cust_ps2_ps2_dat_i_pad}]
# set_load -pin_load 8 [get_ports {cust_i2c_scl_io_pad}]
# set_load -pin_load 8 [get_ports {cust_i2c_sda_io_pad}]
# set_load -pin_load 8 [get_ports {cust_qspi_spi_clk_o_pad}]
# set_load -pin_load 8 [get_ports {cust_qspi_spi_csn_0_o_pad}]
# set_load -pin_load 8 [get_ports {cust_qspi_spi_csn_1_o_pad}]
# set_load -pin_load 8 [get_ports {cust_qspi_spi_csn_2_o_pad}]
# set_load -pin_load 8 [get_ports {cust_qspi_spi_csn_3_o_pad}]
# set_load -pin_load 8 [get_ports {cust_qspi_dat_0_io_pad}]
# set_load -pin_load 8 [get_ports {cust_qspi_dat_1_io_pad}]
# set_load -pin_load 8 [get_ports {cust_qspi_dat_2_io_pad}]
# set_load -pin_load 8 [get_ports {cust_qspi_dat_3_io_pad}]
# set_load -pin_load 8 [get_ports {cust_psram_sclk_o_pad}]
# set_load -pin_load 8 [get_ports {cust_psram_ce_o_pad}]
# set_load -pin_load 8 [get_ports {cust_psram_sio0_io_pad}]
# set_load -pin_load 8 [get_ports {cust_psram_sio1_io_pad}]
# set_load -pin_load 8 [get_ports {cust_psram_sio2_io_pad}]
# set_load -pin_load 8 [get_ports {cust_psram_sio3_io_pad}]
# set_load -pin_load 8 [get_ports {cust_spfs_clk_o_pad}]
# set_load -pin_load 8 [get_ports {cust_spfs_cs_o_pad}]
# set_load -pin_load 8 [get_ports {cust_spfs_mosi_o_pad}]
# set_load -pin_load 8 [get_ports {cust_spfs_miso_i_pad}]
# set_wire_load_mode top
# set_max_fanout 32 [current_design]
# set_max_transition 1.7 [get_clocks {CLK_sys_clk_buf}] -clock_path -rise
# set_max_transition 1.7 [get_clocks {CLK_sys_clk_buf}] -clock_path -fall
# set_max_transition 3.4 [get_clocks {CLK_sys_clk_buf}] -data_path -rise
# set_max_transition 3.4 [get_clocks {CLK_sys_clk_buf}] -data_path -fall
# set_max_transition 3.4 [get_clocks {CLK_cust_qspi_spi_clk_o}] -clock_path -rise
# set_max_transition 3.4 [get_clocks {CLK_cust_qspi_spi_clk_o}] -clock_path -fall
# set_max_transition 6.8 [get_clocks {CLK_cust_qspi_spi_clk_o}] -data_path -rise
# set_max_transition 6.8 [get_clocks {CLK_cust_qspi_spi_clk_o}] -data_path -fall
# set_max_transition 7.083333 [get_clocks {CLK_u_xtal_io_pad_u_P65_1233_PWE_XC}] -clock_path -rise
# set_max_transition 7.083333 [get_clocks {CLK_u_xtal_io_pad_u_P65_1233_PWE_XC}] -clock_path -fall
# set_max_transition 14.166667 [get_clocks {CLK_u_xtal_io_pad_u_P65_1233_PWE_XC}] -data_path -rise
# set_max_transition 14.166667 [get_clocks {CLK_u_xtal_io_pad_u_P65_1233_PWE_XC}] -data_path -fall
# set_max_transition 3.4 [get_clocks {CLK_cust_psram_sclk_o}] -clock_path -rise
# set_max_transition 3.4 [get_clocks {CLK_cust_psram_sclk_o}] -clock_path -fall
# set_max_transition 6.8 [get_clocks {CLK_cust_psram_sclk_o}] -data_path -rise
# set_max_transition 6.8 [get_clocks {CLK_cust_psram_sclk_o}] -data_path -fall
# set_max_transition 1.7 [get_clocks {CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C}] -clock_path -rise
# set_max_transition 1.7 [get_clocks {CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C}] -clock_path -fall
# set_max_transition 3.4 [get_clocks {CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C}] -data_path -rise
# set_max_transition 3.4 [get_clocks {CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C}] -data_path -fall
# set_max_transition 3.4 [get_clocks {CLK_cust_spfs_clk_o}] -clock_path -rise
# set_max_transition 3.4 [get_clocks {CLK_cust_spfs_clk_o}] -clock_path -fall
# set_max_transition 6.8 [get_clocks {CLK_cust_spfs_clk_o}] -data_path -rise
# set_max_transition 6.8 [get_clocks {CLK_cust_spfs_clk_o}] -data_path -fall
# set_max_transition 7.083333 [get_clocks {CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y}] -clock_path -rise
# set_max_transition 7.083333 [get_clocks {CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y}] -clock_path -fall
# set_max_transition 14.166667 [get_clocks {CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y}] -data_path -rise
# set_max_transition 14.166667 [get_clocks {CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y}] -data_path -fall
# ###############################################################################
# # POCV Information
# ###############################################################################
sta/mini/retrosoc_gen2.tcl
+17
View File
@@ -0,0 +1,17 @@
# read lib
read_liberty /nfs/share/home/zhuangchunan/proj/Flow_CX55/lib_data/ccslib/ics55_LLSC_H7CH_ss_rcworst_1p08_125_nldm.lib
read_liberty /nfs/share/home/zhuangchunan/proj/Flow_CX55/lib_data/ccslib/ics55_LLSC_H7CL_ss_rcworst_1p08_125_nldm.lib
read_liberty /nfs/share/home/zhuangchunan/proj/Flow_CX55/lib_data/ccslib/ics55_LLSC_H7CR_ss_rcworst_1p08_125_nldm.lib
read_liberty /nfs/share/home/zhuangchunan/proj/Flow_CX55/lib_data/ccslib/ICSIOA_N55_3P3_ss_1p08_2p97_125c.lib
read_verilog /nfs/share/home/zhaoxueyan/dataset_gj_test26/retrosoc_asic-cx55/retrosoc_asic_yosys.v
link_design retrosoc_asic
# read sdc
read_sdc retrosoc_gen2.sdc
report_checks -path_delay min_max -path_group {CLK_src_xtal CLK_src_ext CLK_xtal_buf CLK_ext_buf CLK_pll CLK_pll_buf CLK_sys_mux_pll CLK_sys_mux_ext CLK_sys_clk_buf CLK_flash_clk_o CLK_cust_qspi_spi_clk_o CLK_cust_psram_sclk_o CLK_cust_spfs_clk_o} -sort_by_slack -slack_max 0.0 -group_path_count 50000 -endpoint_path_count 50000 > retrosoc_sta.log
# set_propagated_clock clk
# read_spef gcd_sky130hd.spef
# set_power_activity -input -activity .1
# set_power_activity -input_port reset -activity 0
# report_power