fix(ci): raise the Mini ci_smoke SDRAM Verilator budget to 7200s

The merged HP subsystem makes the Mini ci_smoke ld2_sdram Verilator step
need roughly 4400 s locally (SIM_TEST_PASS code=0 in 4389 s,
build/ics55-2026-10-23-15-17-2e059475a01b/), so hosted runners time out the
existing 3600 s tier during the crypto self-test on ICS55/SKY130/GF180
(jobs 120251738572, 120251738799, 120251738649). Double the tier to 7200 s;
the ld2_all_sram step stays at 3600 s (measured need about half of that).
Validation-only budget change with the two contract assertions pinned to the
new values; no RTL, firmware, or marker-rule change.

scripts/regress.py

@@ -36,8 +36,9 @@ CI_SMOKE_SDRAM_SIM_VALUES = (
     CI_SMOKE_APP_VALUE,
     "LINK_TYPE=ld2_sdram",
     # Hosted Verilator executes the expanded peripheral acceptance workload
-    # slowly when LP code and accelerator traffic share the SDRAM target.
-    "SOC_SIM_TIME=3600",
+    # slowly when LP code and accelerator traffic share the SDRAM target; the
+    # merged HP subsystem needs roughly 4400 s locally, so double the tier.
+    "SOC_SIM_TIME=7200",
     *CI_SMOKE_VERILATOR_VALUES,
 )
 RTL_LINT_VALUES = ("SIMU=VERILATOR", "HAVE_SVA=YES", "rtl-lint")