fix(ci): raise the Mini ci_smoke Verilator budget to the 3600s tier

The feat/mini-hp-core merge adds the HP subsystem to the Mini Verilator
model, so the ci_smoke acceptance step (which ends in the crypto self-test)
exceeds the old 1800 s wall budget on hosted runners and fails with
SIM_TEST_TIMEOUT. The merged content is functionally correct: the identical
step passes locally with SIM_TEST_PASS code=0 in 1806 s wall
(build/ihp130-2026-10-23-11-20-cff97749f2f3/). This is a validation-only
budget change to the existing 3600 s tier already used by the SDRAM variant;
the contract tests in tests/test_script_tools.py are updated to pin the new
value. No RTL, firmware, or marker-rule change. CI failure under repair:
regression-ihp130 run 39889921334.
This commit is contained in:
maksyuki committed 2026-10-23 11:54:17 +08:00
1 parent 3062aec09b
commit 9ab05c6404
2 files changed
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+3 -1
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@@ -27,7 +27,9 @@ CI_SMOKE_VERILATOR_VALUES = (
CI_SMOKE_SIM_VALUES = (
CI_SMOKE_APP_VALUE,
"LINK_TYPE=ld2_all_sram",
"SOC_SIM_TIME=1800",
# The merged HP subsystem roughly doubled the hosted Verilator runtime of
# this acceptance step; keep the next existing budget tier.
"SOC_SIM_TIME=3600",
*CI_SMOKE_VERILATOR_VALUES,
)
CI_SMOKE_SDRAM_SIM_VALUES = (
+7 -1
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@@ -1318,6 +1318,12 @@ def test_verilator_simulations_use_uniform_timeout() -> None:
assert "TINY_P7_ACCEPTANCE=YES" in values
assert "TINY_SIM_TIMEOUT=6000000" in values
assert "TINY_SIM_ARGS=+p7_monitor" in values
elif "LINK_TYPE=ld2_sdram" in values:
assert simulation_timeout == ["SOC_SIM_TIME=3600"]
elif profile == "configs/ci/ihp130.mk":
# The merged HP subsystem roughly doubled this step's
# hosted runtime; it shares the next budget tier.
assert simulation_timeout == ["SOC_SIM_TIME=3600"]
else:
assert simulation_timeout == ["SOC_SIM_TIME=1800"]
assert "LINK_TYPE=ld2_all_sram" in values
@@ -1621,7 +1627,7 @@ def test_pdk_pr_regressions_cover_firmware_rtl_and_selected_netlist_target() ->
if pdk == "IHP130":
assert "LINK_TYPE=ld2_all_sram" in verilator_values
assert "VERILATOR_SIM_ARGS=--fast-flash" in verilator_values
assert "SOC_SIM_TIME=1800" in verilator_values
assert "SOC_SIM_TIME=3600" in verilator_values
else:
assert "LINK_TYPE=ld2_sdram" in verilator_values
assert "VERILATOR_SIM_ARGS=--fast-flash" in verilator_values