fix(ci): raise the Mini ci_smoke SDRAM Verilator budget to 7200s

The merged HP subsystem makes the Mini ci_smoke ld2_sdram Verilator step
need roughly 4400 s locally (SIM_TEST_PASS code=0 in 4389 s,
build/ics55-2026-10-23-15-17-2e059475a01b/), so hosted runners time out the
existing 3600 s tier during the crypto self-test on ICS55/SKY130/GF180
(jobs 120251738572, 120251738799, 120251738649). Double the tier to 7200 s;
the ld2_all_sram step stays at 3600 s (measured need about half of that).
Validation-only budget change with the two contract assertions pinned to the
new values; no RTL, firmware, or marker-rule change.

scripts/regress.py

@@ -36,8 +36,9 @@ CI_SMOKE_SDRAM_SIM_VALUES = (
     CI_SMOKE_APP_VALUE,
     "LINK_TYPE=ld2_sdram",
     # Hosted Verilator executes the expanded peripheral acceptance workload
-    # slowly when LP code and accelerator traffic share the SDRAM target.
-    "SOC_SIM_TIME=3600",
+    # slowly when LP code and accelerator traffic share the SDRAM target; the
+    # merged HP subsystem needs roughly 4400 s locally, so double the tier.
+    "SOC_SIM_TIME=7200",
     *CI_SMOKE_VERILATOR_VALUES,
 )
 RTL_LINT_VALUES = ("SIMU=VERILATOR", "HAVE_SVA=YES", "rtl-lint")

tests/test_script_tools.py

@@ -1319,7 +1319,7 @@ def test_verilator_simulations_use_uniform_timeout() -> None:
                     assert "TINY_SIM_TIMEOUT=6000000" in values
                     assert "TINY_SIM_ARGS=+p7_monitor" in values
                 elif "LINK_TYPE=ld2_sdram" in values:
-                    assert simulation_timeout == ["SOC_SIM_TIME=3600"]
+                    assert simulation_timeout == ["SOC_SIM_TIME=7200"]
                 elif profile == "configs/ci/ihp130.mk":
                     # The merged HP subsystem roughly doubled this step's
                     # hosted runtime; it shares the next budget tier.
@@ -1631,7 +1631,7 @@ def test_pdk_pr_regressions_cover_firmware_rtl_and_selected_netlist_target() ->
         else:
             assert "LINK_TYPE=ld2_sdram" in verilator_values
             assert "VERILATOR_SIM_ARGS=--fast-flash" in verilator_values
-            assert "SOC_SIM_TIME=3600" in verilator_values
+            assert "SOC_SIM_TIME=7200" in verilator_values
         assert "HAVE_CSR=YES" in verilator_values
         assert any("SIMU=IVERILOG" in values and "sim-asm" in values for values in command_values)
         assert any("SYNTH=YOSYS" in values and "synth" in values for values in command_values)