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feat: modify axil mmio addr range

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maksyuki committed 2025-02-02 00:02:46 +08:00
1 parent de7e59d176
commit 08e3bbf87d
4 files changed
+72 -16
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rtl/firmware.c
+22 -3
View File
@@ -667,9 +667,27 @@ void ip_i2c_test()
void ip_archinfo_test() {
print("[IP] archinfo test\n");
print_reg("[ARCHINFO SYS]", reg_archinfo_sys, 8);
print_reg("[ARCHINFO IDL]", reg_archinfo_idl, 8);
print_reg("[ARCHINFO IDH]", reg_archinfo_idh, 8);
print_reg("[ARCHINFO SYS] ", reg_archinfo_sys, 8);
print_reg("[ARCHINFO IDL] ", reg_archinfo_idl, 8);
print_reg("[ARCHINFO IDH] ", reg_archinfo_idh, 8);
}
void ip_rng_test() {
print("[IP] rng test\n");
reg_rng_ctrl = (uint32_t)1; // en the core
reg_rng_seed = (uint32_t)0xFE1C; // set the init seed
print_reg("[RNG SEED] ", reg_rng_seed, 8);
for(int i = 0; i < 5; ++i) {
print_reg("[RNG VAL] ", reg_rng_val, 8);
}
print("[RNG] reset the seed\n");
reg_rng_seed = (uint32_t)0;
for(int i = 0; i < 5; ++i) {
print_reg("[RNG VAL] ", reg_rng_val, 8);
}
}
void main()
@@ -705,6 +723,7 @@ void main()
// ip_gpio_test();
// ip_i2c_test();
ip_archinfo_test();
ip_rng_test();
// cmd_benchmark(true, 0);
// cmd_benchmark_all();
// cmd_memtest();
rtl/firmware.h
+6 -5
View File
@@ -49,12 +49,13 @@
#define reg_timer1_value (*(volatile uint32_t*)0x0300006c)
#define reg_timer1_data (*(volatile uint32_t*)0x03000070)
#define reg_archinfo_sys (*(volatile uint32_t*)0x03000100)
#define reg_archinfo_idl (*(volatile uint32_t*)0x03000104)
#define reg_archinfo_idh (*(volatile uint32_t*)0x03000108)
#define reg_archinfo_sys (*(volatile uint32_t*)0x03001000)
#define reg_archinfo_idl (*(volatile uint32_t*)0x03001004)
#define reg_archinfo_idh (*(volatile uint32_t*)0x03001008)
#define reg_rng_ctrl (*(volatile uint32_t*)0x03002000)
#define reg_rng_seed (*(volatile uint32_t*)0x03002004)
#define reg_rng_val (*(volatile uint32_t*)0x03002008)
// command register bits
// bit 7 = start
rtl/ip/axil_ip_wrapper.v
+39 -4
View File
@@ -18,11 +18,22 @@ module axil_ip_wrapper (
output mem_axi_rvalid,
input mem_axi_rready,
output [31:0] mem_axi_rdata
// pwm
// input ls_clk_i,
// input pwm_pin_in_i,
// output pwm_irq3_o,
// output pwm_irq2_o,
// output pwm_irq1_o,
// output pwm_irq0_o,
// output [ 3:0] pwm_tim0_o,
// output [ 3:0] pwm_tim1_o,
// output [ 3:0] pwm_tim2_o,
// output [ 3:0] pwm_tim3_o
);
localparam APB_SLAVES_NUM = 2;
localparam [32*APB_SLAVES_NUM-1 : 0] MEM_REGIONS1 = 32'h0300_0100 + 64'h0300_0110_0000_0000;
localparam [32*APB_SLAVES_NUM-1 : 0] MEM_REGIONS2 = 32'h0300_0108 + 64'h0300_0118_0000_0000;
localparam [32*APB_SLAVES_NUM-1 : 0] MEM_REGIONS1 = 64'h0300_2000__0300_1000;
localparam [32*APB_SLAVES_NUM-1 : 0] MEM_REGIONS2 = 64'h0300_2008__0300_1008;
wire [ 31:0] s_m_apb_paddr;
wire [ 2:0] s_m_apb_pprot;
@@ -35,10 +46,11 @@ module axil_ip_wrapper (
wire [ 31:0] s_m_apb_prdata;
wire [ 31:0] s_m_apb_prdata2;
wire [ 31:0] s_m_apb_prdata3;
wire [APB_SLAVES_NUM-1:0] s_m_apb_pslverr;
// ARCHINFO
// RNG
// UART
apb4_archinfo u_apb4_archinfo (
.pclk (clk_i),
.presetn(rst_n_i),
@@ -54,7 +66,7 @@ module axil_ip_wrapper (
.pslverr(s_m_apb_pslverr[0])
);
apb4_archinfo u_apb4_archinfo2 (
apb4_rng u_apb4_rng (
.pclk (clk_i),
.presetn(rst_n_i),
.paddr (s_m_apb_paddr),
@@ -69,6 +81,29 @@ module axil_ip_wrapper (
.pslverr(s_m_apb_pslverr[1])
);
// apb_adv_timer #(
// .APB_ADDR_WIDTH(32)
// ) u_apb_adv_timer (
// .HCLK (clk_i),
// .HRESETn (rst_n_i),
// .PADDR (s_m_apb_paddr),
// .PWDATA (s_m_apb_pwdata),
// .PWRITE (s_m_apb_pwrite),
// .PSEL (s_m_apb_psel[2]),
// .PENABLE (s_m_apb_penable),
// .PRDATA (s_m_apb_prdata3),
// .PREADY (s_m_apb_pready[2]),
// .PSLVERR (s_m_apb_pslverr[2]),
// .dft_cg_enable_i(1'b0),
// .low_speed_clk_i(ls_clk_i),
// .ext_sig_i (pwm_pin_in_i),
// .events_o ({pwm_irq3_o, pwm_irq2_o, pwm_irq1_o, pwm_irq0_o}),
// .ch_0_o (pwm_tim0_o),
// .ch_1_o (pwm_tim1_o),
// .ch_2_o (pwm_tim2_o),
// .ch_3_o (pwm_tim3_o)
// );
axi_apb_bridge #(
.c_apb_num_slaves(APB_SLAVES_NUM),
.memory_regions1 (MEM_REGIONS1),
rtl/retrosoc.v
+5 -4
View File
@@ -327,7 +327,7 @@ module retrosoc #(
// 1 x RNG
// 1 x ARCH
// 1 x UART
// 1 x SPI
// 1 x SPI MASTER
// 4 x PWM
// 1 x PSRAM
picorv32 #(
@@ -475,6 +475,7 @@ module retrosoc #(
.irq_out (s_irq_tim1)
);
wire s_axi_mem_range = s_iomem_addr[31:8] >= 24'h0300_10 && s_iomem_addr[31:8] <= 24'h03FF_FF;
picorv32_axi_adapter u_core2axi (
.clk (clk_i),
.resetn (rst_n_i),
@@ -495,7 +496,7 @@ module retrosoc #(
.mem_axi_rvalid (s_mem_axi_rvalid),
.mem_axi_rready (s_mem_axi_rready),
.mem_axi_rdata (s_mem_axi_rdata),
.mem_valid (s_iomem_valid && s_iomem_addr[31:8] == 24'h030001),
.mem_valid (s_iomem_valid && s_axi_mem_range),
.mem_instr (s_mem_instr),
.mem_ready (s_aximem_ready),
.mem_addr (s_iomem_addr),
@@ -543,7 +544,7 @@ module retrosoc #(
r_irq_7_in_src <= 0;
r_irq_8_in_src <= 0;
end else begin
if (s_iomem_valid && !r_iomem_ready && s_iomem_addr[31:8] == 24'h030000) begin
if (s_iomem_valid && !r_iomem_ready && s_iomem_addr[31:8] == 24'h0300_00) begin
// Handle r_iomem_ready based on wait states
case (s_iomem_addr[7:0])
8'h14: r_iomem_ready <= ~s_simpleuart_reg_dat_wait;
@@ -620,7 +621,7 @@ module retrosoc #(
8'h6c: r_iomem_rdata <= s_tim1_reg_val_dout;
8'h70: r_iomem_rdata <= s_tim1_reg_dat_dout;
endcase
end else if (s_iomem_valid && !r_iomem_ready && s_iomem_addr[31:8] == 24'h030001) begin
end else if (s_iomem_valid && !r_iomem_ready && s_axi_mem_range) begin
r_iomem_ready <= s_aximem_ready;
r_iomem_rdata <= s_aximem_rdata;
end else begin