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feat: chg tech modules' name into generic

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maksyuki committed 2025-02-03 23:49:33 +08:00
1 parent 769a976c15
commit 145dc29585
3 files changed
+36 -57
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tech/tc_clk.v
+24 -24
View File
@@ -5,7 +5,7 @@
//
// -Thomas Benz <tbenz@iis.ee.ethz.ch>
// -Tobias Senti <tsenti@student.ethz.ch>
module ihp_clk_inverter (
module tc_clk_inverter (
input clk_i,
output clk_o
);
@@ -18,7 +18,7 @@ module ihp_clk_inverter (
endmodule
module ihp_clk_buffer (
module tc_clk_buffer (
input clk_i,
output clk_o
);
@@ -31,7 +31,7 @@ module ihp_clk_buffer (
endmodule
module ihp_clk_mux2 (
module tc_clk_mux2 (
input clk0_i,
input clk1_i,
input clk_sel_i,
@@ -46,7 +46,7 @@ module ihp_clk_mux2 (
);
endmodule
module ihp_clk_xor2 (
module tc_clk_xor2 (
input clk0_i,
input clk1_i,
output clk_o
@@ -60,25 +60,25 @@ module ihp_clk_xor2 (
);
endmodule
module ihp_clk_gating #(
parameter [0:0] IS_FUNCTIONAL = 1'b1
) (
input clk_i,
input en_i,
input test_en_i,
output clk_o
);
// module tc_clk_gating #(
// parameter [0:0] IS_FUNCTIONAL = 1'b1
// ) (
// input clk_i,
// input en_i,
// input test_en_i,
// output clk_o
// );
// if (IS_FUNCTIONAL || `ifdef USE_CLKGATE 1 `else 0 `endif) begin
// (* keep *)(* dont_touch = "true" *)
// sg13g2_slgcp_1 i_clkgate (
// .GATE ( en_i ),
// .SCE ( test_en_i ),
// .CLK ( clk_i ),
// .GCLK ( clk_o )
// );
// end else begin
assign clk_o = clk_i;
// end
// // if (IS_FUNCTIONAL || `ifdef USE_CLKGATE 1 `else 0 `endif) begin
// // (* keep *)(* dont_touch = "true" *)
// // sg13g2_slgcp_1 i_clkgate (
// // .GATE ( en_i ),
// // .SCE ( test_en_i ),
// // .CLK ( clk_i ),
// // .GCLK ( clk_o )
// // );
// // end else begin
// assign clk_o = clk_i;
// // end
endmodule
// endmodule
tech/tc_io.v
+2 -2
View File
@@ -1,4 +1,4 @@
module ihp_io_xtl_pad (
module tc_io_xtl_pad (
input xi_pad,
output xo_pad,
input en,
@@ -9,7 +9,7 @@ module ihp_io_xtl_pad (
assign xo_pad = xi_pad;
endmodule
module ihp_io_tri_pad (
module tc_io_tri_pad (
inout pad,
input c2p,
input c2p_en,
tech/tc_sram.v
+10 -31
View File
@@ -8,47 +8,26 @@ module tc_sram_1024x32 (
output [31:0] data_o
);
wire [15:0] s_rd_data_mem1, s_rd_data_mem2;
assign data_o = {s_rd_data_mem2, s_rd_data_mem1};
RM_IHPSG13_1P_1024x16_c2_bm_bist u_mem1 (
wire [63:0] s_rd_data_mem;
assign data_o = s_rd_data_mem[31:0];
RM_IHPSG13_1P_1024x64_c2_bm_bist u_mem (
.A_CLK (clk_i),
.A_ADDR (addr_i),
.A_BM ({{8{mask_i[1]}}, {8{mask_i[0]}}}),
.A_BM ({32'h0, {8{mask_i[3]}}, {8{mask_i[2]}}, {8{mask_i[1]}}, {8{mask_i[0]}}}),
.A_MEN (cs_i),
.A_WEN (wren_i),
.A_REN (~wren_i),
.A_DIN (data_i[15:0]),
.A_DOUT (s_rd_data_mem1),
.A_DIN ({32'h0, data_i[31:0]}),
.A_DOUT (s_rd_data_mem),
.A_DLY (1'b0),
.A_BIST_CLK (1'b0),
.A_BIST_ADDR(10'd0),
.A_BIST_DIN (16'd0),
.A_BIST_BM (16'd0),
.A_BIST_EN (1'b0),
.A_BIST_MEN (1'b0),
.A_BIST_WEN (1'b0),
.A_BIST_REN (1'b0),
.A_BIST_EN (1'b0),
.A_DLY (1'b0)
);
RM_IHPSG13_1P_1024x16_c2_bm_bist u_mem2 (
.A_CLK (clk_i),
.A_ADDR (addr_i),
.A_BM ({{8{mask_i[3]}}, {8{mask_i[2]}}}),
.A_MEN (cs_i),
.A_WEN (wren_i),
.A_REN (~wren_i),
.A_DIN (data_i[31:16]),
.A_DOUT (s_rd_data_mem2),
.A_BIST_CLK (1'b0),
.A_BIST_ADDR(10'd0),
.A_BIST_DIN (16'd0),
.A_BIST_BM (16'd0),
.A_BIST_MEN (1'b0),
.A_BIST_WEN (1'b0),
.A_BIST_REN (1'b0),
.A_BIST_EN (1'b0),
.A_DLY (1'b0)
.A_BIST_DIN (64'd0),
.A_BIST_BM (64'd0)
);
endmodule