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feat: rm unused signals

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maksyuki committed 2025-03-14 21:17:48 +08:00
1 parent 0e47ce2837
commit 14a3da70e2
5 files changed
+50 -298
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fpga/retrosoc_top.v
-12
View File
@@ -47,18 +47,6 @@ module retrosoc_top (
.pll_cfg_2_i_pad (1'b0),
.clk_bypass_i_pad (1'b1),
.ext_rst_n_i_pad (rst_n_i),
// HOUSEKEEPING SPI
.hk_sdi_i_pad (1'b0),
.hk_sdo_o_pad (),
.hk_csb_i_pad (1'b0),
.hk_sck_i_pad (1'b0),
// SPI FLASH
.flash_csb_o_pad (),
.flash_clk_o_pad (),
.flash_io0_io_pad (),
.flash_io1_io_pad (),
.flash_io2_io_pad (),
.flash_io3_io_pad (),
// UART
.uart_tx_o_pad (uart_tx_o),
.uart_rx_i_pad (uart_rx_i),
rtl/retrosoc.v
+50 -159
View File
@@ -34,13 +34,6 @@ module retrosoc #(
) (
input clk_i,
input rst_n_i,
input clk_ext_sel_i,
// pass-through mode from housekeeping SPI
input hk_pt_i,
input hk_pt_csb_i,
input hk_pt_sck_i,
input hk_pt_sdi_i,
output hk_pt_sdo_o,
//sram if including clk_i and rst_n_i above
output [ 3:0] ram_wstrb_o,
output [14:0] ram_addr_o,
@@ -52,39 +45,12 @@ module retrosoc #(
output [15:0] gpio_pullupb_o,
output [15:0] gpio_pulldownb_o,
output [15:0] gpio_outenb_o,
input [ 7:0] spi_slv_ro_config_i,
input spi_slv_ro_xtal_ena_i,
input spi_slv_ro_reg_ena_i,
input spi_slv_ro_pll_cp_ena_i,
input spi_slv_ro_pll_vco_ena_i,
input spi_slv_ro_pll_bias_ena_i,
input [ 3:0] spi_slv_ro_pll_trim_i,
input [11:0] spi_slv_ro_mfgr_id_i,
input [ 7:0] spi_slv_ro_prod_id_i,
input [ 3:0] spi_slv_ro_mask_rev_i,
output uart_tx_o,
input uart_rx_i,
// irq
input irq_pin_i,
input irq_spi_i,
output trap_o,
// spi flash
output flash_csb_o,
output flash_clk_o,
output flash_clk_oeb_o,
output flash_csb_oeb_o,
output flash_io0_oeb_o,
output flash_io1_oeb_o,
output flash_io2_oeb_o,
output flash_io3_oeb_o,
output flash_io0_do_o,
output flash_io1_do_o,
output flash_io2_do_o,
output flash_io3_do_o,
input flash_io0_di_i,
input flash_io1_di_i,
input flash_io2_di_i,
input flash_io3_di_i,
// cust
input cust_uart_rx_i,
output cust_uart_tx_o,
@@ -152,8 +118,6 @@ module retrosoc #(
reg [15:0] r_gpio_pu;
reg [15:0] r_gpio_pd;
reg [15:0] r_gpio_oeb;
reg [ 1:0] r_pll_out_dest;
reg [ 1:0] r_trap_out_dest;
reg [ 1:0] r_irq_7_in_src;
reg [ 1:0] r_irq_8_in_src;
// mmio axil if
@@ -176,7 +140,6 @@ module retrosoc #(
wire [31:0] s_mem_axi_rdata;
// irq
wire [31:0] s_irq;
wire s_irq_stall = 0;
wire s_irq_uart;
wire s_irq_tim0;
wire s_irq_tim1;
@@ -196,12 +159,12 @@ module retrosoc #(
assign gpio_out_o[5] = r_gpio[5];
assign gpio_out_o[6] = r_gpio[6];
assign gpio_out_o[7] = r_gpio[7];
assign gpio_out_o[8] = r_pll_out_dest == 2'b01 ? clk_i : r_gpio[8];
assign gpio_out_o[9] = r_pll_out_dest == 2'b10 ? clk_i : r_gpio[9];
assign gpio_out_o[8] = r_gpio[8];
assign gpio_out_o[9] = r_gpio[9];
assign gpio_out_o[10] = r_gpio[10];
assign gpio_out_o[11] = r_trap_out_dest == 2'b01 ? trap_o : r_gpio[11];
assign gpio_out_o[12] = r_trap_out_dest == 2'b10 ? trap_o : r_gpio[12];
assign gpio_out_o[13] = r_trap_out_dest == 2'b11 ? trap_o : r_gpio[13];
assign gpio_out_o[11] = r_gpio[11];
assign gpio_out_o[12] = r_gpio[12];
assign gpio_out_o[13] = r_gpio[13];
assign gpio_out_o[14] = r_gpio[14];
assign gpio_out_o[15] = r_gpio[15];
@@ -213,12 +176,12 @@ module retrosoc #(
assign gpio_outenb_o[5] = ~rst_n_i | r_gpio_oeb[5];
assign gpio_outenb_o[6] = ~rst_n_i | r_gpio_oeb[6];
assign gpio_outenb_o[7] = ~rst_n_i | r_gpio_oeb[7];
assign gpio_outenb_o[8] = ~rst_n_i | (r_pll_out_dest == 2'b00 ? r_gpio_oeb[8] : 1'b0);
assign gpio_outenb_o[9] = ~rst_n_i | (r_pll_out_dest == 2'b00 ? r_gpio_oeb[9] : 1'b0);
assign gpio_outenb_o[10] = ~rst_n_i | (r_pll_out_dest == 2'b00 ? r_gpio_oeb[10] : 1'b0);
assign gpio_outenb_o[11] = ~rst_n_i | (r_trap_out_dest == 2'b00 ? r_gpio_oeb[11] : 1'b0);
assign gpio_outenb_o[12] = ~rst_n_i | (r_trap_out_dest == 2'b00 ? r_gpio_oeb[12] : 1'b0);
assign gpio_outenb_o[13] = ~rst_n_i | (r_trap_out_dest == 2'b00 ? r_gpio_oeb[13] : 1'b0);
assign gpio_outenb_o[8] = ~rst_n_i | r_gpio_oeb[8];
assign gpio_outenb_o[9] = ~rst_n_i | r_gpio_oeb[9];
assign gpio_outenb_o[10] = ~rst_n_i | r_gpio_oeb[10];
assign gpio_outenb_o[11] = ~rst_n_i | r_gpio_oeb[11];
assign gpio_outenb_o[12] = ~rst_n_i | r_gpio_oeb[12];
assign gpio_outenb_o[13] = ~rst_n_i | r_gpio_oeb[13];
assign gpio_outenb_o[14] = ~rst_n_i | r_gpio_oeb[14];
assign gpio_outenb_o[15] = ~rst_n_i | r_gpio_oeb[15];
@@ -230,12 +193,12 @@ module retrosoc #(
assign gpio_pullupb_o[5] = r_gpio_pu[5];
assign gpio_pullupb_o[6] = r_gpio_pu[6];
assign gpio_pullupb_o[7] = r_gpio_pu[7];
assign gpio_pullupb_o[8] = r_pll_out_dest == 2'b00 ? r_gpio_pu[8] : 1'b1;
assign gpio_pullupb_o[9] = r_pll_out_dest == 2'b00 ? r_gpio_pu[9] : 1'b1;
assign gpio_pullupb_o[10] = r_pll_out_dest == 2'b00 ? r_gpio_pu[10] : 1'b1;
assign gpio_pullupb_o[11] = r_trap_out_dest == 2'b00 ? r_gpio_pu[11] : 1'b1;
assign gpio_pullupb_o[12] = r_trap_out_dest == 2'b00 ? r_gpio_pu[12] : 1'b1;
assign gpio_pullupb_o[13] = r_trap_out_dest == 2'b00 ? r_gpio_pu[13] : 1'b1;
assign gpio_pullupb_o[8] = r_gpio_pu[8];
assign gpio_pullupb_o[9] = r_gpio_pu[9];
assign gpio_pullupb_o[10] = r_gpio_pu[10];
assign gpio_pullupb_o[11] = r_gpio_pu[11];
assign gpio_pullupb_o[12] = r_gpio_pu[12];
assign gpio_pullupb_o[13] = r_gpio_pu[13];
assign gpio_pullupb_o[14] = r_gpio_pu[14];
assign gpio_pullupb_o[15] = r_gpio_pu[15];
@@ -247,12 +210,12 @@ module retrosoc #(
assign gpio_pulldownb_o[5] = r_gpio_pd[5];
assign gpio_pulldownb_o[6] = r_gpio_pd[6];
assign gpio_pulldownb_o[7] = r_gpio_pd[7];
assign gpio_pulldownb_o[8] = r_pll_out_dest == 2'b00 ? r_gpio_pd[8] : 1'b1;
assign gpio_pulldownb_o[9] = r_pll_out_dest == 2'b00 ? r_gpio_pd[9] : 1'b1;
assign gpio_pulldownb_o[10] = r_pll_out_dest == 2'b00 ? r_gpio_pd[10] : 1'b1;
assign gpio_pulldownb_o[11] = r_trap_out_dest == 2'b00 ? r_gpio_pd[11] : 1'b1;
assign gpio_pulldownb_o[12] = r_trap_out_dest == 2'b00 ? r_gpio_pd[12] : 1'b1;
assign gpio_pulldownb_o[13] = r_trap_out_dest == 2'b00 ? r_gpio_pd[13] : 1'b1;
assign gpio_pulldownb_o[8] = r_gpio_pd[8];
assign gpio_pulldownb_o[9] = r_gpio_pd[9];
assign gpio_pulldownb_o[10] = r_gpio_pd[10];
assign gpio_pulldownb_o[11] = r_gpio_pd[11];
assign gpio_pulldownb_o[12] = r_gpio_pd[12];
assign gpio_pulldownb_o[13] = r_gpio_pd[13];
assign gpio_pulldownb_o[14] = r_gpio_pd[14];
assign gpio_pulldownb_o[15] = r_gpio_pd[15];
@@ -273,28 +236,22 @@ module retrosoc #(
end
assign s_irq[2:0] = 3'd0;
assign s_irq[3] = s_irq_stall;
assign s_irq[4] = s_irq_uart;
assign s_irq[5] = irq_pin_i;
assign s_irq[6] = irq_spi_i;
assign s_irq[7] = s_irq_7;
assign s_irq[8] = s_irq_8;
assign s_irq[9] = 1'd0;
assign s_irq[10] = 1'd0;
assign s_irq[11] = s_irq_tim0;
assign s_irq[12] = s_irq_tim1;
assign s_irq[13] = s_cust_uart_irq;
assign s_irq[14] = s_cust_pwm_irq;
assign s_irq[15] = s_cust_ps2_irq;
assign s_irq[16] = s_cust_i2c_irq;
assign s_irq[17] = s_cust_qspi_irq;
assign s_irq[18] = s_cust_spfs_irq;
assign s_irq[31:19] = 13'd0;
assign s_irq[3] = s_irq_uart;
assign s_irq[4] = irq_pin_i;
assign s_irq[5] = s_irq_7;
assign s_irq[6] = s_irq_8;
assign s_irq[7] = s_irq_tim0;
assign s_irq[8] = s_irq_tim1;
assign s_irq[9] = s_cust_uart_irq;
assign s_irq[10] = s_cust_pwm_irq;
assign s_irq[11] = s_cust_ps2_irq;
assign s_irq[12] = s_cust_i2c_irq;
assign s_irq[13] = s_cust_qspi_irq;
assign s_irq[14] = s_cust_spfs_irq;
assign s_irq[31:15] = 17'd0;
// memory mapped IP
// 1 x SPFS
// 16 x GPIO
// 1 x HOUSEKEEPING SPI
// 1 x UART
// 2 x TIMER
// AXIL WRAPPER
@@ -337,9 +294,6 @@ module retrosoc #(
assign s_iomem_wstrb = s_mem_wstrb;
assign s_iomem_addr = s_mem_addr;
assign s_iomem_wdata = s_mem_wdata;
// spi flash
wire s_spimemio_cfgreg_sel = s_mem_valid && (s_mem_addr == 32'h0200_0000);
wire [31:0] s_spimemio_cfgreg_dout;
// uart
wire s_simpleuart_reg_div_sel = s_iomem_valid && (s_iomem_addr == 32'h0300_0010);
wire s_simpleuart_reg_dat_sel = s_iomem_valid && (s_iomem_addr == 32'h0300_0014);
@@ -347,7 +301,7 @@ module retrosoc #(
wire [31:0] s_simpleuart_reg_dat_dout;
wire s_simpleuart_reg_dat_wait;
// tim0
wire s_tim0_reg_cfg_sel = s_iomem_valid && (s_iomem_addr == 32'h0300_005c);
wire s_tim0_reg_cfg_sel = s_iomem_valid && (s_iomem_addr == 32'h0300_005C);
wire s_tim0_reg_val_sel = s_iomem_valid && (s_iomem_addr == 32'h0300_0060);
wire s_tim0_reg_dat_sel = s_iomem_valid && (s_iomem_addr == 32'h0300_0064);
wire [31:0] s_tim0_reg_cfg_dout;
@@ -355,7 +309,7 @@ module retrosoc #(
wire [31:0] s_tim0_reg_dat_dout;
// tim1
wire s_tim1_reg_cfg_sel = s_iomem_valid && (s_iomem_addr == 32'h0300_0068);
wire s_tim1_reg_val_sel = s_iomem_valid && (s_iomem_addr == 32'h0300_006c);
wire s_tim1_reg_val_sel = s_iomem_valid && (s_iomem_addr == 32'h0300_006C);
wire s_tim1_reg_dat_sel = s_iomem_valid && (s_iomem_addr == 32'h0300_0070);
wire [31:0] s_tim1_reg_cfg_dout;
wire [31:0] s_tim1_reg_val_dout;
@@ -368,39 +322,6 @@ module retrosoc #(
reg [ 2:0] r_psram_cfg_chd_din;
wire [ 2:0] s_psram_cfg_chd_dout;
spimemio u_spimemio (
.clk (clk_i),
.resetn (rst_n_i),
.valid (s_mem_valid && s_mem_addr >= 4 * MEM_WORDS && s_mem_addr < 32'h0200_0000),
.ready (s_spimem_ready),
.addr (s_mem_addr[23:0]),
.rdata (s_spimem_rdata),
.pass_thru (hk_pt_i),
.pass_thru_csb(hk_pt_csb_i),
.pass_thru_sck(hk_pt_sck_i),
.pass_thru_sdi(hk_pt_sdi_i),
.pass_thru_sdo(hk_pt_sdo_o),
.flash_csb (flash_csb_o),
.flash_clk (flash_clk_o),
.flash_csb_oeb(flash_csb_oeb_o),
.flash_clk_oeb(flash_clk_oeb_o),
.flash_io0_oeb(flash_io0_oeb_o),
.flash_io1_oeb(flash_io1_oeb_o),
.flash_io2_oeb(flash_io2_oeb_o),
.flash_io3_oeb(flash_io3_oeb_o),
.flash_io0_do (flash_io0_do_o),
.flash_io1_do (flash_io1_do_o),
.flash_io2_do (flash_io2_do_o),
.flash_io3_do (flash_io3_do_o),
.flash_io0_di (flash_io0_di_i),
.flash_io1_di (flash_io1_di_i),
.flash_io2_di (flash_io2_di_i),
.flash_io3_di (flash_io3_di_i),
.cfgreg_we (s_spimemio_cfgreg_sel ? s_mem_wstrb : 4'b0000),
.cfgreg_di (s_mem_wdata),
.cfgreg_do (s_spimemio_cfgreg_dout)
);
simpleuart u_simpleuart (
.clk (clk_i),
.resetn (rst_n_i),
@@ -560,14 +481,12 @@ module retrosoc #(
always @(posedge clk_i, negedge rst_n_i) begin
if (!rst_n_i) begin
r_gpio <= 0;
r_gpio_oeb <= 16'hffff;
r_gpio_pu <= 0;
r_gpio_pd <= 0;
r_pll_out_dest <= 0;
r_trap_out_dest <= 0;
r_irq_7_in_src <= 0;
r_irq_8_in_src <= 0;
r_gpio <= 16'd0;
r_gpio_oeb <= 16'hffff;
r_gpio_pu <= 16'd0;
r_gpio_pd <= 16'd0;
r_irq_7_in_src <= 2'd0;
r_irq_8_in_src <= 2'd0;
end else begin
if (s_iomem_valid && !r_iomem_ready && s_iomem_addr[31:8] == 24'h0300_00) begin
// Handle r_iomem_ready based on wait states
@@ -591,49 +510,26 @@ module retrosoc #(
if (s_iomem_wstrb[0]) r_gpio_pu[7:0] <= s_iomem_wdata[7:0];
if (s_iomem_wstrb[1]) r_gpio_pu[15:8] <= s_iomem_wdata[15:8];
end
8'h0c: begin
8'h0C: begin
r_iomem_rdata <= {16'd0, r_gpio_pu};
if (s_iomem_wstrb[0]) r_gpio_pd[7:0] <= s_iomem_wdata[7:0];
if (s_iomem_wstrb[1]) r_gpio_pd[15:8] <= s_iomem_wdata[15:8];
end
8'h10: r_iomem_rdata <= s_simpleuart_reg_div_dout;
8'h14: r_iomem_rdata <= s_simpleuart_reg_dat_dout;
8'h18: r_iomem_rdata <= {24'd0, spi_slv_ro_config_i};
8'h1c: r_iomem_rdata <= {30'd0, spi_slv_ro_xtal_ena_i, spi_slv_ro_reg_ena_i};
8'h20: begin
r_iomem_rdata <= {
25'd0,
spi_slv_ro_pll_trim_i,
spi_slv_ro_pll_cp_ena_i,
spi_slv_ro_pll_vco_ena_i,
spi_slv_ro_pll_bias_ena_i
};
end
8'h24: r_iomem_rdata <= {20'd0, spi_slv_ro_mfgr_id_i};
8'h28: r_iomem_rdata <= {24'd0, spi_slv_ro_prod_id_i};
8'h2c: r_iomem_rdata <= {28'd0, spi_slv_ro_mask_rev_i};
8'h30: r_iomem_rdata <= {31'd0, clk_ext_sel_i};
8'h38: begin
r_iomem_rdata <= {30'd0, r_pll_out_dest};
if (s_iomem_wstrb[0]) r_pll_out_dest <= s_iomem_wdata[1:0];
end
8'h3c: begin
r_iomem_rdata <= {30'd0, r_trap_out_dest};
if (s_iomem_wstrb[0]) r_trap_out_dest <= s_iomem_wdata[1:0];
end
8'h40: begin
8'h18: begin
r_iomem_rdata <= {30'd0, r_irq_7_in_src};
if (s_iomem_wstrb[0]) r_irq_7_in_src <= s_iomem_wdata[1:0];
end
8'h44: begin
8'h1C: begin
r_iomem_rdata <= {30'd0, r_irq_8_in_src};
if (s_iomem_wstrb[0]) r_irq_8_in_src <= s_iomem_wdata[1:0];
end
8'h5c: r_iomem_rdata <= s_tim0_reg_cfg_dout;
8'h5C: r_iomem_rdata <= s_tim0_reg_cfg_dout;
8'h60: r_iomem_rdata <= s_tim0_reg_val_dout;
8'h64: r_iomem_rdata <= s_tim0_reg_dat_dout;
8'h68: r_iomem_rdata <= s_tim1_reg_cfg_dout;
8'h6c: r_iomem_rdata <= s_tim1_reg_val_dout;
8'h6C: r_iomem_rdata <= s_tim1_reg_val_dout;
8'h70: r_iomem_rdata <= s_tim1_reg_dat_dout;
8'h80: begin
r_iomem_rdata <= {27'd0, s_psram_cfg_wait_dout};
@@ -654,14 +550,9 @@ module retrosoc #(
end
// data mux
assign s_mem_ready = (s_iomem_valid && r_iomem_ready) ||
s_spimem_ready || r_ram_ready ||
s_spimemio_cfgreg_sel || s_psram_ready;
assign s_mem_ready = (s_iomem_valid && r_iomem_ready) || r_ram_ready || s_psram_ready;
assign s_mem_rdata = (s_iomem_valid && r_iomem_ready) ? r_iomem_rdata :
s_spimem_ready ? s_spimem_rdata :
r_ram_ready ? ram_rdata_o :
s_spimemio_cfgreg_sel ? s_spimemio_cfgreg_dout :
s_psram_ready ? s_psram_rdata :
32'h0000_0000;
rtl/retrosoc_asic.v
-110
View File
@@ -32,18 +32,6 @@ module retrosoc_asic (
input clk_bypass_i_pad,
input ext_rst_n_i_pad,
output sys_clkdiv4_o_pad,
// HOUSEKEEPING SPI
input hk_sdi_i_pad,
output hk_sdo_o_pad,
input hk_csb_i_pad,
input hk_sck_i_pad,
// SPI FLASH
output flash_csb_o_pad,
output flash_clk_o_pad,
inout flash_io0_io_pad,
inout flash_io1_io_pad,
inout flash_io2_io_pad,
inout flash_io3_io_pad,
// UART
output uart_tx_o_pad,
input uart_rx_i_pad,
@@ -107,26 +95,6 @@ module retrosoc_asic (
wire s_sys_rst_n;
wire s_sys_clkdiv4_o;
// io
wire s_hk_sdi_i;
wire s_hk_sdo_o;
wire s_hk_csb_i;
wire s_hk_sck_i;
wire s_flash_csb_o;
wire s_flash_clk_o;
wire s_flash_clk_oeb_o;
wire s_flash_csb_oeb_o;
wire s_flash_io0_oeb_o;
wire s_flash_io1_oeb_o;
wire s_flash_io2_oeb_o;
wire s_flash_io3_oeb_o;
wire s_flash_io0_do_o;
wire s_flash_io1_do_o;
wire s_flash_io2_do_o;
wire s_flash_io3_do_o;
wire s_flash_io0_di_i;
wire s_flash_io1_di_i;
wire s_flash_io2_di_i;
wire s_flash_io3_di_i;
wire s_uart_tx_o;
wire s_uart_rx_i;
wire [15:0] s_gpio_out_o;
@@ -204,16 +172,6 @@ module retrosoc_asic (
tc_io_tri_pad u_clk_bypass_i_pad (.pad(clk_bypass_i_pad), .c2p(), .c2p_en(1'b0), .p2c(s_clk_bypass_i));
tc_io_tri_schmitt_pad u_ext_rst_n_i_pad (.pad(ext_rst_n_i_pad), .c2p(), .c2p_en(1'b0), .p2c(s_ext_rst_n_i));
tc_io_tri_pad u_sys_clkdiv4_o_pad (.pad(sys_clkdiv4_o_pad), .c2p(s_sys_clkdiv4_o), .c2p_en(1'b1), .p2c());
tc_io_tri_pad u_hk_sdi_i_pad (.pad(hk_sdi_i_pad), .c2p(), .c2p_en(1'b0), .p2c(s_hk_sdi_i));
tc_io_tri_pad u_hk_sdo_o_pad (.pad(hk_sdo_o_pad), .c2p(s_hk_sdo_o), .c2p_en(~s_hk_sdo_enb), .p2c());
tc_io_tri_pad u_hk_csb_i_pad (.pad(hk_csb_i_pad), .c2p(), .c2p_en(1'b0), .p2c(s_hk_csb_i));
tc_io_tri_pad u_hk_sck_i_pad (.pad(hk_sck_i_pad), .c2p(), .c2p_en(1'b0), .p2c(s_hk_sck_i));
tc_io_tri_pad u_flash_csb_o_pad (.pad(flash_csb_o_pad), .c2p(s_flash_csb_o), .c2p_en(~s_flash_csb_oeb_o), .p2c());
tc_io_tri_pad u_flash_clk_o_pad (.pad(flash_clk_o_pad), .c2p(s_flash_clk_o), .c2p_en(~s_flash_clk_oeb_o), .p2c());
tc_io_tri_pad u_flash_io0_io_pad (.pad(flash_io0_io_pad), .c2p(s_flash_io0_do_o), .c2p_en(~s_flash_io0_oeb_o), .p2c(s_flash_io0_di_i));
tc_io_tri_pad u_flash_io1_io_pad (.pad(flash_io1_io_pad), .c2p(s_flash_io1_do_o), .c2p_en(~s_flash_io1_oeb_o), .p2c(s_flash_io1_di_i));
tc_io_tri_pad u_flash_io2_io_pad (.pad(flash_io2_io_pad), .c2p(s_flash_io2_do_o), .c2p_en(~s_flash_io2_oeb_o), .p2c(s_flash_io2_di_i));
tc_io_tri_pad u_flash_io3_io_pad (.pad(flash_io3_io_pad), .c2p(s_flash_io3_do_o), .c2p_en(~s_flash_io3_oeb_o), .p2c(s_flash_io3_di_i));
tc_io_tri_pad u_uart_tx_o_pad (.pad(uart_tx_o_pad), .c2p(s_uart_tx_o), .c2p_en(1'b1), .p2c());
tc_io_tri_pad u_uart_rx_i_pad (.pad(uart_rx_i_pad), .c2p(), .c2p_en(1'b0), .p2c(s_uart_rx_i));
tc_io_tri_pad u_gpio_0_io_pad (.pad(gpio_0_io_pad), .c2p(s_gpio_out_o[0]), .c2p_en(~s_gpio_outenb_o[0]), .p2c(s_gpio_in_i[0]));
@@ -280,12 +238,6 @@ module retrosoc_asic (
retrosoc u_retrosoc (
.clk_i (s_sys_clk),
.rst_n_i (s_sys_rst_n),
.clk_ext_sel_i (s_hk_pll_bypass),
.hk_pt_i (s_hk_pt_rst),
.hk_pt_csb_i (s_hk_pt_csb),
.hk_pt_sck_i (s_hk_pt_sck),
.hk_pt_sdi_i (s_hk_pt_sdi),
.hk_pt_sdo_o (s_hk_pt_sdo),
.ram_wstrb_o (s_ram_wstrb),
.ram_addr_o (s_ram_addr),
.ram_wdata_o (s_ram_wdata),
@@ -295,37 +247,9 @@ module retrosoc_asic (
.gpio_pullupb_o (s_gpio_pullupb_o),
.gpio_pulldownb_o (s_gpio_pulldownb_o),
.gpio_outenb_o (s_gpio_outenb_o),
.spi_slv_ro_config_i (8'd0),
.spi_slv_ro_xtal_ena_i (s_hk_xtal_ena),
.spi_slv_ro_reg_ena_i (1'b0),
.spi_slv_ro_pll_cp_ena_i (s_hk_pll_cp_ena),
.spi_slv_ro_pll_vco_ena_i (s_hk_pll_vco_ena),
.spi_slv_ro_pll_bias_ena_i(s_hk_pll_bias_ena),
.spi_slv_ro_pll_trim_i (s_hk_pll_trim),
.spi_slv_ro_mfgr_id_i (s_hk_mfgr_id),
.spi_slv_ro_prod_id_i (s_hk_prod_id),
.spi_slv_ro_mask_rev_i (s_hk_mask_rev),
.uart_tx_o (s_uart_tx_o),
.uart_rx_i (s_uart_rx_i),
.irq_pin_i (s_irq_pin_i),
.irq_spi_i (s_hk_irq),
.trap_o (s_hk_trap),
.flash_csb_o (s_flash_csb_o),
.flash_clk_o (s_flash_clk_o),
.flash_clk_oeb_o (s_flash_clk_oeb_o),
.flash_csb_oeb_o (s_flash_csb_oeb_o),
.flash_io0_oeb_o (s_flash_io0_oeb_o),
.flash_io1_oeb_o (s_flash_io1_oeb_o),
.flash_io2_oeb_o (s_flash_io2_oeb_o),
.flash_io3_oeb_o (s_flash_io3_oeb_o),
.flash_io0_do_o (s_flash_io0_do_o),
.flash_io1_do_o (s_flash_io1_do_o),
.flash_io2_do_o (s_flash_io2_do_o),
.flash_io3_do_o (s_flash_io3_do_o),
.flash_io0_di_i (s_flash_io0_di_i),
.flash_io1_di_i (s_flash_io1_di_i),
.flash_io2_di_i (s_flash_io2_di_i),
.flash_io3_di_i (s_flash_io3_di_i),
.cust_uart_rx_i (s_cust_uart_rx_i),
.cust_uart_tx_o (s_cust_uart_tx_o),
.cust_pwm_pwm_o (s_cust_pwm_pwm_o),
@@ -360,40 +284,6 @@ module retrosoc_asic (
.cust_spfs_miso_i (s_cust_spfs_miso_i)
);
/* it can control the xtal oscillator, PLL which CANNOT be changed from the CPU */
/* without potentially killing it. */
// 'reg_ena': regulator enable
ravenna_spi u_ravenna_spi (
.RST (~s_sys_rst_n),
.SCK (s_hk_sck_i),
.SDI (s_hk_sdi_i),
.CSB (s_hk_csb_i),
.SDO (s_hk_sdo_o),
.sdo_enb (s_hk_sdo_enb),
.xtal_ena (s_hk_xtal_ena),
.reg_ena (),
.pll_vco_ena (s_hk_pll_vco_ena),
.pll_vco_in (s_hk_pll_vco_in),
.pll_cp_ena (s_hk_pll_cp_ena),
.pll_bias_ena (s_hk_pll_bias_ena),
.pll_trim (s_hk_pll_trim),
.pll_bypass (s_hk_pll_bypass),
.tm_nvcp (),
.irq (s_hk_irq),
.reset (s_hk_rst),
.trap (s_hk_trap),
.pass_thru_reset(s_hk_pt_rst),
.pass_thru_sck (s_hk_pt_sck),
.pass_thru_csb (s_hk_pt_csb),
.pass_thru_sdi (s_hk_pt_sdi),
.pass_thru_sdo (s_hk_pt_sdo),
.mask_rev_in (4'd0),
.mfgr_id (s_hk_mfgr_id),
.prod_id (s_hk_prod_id),
.mask_rev (s_hk_mask_rev)
);
spram_model u_spram_model (
.clk (s_sys_clk),
.wen (s_ram_wstrb),
rtl/retrosoc_def.v
-7
View File
@@ -1,7 +0,0 @@
`ifndef RETROSOC_DEF
`define SPIFS_START 32'h3000_0000
`define SPIFS_END 32'h3FFF_FFFF
`endif
rtl/retrosoc_tb.v
-10
View File
@@ -64,16 +64,6 @@ module retrosoc_tb;
.pll_cfg_2_i_pad (r_pll_cfg[2]),
.clk_bypass_i_pad (~r_pll_en),
.ext_rst_n_i_pad (r_rst_n),
.hk_sdi_i_pad (1'b1),
.hk_sdo_o_pad (),
.hk_csb_i_pad (1'b1),
.hk_sck_i_pad (1'b0),
.flash_csb_o_pad (s_flash_csb),
.flash_clk_o_pad (s_flash_clk),
.flash_io0_io_pad (s_flash_io0),
.flash_io1_io_pad (s_flash_io1),
.flash_io2_io_pad (s_flash_io2),
.flash_io3_io_pad (s_flash_io3),
.uart_tx_o_pad (s_uart_tx),
.uart_rx_i_pad (1'b0),
.gpio_0_io_pad (),