admin/retroSoC
1
0 Fork 0
mirror of https://github.com/retroSoC/retroSoC.git synced 2026-11-05 06:32:37 +00:00
Code Issues Packages Projects Releases Wiki Activity

fix: fix counter/timer bugs

Browse Source
This commit is contained in:
maksyuki committed 2025-02-28 09:46:52 +08:00
1 parent c06165cc3a
commit 18e50b43f1
3 files changed
+11 -7
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

rtl/Makefile
+3 -3
View File
@@ -132,12 +132,12 @@ LDS_PATH := ../crt/sections.lds
# +behv_wave
retrosim: retrosoc_tb.vvp $(FIRMWARE_NAME).elf
ln -sf $(FIRMWARE_NAME).hex mem_Q128_bottom.vmf
vvp -l run.log -N $< +$(RTL_SIM_PLLEN) +$(RTL_SIM_PLLCFG) +behv_$(WAVE) -fst
vvp -l run.log -N $< +$(RTL_SIM_PLLEN) +$(RTL_SIM_PLLCFG) +behv_$(WAVE) +sim_$(SIM_TOOL) -fst
# +syn_wave
retrosynsim: retrosoc_syn_tb.vvp $(FIRMWARE_NAME).elf
ln -sf $(FIRMWARE_NAME).hex mem_Q128_bottom.vmf
vvp -l synrun.log -N $< +$(RTL_SIM_PLLEN) +$(RTL_SIM_PLLCFG) +syn_$(WAVE) -fst
vvp -l synrun.log -N $< +$(RTL_SIM_PLLEN) +$(RTL_SIM_PLLCFG) +syn_$(WAVE) +sim_$(SIM_TOOL) -fst
retrosoc_tb.vvp:
@@ -172,7 +172,7 @@ vsim: vcomp
bsub -Is ./simv -l vsim.log +$(RTL_SIM_PLLEN) +$(RTL_SIM_PLLCFG) +behv_$(WAVE) +sim_$(SIM_TOOL)
vnetsim: vnetcomp
bsub -Is ./net_simv -l vnetsim.log +$(RTL_SIM_PLLEN) +$(RTL_SIM_PLLCFG) +behv_$(WAVE) +sim_$(SIM_TOOL) +bus_conflict_off
bsub -Is ./net_simv -l vnetsim.log +$(RTL_SIM_PLLEN) +$(RTL_SIM_PLLCFG) +syn_$(WAVE) +sim_$(SIM_TOOL) +bus_conflict_off
vwave:
bsub -Is verdi -ssf retrosoc_tb.fsdb -nologo &
rtl/retrosoc.v
+2 -2
View File
@@ -629,10 +629,10 @@ module retrosoc #(
r_iomem_rdata <= {30'd0, r_irq_8_in_src};
if (s_iomem_wstrb[0]) r_irq_8_in_src <= s_iomem_wdata[1:0];
end
8'h5c: r_iomem_rdata <= {28'd0, s_tim0_reg_cfg_dout};
8'h5c: r_iomem_rdata <= s_tim0_reg_cfg_dout;
8'h60: r_iomem_rdata <= s_tim0_reg_val_dout;
8'h64: r_iomem_rdata <= s_tim0_reg_dat_dout;
8'h68: r_iomem_rdata <= {28'd0, s_tim1_reg_cfg_dout};
8'h68: r_iomem_rdata <= s_tim1_reg_cfg_dout;
8'h6c: r_iomem_rdata <= s_tim1_reg_val_dout;
8'h70: r_iomem_rdata <= s_tim1_reg_dat_dout;
8'h80: begin
rtl/retrosoc_tb.v
+6 -2
View File
@@ -194,6 +194,7 @@ module retrosoc_tb;
initial begin
if ($test$plusargs("behv_wave")) begin
$display("gen behv sim wave");
if ($test$plusargs("sim_iver")) begin
$dumpfile("retrosoc_tb.fst");
$dumpvars(0, retrosoc_tb);
@@ -206,15 +207,18 @@ module retrosoc_tb;
end
$finish;
end else if ($test$plusargs("syn_wave")) begin
$display("gen syn sim wave");
if ($test$plusargs("sim_iver")) begin
$display("gen retrosoc_syn_tb.fst");
$dumpfile("retrosoc_syn_tb.fst");
$dumpvars(0, retrosoc_tb);
end else begin
// $fsdbDumpfile("retrosoc_syn_tb.fsdb");
// $fsdbDumpvars(0);
end
repeat (1500) begin
repeat (5000) @(posedge r_xtal_clk);
repeat (10) begin
$display("hello");
repeat (100) @(posedge r_xtal_clk);
end
$finish;
end