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feat: refactor RIB to RIBP: Update tests and scripts to reflect RIBP interface changes

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- Updated test cases in , , , , , , , and  to replace references from RIB to RIBP.
- Modified file names and paths in tests to align with the new RIBP naming conventions.
- Ensured that all assertions and checks in the tests are consistent with the updated RIBP interfaces and functionality.
- Added a new test for migrating user core RIBP interfaces in .
This commit is contained in:
maksyuki committed 2026-08-04 10:56:36 +08:00
1 parent bef5881149
commit 1b4b53c650
139 files changed
+3363 -3217
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tests/test_sdram.py
+10 -10
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@@ -36,12 +36,12 @@ def test_sdram_controller_preserves_full_and_masked_writes(tmp_path: Path) -> No
"+define+SV_ASSRT_DISABLE",
f"+incdir+{generated / 'rtl'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram_clkgen.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram_reg.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram_core.sv"),
str(ROOT / "rtl/ip/ribp/memory/sdram.sv"),
str(ROOT / "rtl/ip/ribp/memory/sdram_clkgen.sv"),
str(ROOT / "rtl/ip/ribp/memory/sdram_reg.sv"),
str(ROOT / "rtl/ip/ribp/memory/sdram_core.sv"),
str(ROOT / "rtl/mini/dv/verilator/rtl/sdram_verilator_model.sv"),
str(ROOT / "tests/rtl/sdram_data_tb.sv"),
"",
@@ -97,12 +97,12 @@ def test_sdram_controller_preserves_data_with_micron_timing_model(tmp_path: Path
f"+incdir+{generated / 'rtl'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
f"+incdir+{ROOT / 'rtl/managed/third_party/model/sdram'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram_clkgen.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram_reg.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram_core.sv"),
str(ROOT / "rtl/ip/ribp/memory/sdram.sv"),
str(ROOT / "rtl/ip/ribp/memory/sdram_clkgen.sv"),
str(ROOT / "rtl/ip/ribp/memory/sdram_reg.sv"),
str(ROOT / "rtl/ip/ribp/memory/sdram_core.sv"),
str(ROOT / "tests/rtl/sdram_data_tb.sv"),
"",
]