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feat: refactor RIB to RIBP: Update tests and scripts to reflect RIBP interface changes

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- Updated test cases in , , , , , , , and  to replace references from RIB to RIBP.
- Modified file names and paths in tests to align with the new RIBP naming conventions.
- Ensured that all assertions and checks in the tests are consistent with the updated RIBP interfaces and functionality.
- Added a new test for migrating user core RIBP interfaces in .
This commit is contained in:
maksyuki committed 2026-08-04 10:56:36 +08:00
1 parent bef5881149
commit 1b4b53c650
139 files changed
+3363 -3217
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ATTRIBUTIONS.md
+10 -10
View File
@@ -16,26 +16,26 @@ The header in rtl/tech/tc_clk.sv also states the Solderpad Hardware License, Ver
The following RTL files retain the original header from the Ravenna example SoC project, which refers to a design using PicoRV32 in ASIC:
- rtl/ip/rib/peripheral/gpio.sv
- rtl/ip/rib/peripheral/timer.sv
- rtl/ip/rib/serial/uart.sv
- rtl/ip/ribp/peripheral/gpio.sv
- rtl/ip/ribp/peripheral/timer.sv
- rtl/ip/ribp/serial/uart.sv
The preserved notice attributes the work to Clifford Wolf and Tim Edwards.
## 3. Hirosh Dabui
The SDRAM controller implementation in rtl/ip/rib/memory/sdram_core.sv retains the original copyright notice attributed to Hirosh Dabui.
The SDRAM controller implementation in rtl/ip/ribp/memory/sdram_core.sv retains the original copyright notice attributed to Hirosh Dabui.
## 4. EmbedFire
Several SPI/I2C-related RTL files retain the original attribution to EmbedFire and refer to source files such as sd_init.v, sd_write.v, sd_read.v, data_rw_ctrl.v, and i2c_ctrl.v:
- rtl/ip/rib/serial/i2c_core.sv
- rtl/ip/rib/storage/spisd_core.sv
- rtl/ip/rib/storage/spisd_data.sv
- rtl/ip/rib/storage/spisd_init.sv
- rtl/ip/rib/storage/spisd_read.sv
- rtl/ip/rib/storage/spisd_write.sv
- rtl/ip/ribp/serial/i2c_core.sv
- rtl/ip/ribp/storage/spisd_core.sv
- rtl/ip/ribp/storage/spisd_data.sv
- rtl/ip/ribp/storage/spisd_init.sv
- rtl/ip/ribp/storage/spisd_read.sv
- rtl/ip/ribp/storage/spisd_write.sv
These headers state that the original code was published on GitHub by EmbedFire, but that the original license was not specified in the retained header.
Makefile
+2 -2
View File
@@ -210,7 +210,7 @@ endif
benchmark-report \
pin-map check-pin-map soc-topology check-soc-topology user-extensions check-user-extensions \
check-clock-reset-domains tech-cell-test rtl-lint check-rtl-lint \
formal formal-bus formal-rib-adapter formal-spill-register formal-rib2apb formal-clean formal-doctor
formal formal-bus formal-rib-adapter formal-spill-register formal-ribp2apb formal-clean formal-doctor
.NOTPARALLEL: setup
help:
@@ -235,7 +235,7 @@ help:
' check-user-extensions validate the canonical user-extension map' \
' check-clock-reset-domains validate the root clock/reset and CDC inventory' \
' rtl-lint | check-rtl-lint run/check strict Verilator RTL lint warnings' \
' formal | formal-bus | formal-rib-adapter | formal-spill-register | formal-rib2apb run SBY protocol proofs' \
' formal | formal-bus | formal-rib-adapter | formal-spill-register | formal-ribp2apb run SBY protocol proofs' \
' formal-sysctrl | formal-pll-rcu | formal-gpio-user run SBY peripheral-control proofs' \
' formal-doctor check the SBY, Yosys, sv2v, and Bitwuzla formal toolchain' \
' benchmark-report run the benchmark profile and write meta/performance.json' \
NOTICE
+3 -3
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@@ -5,8 +5,8 @@ This repository includes RTL source files that preserve third-party copyright an
The following third-party projects or authors are referenced in the RTL source headers currently present in this repository:
- ETH Zurich and University of Bologna: notices are preserved in several RTL files under rtl/managed/clusterip/, rtl/managed/mpw/core/username7/ibex/, and in rtl/tech/tc_clk.sv.
- Ravenna / PicoRV32 in ASIC: notices are preserved in rtl/ip/rib/peripheral/gpio.sv, rtl/ip/rib/peripheral/timer.sv, and rtl/ip/rib/serial/uart.sv.
- Hirosh Dabui: the original copyright notice is preserved in rtl/ip/rib/memory/sdram_core.sv.
- EmbedFire: attribution is preserved in rtl/ip/rib/serial/i2c_core.sv and the SPI SD card related files under rtl/ip/rib/storage/.
- Ravenna / PicoRV32 in ASIC: notices are preserved in rtl/ip/ribp/peripheral/gpio.sv, rtl/ip/ribp/peripheral/timer.sv, and rtl/ip/ribp/serial/uart.sv.
- Hirosh Dabui: the original copyright notice is preserved in rtl/ip/ribp/memory/sdram_core.sv.
- EmbedFire: attribution is preserved in rtl/ip/ribp/serial/i2c_core.sv and the SPI SD card related files under rtl/ip/ribp/storage/.
These notices are included solely to preserve attribution for the retained third-party source material. They do not alter the licensing terms of the retroSoC repository itself, which is distributed under the Mulan PSL v2 license.
app/apps/benchmark/main.c
+1 -1
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@@ -114,7 +114,7 @@ static void rs_benchmark_report(const char *region, const char *operation, uint3
rs_benchmark_put_hex(checksum);
rs_benchmark_put_counter(" cycles=", cycles);
rs_benchmark_put_counter(" mgmt_wait=", snapshot->mgmt_wait);
rs_benchmark_put_counter(" rib_wait=", snapshot->rib_wait);
rs_benchmark_put_counter(" ribp_wait=", snapshot->ribp_wait);
rs_benchmark_put_counter(" sdram_wait=", snapshot->sdram_wait);
rs_benchmark_put_counter(" psram_wait=", snapshot->psram_wait);
rs_benchmark_put_counter(" flash_wait=", snapshot->flash_wait);
config/dependencies.lock.json
+5 -5
View File
@@ -62,19 +62,19 @@
},
"cluster_archinfo": {"url": "https://github.com/retroSoC/archinfo.git", "revision": "d65dd13c83a1176668bf5178004814a1551bf6ba", "destination": "rtl/managed/clusterip/archinfo", "license": "NOASSERTION"},
"cluster_clint": {"url": "https://github.com/retroSoC/clint.git", "revision": "ce49f1a5501c0a9f18c0e3f358417648f3f2fb18", "destination": "rtl/managed/clusterip/clint", "license": "NOASSERTION"},
"cluster_common": {"url": "https://github.com/retroSoC/common.git", "revision": "215e47f3774a0f7a493aa2a74da68861d3b6d397", "destination": "rtl/managed/clusterip/common", "license": "NOASSERTION"},
"cluster_common": {"url": "https://github.com/retroSoC/common.git", "revision": "f666d8f04977157fe282ca9873c45aad6757c37f", "destination": "rtl/managed/clusterip/common", "license": "NOASSERTION"},
"cluster_crc": {"url": "https://github.com/retroSoC/crc.git", "revision": "4654a63d06d487b5b9fe22af228c36c736b90bad", "destination": "rtl/managed/clusterip/crc", "license": "NOASSERTION"},
"cluster_i2c": {"url": "https://github.com/retroSoC/i2c.git", "revision": "73b024547c5cd70fb8bf801cc7757db2536c604f", "destination": "rtl/managed/clusterip/i2c", "license": "NOASSERTION"},
"cluster_i2s": {"url": "https://github.com/retroSoC/i2s.git", "revision": "bd0978e8b45e4cf4c1335a1fa7311385d2a4e805", "destination": "rtl/managed/clusterip/i2s", "license": "NOASSERTION"},
"cluster_plic": {"url": "https://github.com/retroSoC/plic.git", "revision": "c851d93829d2e75b224003a058e718925855c0cc", "destination": "rtl/managed/clusterip/plic", "license": "NOASSERTION"},
"cluster_ps2": {"url": "https://github.com/retroSoC/ps2.git", "revision": "60921e0f72d6113f8615d03ce54567388fc2410f", "destination": "rtl/managed/clusterip/ps2", "license": "NOASSERTION"},
"cluster_pwm": {"url": "https://github.com/retroSoC/pwm.git", "revision": "0777ef085c661d2b103f2fa0f8519f97eea3c950", "destination": "rtl/managed/clusterip/pwm", "license": "NOASSERTION"},
"cluster_pwm": {"url": "https://github.com/retroSoC/pwm.git", "revision": "c631ede87506d34f714167313ba69b196c0bea72", "destination": "rtl/managed/clusterip/pwm", "license": "NOASSERTION"},
"cluster_rng": {"url": "https://github.com/retroSoC/rng.git", "revision": "7374e1e7f25bfd1ff9954ea99f19b77a583def29", "destination": "rtl/managed/clusterip/rng", "license": "NOASSERTION"},
"cluster_rtc": {"url": "https://github.com/retroSoC/rtc.git", "revision": "69963b8424cb00e04c8be70157b8ca738464e342", "destination": "rtl/managed/clusterip/rtc", "license": "NOASSERTION"},
"cluster_rtc": {"url": "https://github.com/retroSoC/rtc.git", "revision": "c6cc82f7530eea0b87ebe1d2cde2a67c9268c0db", "destination": "rtl/managed/clusterip/rtc", "license": "NOASSERTION"},
"cluster_spi": {"url": "https://github.com/retroSoC/spi.git", "revision": "515cb408806584525605b4747db5e890dbdf1928", "destination": "rtl/managed/clusterip/spi", "license": "NOASSERTION"},
"cluster_timer": {"url": "https://github.com/retroSoC/timer.git", "revision": "0c44b0d8b742c6a477fda15a812cf22962b54dd8", "destination": "rtl/managed/clusterip/timer", "license": "NOASSERTION"},
"cluster_timer": {"url": "https://github.com/retroSoC/timer.git", "revision": "75fa45d786739e1d5ab6d1e10520be2c2f0d022a", "destination": "rtl/managed/clusterip/timer", "license": "NOASSERTION"},
"cluster_uart": {"url": "https://github.com/retroSoC/uart.git", "revision": "eca12213ba06f42e0a6dd0f27907fd4c447e2774", "destination": "rtl/managed/clusterip/uart", "license": "NOASSERTION"},
"cluster_wdg": {"url": "https://github.com/retroSoC/wdg.git", "revision": "b2603c1faeba96603392f0fe9e692e645d7e061f", "destination": "rtl/managed/clusterip/wdg", "license": "NOASSERTION"}
"cluster_wdg": {"url": "https://github.com/retroSoC/wdg.git", "revision": "86981d54b1b13e6e82d25ab0a369de67ff946dcb", "destination": "rtl/managed/clusterip/wdg", "license": "NOASSERTION"}
},
"archives": {
"fatfs": {
crt/include/retrosoc/core/soc.h
+126 -126
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@@ -38,125 +38,125 @@
#define RS_SOC_REG32(base, offset) (*(volatile uint32_t *)(uintptr_t)((base) + (offset)))
// gpio
#define reg_gpio_oe RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x00))
#define reg_gpio_cs RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x04))
#define reg_gpio_pu RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x08))
#define reg_gpio_pd RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x0C))
#define reg_gpio_do RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x10))
#define reg_gpio_di RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x14))
#define reg_gpio_ien RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x18))
#define reg_gpio_itype0 RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x1C))
#define reg_gpio_itype1 RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x20))
#define reg_gpio_istat RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x24))
#define reg_gpio_iofcfg RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x28))
#define reg_gpio_pinmux RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x2C))
#define reg_gpio_user_sel RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x30))
#define reg_gpio_user_lock RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x34))
#define reg_gpio_user_status RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x38))
#define reg_gpio_oe RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x00))
#define reg_gpio_cs RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x04))
#define reg_gpio_pu RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x08))
#define reg_gpio_pd RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x0C))
#define reg_gpio_do RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x10))
#define reg_gpio_di RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x14))
#define reg_gpio_ien RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x18))
#define reg_gpio_itype0 RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x1C))
#define reg_gpio_itype1 RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x20))
#define reg_gpio_istat RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x24))
#define reg_gpio_iofcfg RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x28))
#define reg_gpio_pinmux RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x2C))
#define reg_gpio_user_sel RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x30))
#define reg_gpio_user_lock RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x34))
#define reg_gpio_user_status RS_SOC_REG32(RS_SOC_RIBP_GPIO_BASE, UINT32_C(0x38))
// uart0
#define reg_uart0_clkdiv RS_SOC_REG32(RS_SOC_RIB_UART0_BASE, UINT32_C(0x00))
#define reg_uart0_data RS_SOC_REG32(RS_SOC_RIB_UART0_BASE, UINT32_C(0x04))
#define reg_uart0_clkdiv RS_SOC_REG32(RS_SOC_RIBP_UART0_BASE, UINT32_C(0x00))
#define reg_uart0_data RS_SOC_REG32(RS_SOC_RIBP_UART0_BASE, UINT32_C(0x04))
// tim0
#define reg_tim0_cfg RS_SOC_REG32(RS_SOC_RIB_TIM0_BASE, UINT32_C(0x00))
#define reg_tim0_rld RS_SOC_REG32(RS_SOC_RIB_TIM0_BASE, UINT32_C(0x04))
#define reg_tim0_val RS_SOC_REG32(RS_SOC_RIB_TIM0_BASE, UINT32_C(0x08))
#define reg_tim0_cfg RS_SOC_REG32(RS_SOC_RIBP_TIM0_BASE, UINT32_C(0x00))
#define reg_tim0_rld RS_SOC_REG32(RS_SOC_RIBP_TIM0_BASE, UINT32_C(0x04))
#define reg_tim0_val RS_SOC_REG32(RS_SOC_RIBP_TIM0_BASE, UINT32_C(0x08))
// tim1
#define reg_tim1_cfg RS_SOC_REG32(RS_SOC_RIB_TIM1_BASE, UINT32_C(0x00))
#define reg_tim1_rld RS_SOC_REG32(RS_SOC_RIB_TIM1_BASE, UINT32_C(0x04))
#define reg_tim1_val RS_SOC_REG32(RS_SOC_RIB_TIM1_BASE, UINT32_C(0x08))
#define reg_tim1_cfg RS_SOC_REG32(RS_SOC_RIBP_TIM1_BASE, UINT32_C(0x00))
#define reg_tim1_rld RS_SOC_REG32(RS_SOC_RIBP_TIM1_BASE, UINT32_C(0x04))
#define reg_tim1_val RS_SOC_REG32(RS_SOC_RIBP_TIM1_BASE, UINT32_C(0x08))
// psram
#define reg_psram_wait RS_SOC_REG32(RS_SOC_RIB_PSRAM_BASE, UINT32_C(0x00))
#define reg_psram_chd RS_SOC_REG32(RS_SOC_RIB_PSRAM_BASE, UINT32_C(0x04))
#define reg_psram_init RS_SOC_REG32(RS_SOC_RIB_PSRAM_BASE, UINT32_C(0x08))
#define reg_psram_wait RS_SOC_REG32(RS_SOC_RIBP_PSRAM_BASE, UINT32_C(0x00))
#define reg_psram_chd RS_SOC_REG32(RS_SOC_RIBP_PSRAM_BASE, UINT32_C(0x04))
#define reg_psram_init RS_SOC_REG32(RS_SOC_RIBP_PSRAM_BASE, UINT32_C(0x08))
// spisd
#define reg_spisd_mode RS_SOC_REG32(RS_SOC_RIB_SPISD_BASE, UINT32_C(0x00))
#define reg_spisd_clkdiv RS_SOC_REG32(RS_SOC_RIB_SPISD_BASE, UINT32_C(0x04))
#define reg_spisd_addr RS_SOC_REG32(RS_SOC_RIB_SPISD_BASE, UINT32_C(0x08))
#define reg_spisd_txdata RS_SOC_REG32(RS_SOC_RIB_SPISD_BASE, UINT32_C(0x0C))
#define reg_spisd_rxdata RS_SOC_REG32(RS_SOC_RIB_SPISD_BASE, UINT32_C(0x10))
#define reg_spisd_status RS_SOC_REG32(RS_SOC_RIB_SPISD_BASE, UINT32_C(0x14))
#define reg_spisd_sync RS_SOC_REG32(RS_SOC_RIB_SPISD_BASE, UINT32_C(0x18))
#define reg_spisd_mode RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x00))
#define reg_spisd_clkdiv RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x04))
#define reg_spisd_addr RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x08))
#define reg_spisd_txdata RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x0C))
#define reg_spisd_rxdata RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x10))
#define reg_spisd_status RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x14))
#define reg_spisd_sync RS_SOC_REG32(RS_SOC_RIBP_SPISD_BASE, UINT32_C(0x18))
// i2c0
#define reg_i2c0_clkdiv RS_SOC_REG32(RS_SOC_RIB_I2C0_BASE, UINT32_C(0x00))
#define reg_i2c0_devaddr RS_SOC_REG32(RS_SOC_RIB_I2C0_BASE, UINT32_C(0x04))
#define reg_i2c0_regaddr RS_SOC_REG32(RS_SOC_RIB_I2C0_BASE, UINT32_C(0x08))
#define reg_i2c0_txdata RS_SOC_REG32(RS_SOC_RIB_I2C0_BASE, UINT32_C(0x0C))
#define reg_i2c0_rxdata RS_SOC_REG32(RS_SOC_RIB_I2C0_BASE, UINT32_C(0x10))
#define reg_i2c0_xfer RS_SOC_REG32(RS_SOC_RIB_I2C0_BASE, UINT32_C(0x14))
#define reg_i2c0_cfg RS_SOC_REG32(RS_SOC_RIB_I2C0_BASE, UINT32_C(0x18))
#define reg_i2c0_status RS_SOC_REG32(RS_SOC_RIB_I2C0_BASE, UINT32_C(0x1C))
#define reg_i2c0_clkdiv RS_SOC_REG32(RS_SOC_RIBP_I2C0_BASE, UINT32_C(0x00))
#define reg_i2c0_devaddr RS_SOC_REG32(RS_SOC_RIBP_I2C0_BASE, UINT32_C(0x04))
#define reg_i2c0_regaddr RS_SOC_REG32(RS_SOC_RIBP_I2C0_BASE, UINT32_C(0x08))
#define reg_i2c0_txdata RS_SOC_REG32(RS_SOC_RIBP_I2C0_BASE, UINT32_C(0x0C))
#define reg_i2c0_rxdata RS_SOC_REG32(RS_SOC_RIBP_I2C0_BASE, UINT32_C(0x10))
#define reg_i2c0_xfer RS_SOC_REG32(RS_SOC_RIBP_I2C0_BASE, UINT32_C(0x14))
#define reg_i2c0_cfg RS_SOC_REG32(RS_SOC_RIBP_I2C0_BASE, UINT32_C(0x18))
#define reg_i2c0_status RS_SOC_REG32(RS_SOC_RIBP_I2C0_BASE, UINT32_C(0x1C))
// i2s
#define reg_i2s_mode RS_SOC_REG32(RS_SOC_RIB_I2S_BASE, UINT32_C(0x00))
#define reg_i2s_format RS_SOC_REG32(RS_SOC_RIB_I2S_BASE, UINT32_C(0x04))
#define reg_i2s_upbound RS_SOC_REG32(RS_SOC_RIB_I2S_BASE, UINT32_C(0x08))
#define reg_i2s_lowbound RS_SOC_REG32(RS_SOC_RIB_I2S_BASE, UINT32_C(0x0C))
#define reg_i2s_recven RS_SOC_REG32(RS_SOC_RIB_I2S_BASE, UINT32_C(0x10))
#define reg_i2s_txdata RS_SOC_REG32(RS_SOC_RIB_I2S_BASE, UINT32_C(0x14))
#define reg_i2s_rxdata RS_SOC_REG32(RS_SOC_RIB_I2S_BASE, UINT32_C(0x18))
#define reg_i2s_status RS_SOC_REG32(RS_SOC_RIB_I2S_BASE, UINT32_C(0x1C))
#define reg_i2s_mode RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x00))
#define reg_i2s_format RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x04))
#define reg_i2s_upbound RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x08))
#define reg_i2s_lowbound RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x0C))
#define reg_i2s_recven RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x10))
#define reg_i2s_txdata RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x14))
#define reg_i2s_rxdata RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x18))
#define reg_i2s_status RS_SOC_REG32(RS_SOC_RIBP_I2S_BASE, UINT32_C(0x1C))
// onewire
#define reg_onewire_clkdiv RS_SOC_REG32(RS_SOC_RIB_ONEWIRE_BASE, UINT32_C(0x00))
#define reg_onewire_zerocnt RS_SOC_REG32(RS_SOC_RIB_ONEWIRE_BASE, UINT32_C(0x04))
#define reg_onewire_onecnt RS_SOC_REG32(RS_SOC_RIB_ONEWIRE_BASE, UINT32_C(0x08))
#define reg_onewire_rstcnt RS_SOC_REG32(RS_SOC_RIB_ONEWIRE_BASE, UINT32_C(0x0C))
#define reg_onewire_txdata RS_SOC_REG32(RS_SOC_RIB_ONEWIRE_BASE, UINT32_C(0x10))
#define reg_onewire_ctrl RS_SOC_REG32(RS_SOC_RIB_ONEWIRE_BASE, UINT32_C(0x14))
#define reg_onewire_status RS_SOC_REG32(RS_SOC_RIB_ONEWIRE_BASE, UINT32_C(0x18))
#define reg_onewire_clkdiv RS_SOC_REG32(RS_SOC_RIBP_ONEWIRE_BASE, UINT32_C(0x00))
#define reg_onewire_zerocnt RS_SOC_REG32(RS_SOC_RIBP_ONEWIRE_BASE, UINT32_C(0x04))
#define reg_onewire_onecnt RS_SOC_REG32(RS_SOC_RIBP_ONEWIRE_BASE, UINT32_C(0x08))
#define reg_onewire_rstcnt RS_SOC_REG32(RS_SOC_RIBP_ONEWIRE_BASE, UINT32_C(0x0C))
#define reg_onewire_txdata RS_SOC_REG32(RS_SOC_RIBP_ONEWIRE_BASE, UINT32_C(0x10))
#define reg_onewire_ctrl RS_SOC_REG32(RS_SOC_RIBP_ONEWIRE_BASE, UINT32_C(0x14))
#define reg_onewire_status RS_SOC_REG32(RS_SOC_RIBP_ONEWIRE_BASE, UINT32_C(0x18))
// xpi
#define reg_xpi_cfgidx RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x00))
#define reg_xpi_accmd RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x04))
#define reg_xpi_mmstad RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x08))
#define reg_xpi_mmoffst RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x0C))
#define reg_xpi_mode RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x10))
#define reg_xpi_nss RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x14))
#define reg_xpi_clkdiv RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x18))
#define reg_xpi_rdwr RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x1C))
#define reg_xpi_revdat RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x20))
#define reg_xpi_txupb RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x24))
#define reg_xpi_txlowb RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x28))
#define reg_xpi_rxupb RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x2C))
#define reg_xpi_rxlowb RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x30))
#define reg_xpi_flush RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x34))
#define reg_xpi_cmdtyp RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x38))
#define reg_xpi_cmdlen RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x3C))
#define reg_xpi_cmddat RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x40))
#define reg_xpi_adrtyp RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x44))
#define reg_xpi_adrlen RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x48))
#define reg_xpi_adrdat RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x4C))
#define reg_xpi_alttyp RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x50))
#define reg_xpi_altlen RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x54))
#define reg_xpi_altdat RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x58))
#define reg_xpi_tdulen RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x5C))
#define reg_xpi_rdulen RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x60))
#define reg_xpi_dattyp RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x64))
#define reg_xpi_datlen RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x68))
#define reg_xpi_datbit RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x6C))
#define reg_xpi_hlvlen RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x70))
#define reg_xpi_txdata RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x74))
#define reg_xpi_rxdata RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x78))
#define reg_xpi_start RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x7C))
#define reg_xpi_status RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x80))
#define reg_xpi_cfgidx RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x00))
#define reg_xpi_accmd RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x04))
#define reg_xpi_mmstad RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x08))
#define reg_xpi_mmoffst RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x0C))
#define reg_xpi_mode RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x10))
#define reg_xpi_nss RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x14))
#define reg_xpi_clkdiv RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x18))
#define reg_xpi_rdwr RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x1C))
#define reg_xpi_revdat RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x20))
#define reg_xpi_txupb RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x24))
#define reg_xpi_txlowb RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x28))
#define reg_xpi_rxupb RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x2C))
#define reg_xpi_rxlowb RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x30))
#define reg_xpi_flush RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x34))
#define reg_xpi_cmdtyp RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x38))
#define reg_xpi_cmdlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x3C))
#define reg_xpi_cmddat RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x40))
#define reg_xpi_adrtyp RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x44))
#define reg_xpi_adrlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x48))
#define reg_xpi_adrdat RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x4C))
#define reg_xpi_alttyp RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x50))
#define reg_xpi_altlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x54))
#define reg_xpi_altdat RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x58))
#define reg_xpi_tdulen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x5C))
#define reg_xpi_rdulen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x60))
#define reg_xpi_dattyp RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x64))
#define reg_xpi_datlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x68))
#define reg_xpi_datbit RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x6C))
#define reg_xpi_hlvlen RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x70))
#define reg_xpi_txdata RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x74))
#define reg_xpi_rxdata RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x78))
#define reg_xpi_start RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x7C))
#define reg_xpi_status RS_SOC_REG32(RS_SOC_RIBP_XPI_BASE, UINT32_C(0x80))
// dma(32b xfer, hardware trigger by I2S fifo, QSPI fifo)
#define reg_dma_mode RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x00))
#define reg_dma_srcaddr RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x04))
#define reg_dma_srcincr RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x08))
#define reg_dma_dstaddr RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x0C))
#define reg_dma_dstincr RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x10))
#define reg_dma_xferlen RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x14))
#define reg_dma_start RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x18))
#define reg_dma_stop RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x1C))
#define reg_dma_reset RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x20))
#define reg_dma_status RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x24))
#define reg_dma_fsm RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x28))
#define reg_dma_error_status RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x2C))
#define reg_dma_error_addr RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x30))
#define reg_dma_mode RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x00))
#define reg_dma_srcaddr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x04))
#define reg_dma_srcincr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x08))
#define reg_dma_dstaddr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x0C))
#define reg_dma_dstincr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x10))
#define reg_dma_xferlen RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x14))
#define reg_dma_start RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x18))
#define reg_dma_stop RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x1C))
#define reg_dma_reset RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x20))
#define reg_dma_status RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x24))
#define reg_dma_fsm RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x28))
#define reg_dma_error_status RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x2C))
#define reg_dma_error_addr RS_SOC_REG32(RS_SOC_RIBP_DMA_BASE, UINT32_C(0x30))
#define RS_SOC_DMA_ERROR_PENDING UINT32_C(0x00000001)
#define RS_SOC_DMA_ERROR_RESPONSE_SHIFT 1U
#define RS_SOC_DMA_ERROR_RESPONSE_MASK UINT32_C(0x0000000E)
// sys ctrl
#define RS_SOC_SYSCTRL_REG32(offset) RS_SOC_REG32(RS_SOC_RIB_SYSCTRL_BASE, (offset))
#define reg_sysctrl_coresel RS_SOC_REG32(RS_SOC_RIB_SYSCTRL_BASE, UINT32_C(0x00))
#define reg_sysctrl_ipsel RS_SOC_REG32(RS_SOC_RIB_SYSCTRL_BASE, UINT32_C(0x04))
#define RS_SOC_SYSCTRL_REG32(offset) RS_SOC_REG32(RS_SOC_RIBP_SYSCTRL_BASE, (offset))
#define reg_sysctrl_coresel RS_SOC_REG32(RS_SOC_RIBP_SYSCTRL_BASE, UINT32_C(0x00))
#define reg_sysctrl_ipsel RS_SOC_REG32(RS_SOC_RIBP_SYSCTRL_BASE, UINT32_C(0x04))
#define reg_sysctrl_pll_cfg RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PLL_CFG_OFFSET)
#define reg_sysctrl_pll_cmd RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PLL_CMD_OFFSET)
/* Status: bit 0 pending (W1C), bit 1 write, bits 3:2 reason (1 unmapped, 2 reserved). */
@@ -175,8 +175,8 @@
#define reg_sysctrl_perf_user_wait_hi RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_USER_WAIT_HI_OFFSET)
#define reg_sysctrl_perf_dma_wait_lo RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_DMA_WAIT_LO_OFFSET)
#define reg_sysctrl_perf_dma_wait_hi RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_DMA_WAIT_HI_OFFSET)
#define reg_sysctrl_perf_rib_wait_lo RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_RIB_WAIT_LO_OFFSET)
#define reg_sysctrl_perf_rib_wait_hi RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_RIB_WAIT_HI_OFFSET)
#define reg_sysctrl_perf_ribp_wait_lo RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_RIBP_WAIT_LO_OFFSET)
#define reg_sysctrl_perf_ribp_wait_hi RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_RIBP_WAIT_HI_OFFSET)
#define reg_sysctrl_perf_apb_wait_lo RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_APB_WAIT_LO_OFFSET)
#define reg_sysctrl_perf_apb_wait_hi RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_APB_WAIT_HI_OFFSET)
#define reg_sysctrl_perf_sdram_wait_lo \
@@ -206,28 +206,28 @@
#define RS_SOC_PERF_CTRL_CLEAR UINT32_C(0x00000002)
#define RS_SOC_PERF_CTRL_SNAPSHOT UINT32_C(0x00000004)
// clint
#define reg_clint_mtimel RS_SOC_REG32(RS_SOC_RIB_CLINT_BASE, UINT32_C(0x00))
#define reg_clint_mtimeh RS_SOC_REG32(RS_SOC_RIB_CLINT_BASE, UINT32_C(0x04))
#define reg_clint_mtimecmpl RS_SOC_REG32(RS_SOC_RIB_CLINT_BASE, UINT32_C(0x08))
#define reg_clint_mtimecmph RS_SOC_REG32(RS_SOC_RIB_CLINT_BASE, UINT32_C(0x0C))
#define reg_clint_msip RS_SOC_REG32(RS_SOC_RIB_CLINT_BASE, UINT32_C(0x10))
#define reg_clint_clkdiv RS_SOC_REG32(RS_SOC_RIB_CLINT_BASE, UINT32_C(0x14))
#define reg_clint_mtimel RS_SOC_REG32(RS_SOC_RIBP_CLINT_BASE, UINT32_C(0x00))
#define reg_clint_mtimeh RS_SOC_REG32(RS_SOC_RIBP_CLINT_BASE, UINT32_C(0x04))
#define reg_clint_mtimecmpl RS_SOC_REG32(RS_SOC_RIBP_CLINT_BASE, UINT32_C(0x08))
#define reg_clint_mtimecmph RS_SOC_REG32(RS_SOC_RIBP_CLINT_BASE, UINT32_C(0x0C))
#define reg_clint_msip RS_SOC_REG32(RS_SOC_RIBP_CLINT_BASE, UINT32_C(0x10))
#define reg_clint_clkdiv RS_SOC_REG32(RS_SOC_RIBP_CLINT_BASE, UINT32_C(0x14))
// sdram
#define reg_sdram_clkdiv RS_SOC_REG32(RS_SOC_RIB_SDRAM_BASE, UINT32_C(0x00))
#define reg_sdram_cfg RS_SOC_REG32(RS_SOC_RIB_SDRAM_BASE, UINT32_C(0x04))
#define reg_sdram_clkdiv RS_SOC_REG32(RS_SOC_RIBP_SDRAM_BASE, UINT32_C(0x00))
#define reg_sdram_cfg RS_SOC_REG32(RS_SOC_RIBP_SDRAM_BASE, UINT32_C(0x04))
// dvp
#define reg_dvp_recven RS_SOC_REG32(RS_SOC_RIB_DVP_BASE, UINT32_C(0x00))
#define reg_dvp_rxdata RS_SOC_REG32(RS_SOC_RIB_DVP_BASE, UINT32_C(0x04))
#define reg_dvp_status RS_SOC_REG32(RS_SOC_RIB_DVP_BASE, UINT32_C(0x08))
#define reg_dvp_recven RS_SOC_REG32(RS_SOC_RIBP_DVP_BASE, UINT32_C(0x00))
#define reg_dvp_rxdata RS_SOC_REG32(RS_SOC_RIBP_DVP_BASE, UINT32_C(0x04))
#define reg_dvp_status RS_SOC_REG32(RS_SOC_RIBP_DVP_BASE, UINT32_C(0x08))
// i2c1
#define reg_i2c1_clkdiv RS_SOC_REG32(RS_SOC_RIB_I2C1_BASE, UINT32_C(0x00))
#define reg_i2c1_devaddr RS_SOC_REG32(RS_SOC_RIB_I2C1_BASE, UINT32_C(0x04))
#define reg_i2c1_regaddr RS_SOC_REG32(RS_SOC_RIB_I2C1_BASE, UINT32_C(0x08))
#define reg_i2c1_txdata RS_SOC_REG32(RS_SOC_RIB_I2C1_BASE, UINT32_C(0x0C))
#define reg_i2c1_rxdata RS_SOC_REG32(RS_SOC_RIB_I2C1_BASE, UINT32_C(0x10))
#define reg_i2c1_xfer RS_SOC_REG32(RS_SOC_RIB_I2C1_BASE, UINT32_C(0x14))
#define reg_i2c1_cfg RS_SOC_REG32(RS_SOC_RIB_I2C1_BASE, UINT32_C(0x18))
#define reg_i2c1_status RS_SOC_REG32(RS_SOC_RIB_I2C1_BASE, UINT32_C(0x1C))
#define reg_i2c1_clkdiv RS_SOC_REG32(RS_SOC_RIBP_I2C1_BASE, UINT32_C(0x00))
#define reg_i2c1_devaddr RS_SOC_REG32(RS_SOC_RIBP_I2C1_BASE, UINT32_C(0x04))
#define reg_i2c1_regaddr RS_SOC_REG32(RS_SOC_RIBP_I2C1_BASE, UINT32_C(0x08))
#define reg_i2c1_txdata RS_SOC_REG32(RS_SOC_RIBP_I2C1_BASE, UINT32_C(0x0C))
#define reg_i2c1_rxdata RS_SOC_REG32(RS_SOC_RIBP_I2C1_BASE, UINT32_C(0x10))
#define reg_i2c1_xfer RS_SOC_REG32(RS_SOC_RIBP_I2C1_BASE, UINT32_C(0x14))
#define reg_i2c1_cfg RS_SOC_REG32(RS_SOC_RIBP_I2C1_BASE, UINT32_C(0x18))
#define reg_i2c1_status RS_SOC_REG32(RS_SOC_RIBP_I2C1_BASE, UINT32_C(0x1C))
// archinfo
#define reg_archinfo_sys RS_SOC_REG32(RS_SOC_APB_ARCHINFO_BASE, UINT32_C(0x00))
#define reg_archinfo_idl RS_SOC_REG32(RS_SOC_APB_ARCHINFO_BASE, UINT32_C(0x04))
crt/include/retrosoc/hal/perf.h
+1 -1
View File
@@ -9,7 +9,7 @@ typedef struct {
uint64_t mgmt_wait;
uint64_t user_wait;
uint64_t dma_wait;
uint64_t rib_wait;
uint64_t ribp_wait;
uint64_t apb_wait;
uint64_t sdram_wait;
uint64_t psram_wait;
crt/src/hal/perf.c
+2 -2
View File
@@ -30,8 +30,8 @@ rs_status_t rs_perf_snapshot(rs_perf_snapshot_t *snapshot) {
rs_perf_read_counter(&reg_sysctrl_perf_user_wait_lo, &reg_sysctrl_perf_user_wait_hi);
snapshot->dma_wait =
rs_perf_read_counter(&reg_sysctrl_perf_dma_wait_lo, &reg_sysctrl_perf_dma_wait_hi);
snapshot->rib_wait =
rs_perf_read_counter(&reg_sysctrl_perf_rib_wait_lo, &reg_sysctrl_perf_rib_wait_hi);
snapshot->ribp_wait =
rs_perf_read_counter(&reg_sysctrl_perf_ribp_wait_lo, &reg_sysctrl_perf_ribp_wait_hi);
snapshot->apb_wait =
rs_perf_read_counter(&reg_sysctrl_perf_apb_wait_lo, &reg_sysctrl_perf_apb_wait_hi);
snapshot->sdram_wait =
docs/engineering.md
+1 -1
View File
@@ -111,7 +111,7 @@ Verilator regressions.
`make CONFIG=configs/ci/ihp130.mk formal` proves selected
protocol invariants with SymbiYosys, Yosys, `sv2v`, and Bitwuzla. The current
targets are `bus`, `rib_adapter`, `spill_register`, `rib2apb`, `sysctrl`,
targets are `bus`, `rib_adapter`, `spill_register`, `ribp2apb`, `sysctrl`,
`pll_rcu`, and `gpio_user`; each uses
the SBY `prove` task for bounded model checking and k-induction, plus a
`cover` task, at depth 20. `sysctrl` checks register side effects, PLL request
rtl/ip/experimental/axi4f2rib.sv → rtl/ip/experimental/axi4f2ribp.sv
+2 -2
View File
@@ -8,7 +8,7 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
module axi4f2rib (
module axi4f2ribp (
// verilog_format: off
input logic aclk_i,
input logic aresetn_i,
@@ -29,7 +29,7 @@ module axi4f2rib (
output logic [ 1:0] rresp_o,
output logic rvalid_o,
input logic rready_i,
rib_if.master rib
ribp_if.master ribp
// verilog_format: on
);
rtl/ip/experimental/gpu.sv
+1 -1
View File
@@ -8,5 +8,5 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
module rib_gpu ();
module ribp_gpu ();
endmodule
rtl/ip/experimental/wb2rib.sv → rtl/ip/experimental/wb2ribp.sv
+1 -1
View File
@@ -10,5 +10,5 @@
`include "mmap_define.svh"
module wb2rib ();
module wb2ribp ();
endmodule
rtl/ip/rib/interconnect/rib_regslice.sv
-136
View File
@@ -1,136 +0,0 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
module rib_regslice (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib_slv,
rib_if.master rib_mst
// verilog_format: on
);
localparam FSM_IDLE = 2'd0;
localparam FSM_REQ = 2'd1;
localparam FSM_RESP = 2'd2;
logic [1:0] s_fsm_d, s_fsm_q;
logic s_rib_mst_valid_d, s_rib_mst_valid_q;
logic [31:0] s_rib_mst_addr_d, s_rib_mst_addr_q;
logic [31:0] s_rib_mst_wdata_d, s_rib_mst_wdata_q;
logic [3:0] s_rib_mst_wstrb_d, s_rib_mst_wstrb_q;
logic [31:0] s_rib_mst_rdata_d, s_rib_mst_rdata_q;
logic s_rib_mst_ready_d, s_rib_mst_ready_q;
// rib mst if
assign rib_mst.valid = s_rib_mst_valid_q;
assign rib_mst.addr = s_rib_mst_addr_q;
assign rib_mst.wdata = s_rib_mst_wdata_q;
assign rib_mst.wstrb = s_rib_mst_wstrb_q;
always_comb begin
s_fsm_d = s_fsm_q;
s_rib_mst_valid_d = s_rib_mst_valid_q;
s_rib_mst_addr_d = s_rib_mst_addr_q;
s_rib_mst_wdata_d = s_rib_mst_wdata_q;
s_rib_mst_wstrb_d = s_rib_mst_wstrb_q;
s_rib_mst_ready_d = s_rib_mst_ready_q;
s_rib_mst_rdata_d = s_rib_mst_rdata_q;
rib_slv.ready = '0;
rib_slv.rdata = '0;
unique case (s_fsm_q)
FSM_IDLE: begin
if (rib_slv.valid) begin
s_fsm_d = FSM_REQ;
s_rib_mst_valid_d = rib_slv.valid;
s_rib_mst_addr_d = rib_slv.addr;
s_rib_mst_wdata_d = rib_slv.wdata;
s_rib_mst_wstrb_d = rib_slv.wstrb;
end
end
FSM_REQ: begin
if (rib_mst.ready) begin
s_fsm_d = FSM_RESP;
s_rib_mst_valid_d = 1'b0;
s_rib_mst_ready_d = rib_mst.ready;
s_rib_mst_rdata_d = rib_mst.rdata;
end
end
FSM_RESP: begin
s_fsm_d = FSM_IDLE;
rib_slv.ready = s_rib_mst_ready_q;
rib_slv.rdata = s_rib_mst_rdata_q;
end
default: begin
s_fsm_d = s_fsm_q;
s_rib_mst_valid_d = s_rib_mst_valid_q;
s_rib_mst_addr_d = s_rib_mst_addr_q;
s_rib_mst_wdata_d = s_rib_mst_wdata_q;
s_rib_mst_wstrb_d = s_rib_mst_wstrb_q;
s_rib_mst_ready_d = s_rib_mst_ready_q;
s_rib_mst_rdata_d = s_rib_mst_rdata_q;
rib_slv.ready = '0;
rib_slv.rdata = '0;
end
endcase
end
dffr #(2) u_fsm_dffr (
clk_i,
rst_n_i,
s_fsm_d,
s_fsm_q
);
dffr #(1) u_rib_mstr_valid_dffr (
clk_i,
rst_n_i,
s_rib_mst_valid_d,
s_rib_mst_valid_q
);
dffr #(32) u_rib_mst_addr_dffr (
clk_i,
rst_n_i,
s_rib_mst_addr_d,
s_rib_mst_addr_q
);
dffr #(32) u_rib_mst_wdata_dffr (
clk_i,
rst_n_i,
s_rib_mst_wdata_d,
s_rib_mst_wdata_q
);
dffr #(4) u_rib_mst_wstrb_dffr (
clk_i,
rst_n_i,
s_rib_mst_wstrb_d,
s_rib_mst_wstrb_q
);
dffr #(32) u_rib_mst_rdata_dffr (
clk_i,
rst_n_i,
s_rib_mst_rdata_d,
s_rib_mst_rdata_q
);
dffr #(1) u_rib_mst_ready_dffr (
clk_i,
rst_n_i,
s_rib_mst_ready_d,
s_rib_mst_ready_q
);
endmodule
rtl/ip/rib/memory/sdram_reg.sv
-84
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@@ -1,84 +0,0 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIB_SDRAM_DEF_SV
`define RIB_SDRAM_DEF_SV
// verilog_format: off
`define RIB_SDRAM_CLKDIV 8'h00
`define RIB_SDRAM_CFG 8'h04
// verilog_format: on
`endif
module sdram_reg (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib,
output logic [1:0] clkdiv_o
// verilog_format: on
);
// rib
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
// register
logic s_sdram_clkdiv_en;
logic [1:0] s_sdram_clkdiv_d, s_sdram_clkdiv_q;
// rib
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
// reg
assign clkdiv_o = s_sdram_clkdiv_q;
assign s_sdram_clkdiv_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_SDRAM_CLKDIV;
assign s_sdram_clkdiv_d = rib.wdata[1:0];
dffer #(2) u_sdram_clkdiv_dffer (
clk_i,
rst_n_i,
s_sdram_clkdiv_en,
s_sdram_clkdiv_d,
s_sdram_clkdiv_q
);
// rib resp
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
clk_i,
rst_n_i,
s_rib_ready_d,
s_rib_ready_q
);
assign s_rib_rdata_en = s_rib_rd_hdshk;
always_comb begin
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_SDRAM_CLKDIV: s_rib_rdata_d = {30'd0, s_sdram_clkdiv_q};
default: s_rib_rdata_d = s_rib_rdata_q;
endcase
end
dffer #(32) u_rib_rdata_dffer (
clk_i,
rst_n_i,
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
);
endmodule
rtl/ip/rib/peripheral/clint.sv
-180
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@@ -1,180 +0,0 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef CLINT_DEF_SV
`define CLINT_DEF_SV
// verilog_format: off
`define RIB_CLINT_MTIMEL 8'h00
`define RIB_CLINT_MTIMEH 8'h04
`define RIB_CLINT_MTIMECMPL 8'h08
`define RIB_CLINT_MTIMECMPH 8'h0C
`define RIB_CLINT_MSIP 8'h10
`define RIB_CLINT_CLKDIV 8'h14
// verilog_format: on
`endif
interface simp_clint_if ();
logic tmr_irq_o;
logic sfr_irq_o;
modport dut(output tmr_irq_o, output sfr_irq_o);
endinterface
module rib_clint (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib,
simp_clint_if.dut clint
// verilog_format: on
);
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
logic s_clint_clkdiv_en;
logic [7:0] s_clint_clkdiv_d, s_clint_clkdiv_q;
logic s_clint_mtime_en;
logic [63:0] s_clint_mtime_d, s_clint_mtime_q;
logic s_clint_mtimecmp_en;
logic [63:0] s_clint_mtimecmp_d, s_clint_mtimecmp_q;
logic s_clint_msip_en;
logic s_clint_msip_d, s_clint_msip_q;
// utils
logic [7:0] s_clk_cnt_d, s_clk_cnt_q;
// pipelined 64-bit compare: split into hi32 and lo32 stages
logic s_tmr_hi_gt, s_tmr_hi_eq, s_tmr_lo_ge;
logic s_tmr_irq_d, s_tmr_irq_q;
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
// pipelined 64-bit magnitude compare (registered output)
assign s_tmr_hi_gt = s_clint_mtime_q[63:32] > s_clint_mtimecmp_q[63:32];
assign s_tmr_hi_eq = s_clint_mtime_q[63:32] == s_clint_mtimecmp_q[63:32];
assign s_tmr_lo_ge = s_clint_mtime_q[31:0] >= s_clint_mtimecmp_q[31:0];
assign s_tmr_irq_d = s_tmr_hi_gt || (s_tmr_hi_eq && s_tmr_lo_ge);
dffr #(1) u_tmr_irq_dffr (
clk_i,
rst_n_i,
s_tmr_irq_d,
s_tmr_irq_q
);
assign clint.tmr_irq_o = s_tmr_irq_q;
assign clint.sfr_irq_o = s_clint_msip_q;
assign s_clint_clkdiv_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_CLINT_CLKDIV;
assign s_clint_clkdiv_d = rib.wdata[7:0];
dffer #(8) u_clint_clkdiv_dffer (
clk_i,
rst_n_i,
s_clint_clkdiv_en,
s_clint_clkdiv_d,
s_clint_clkdiv_q
);
always_comb begin
s_clk_cnt_d = s_clk_cnt_q;
if (s_clk_cnt_q == s_clint_clkdiv_q) begin
s_clk_cnt_d = '0;
end else begin
s_clk_cnt_d = s_clk_cnt_q + 1'b1;
end
end
dffr #(8) u_clk_cnt_dffr (
clk_i,
rst_n_i,
s_clk_cnt_d,
s_clk_cnt_q
);
assign s_clint_mtime_en = s_clk_cnt_q == s_clint_clkdiv_q;
assign s_clint_mtime_d = s_clint_mtime_q + 1'b1;
dffer #(64) u_clint_mtime_dffer (
clk_i,
rst_n_i,
s_clint_mtime_en,
s_clint_mtime_d,
s_clint_mtime_q
);
assign s_clint_mtimecmp_en = s_rib_wr_hdshk && (rib.addr[7:0] == `RIB_CLINT_MTIMECMPL || rib.addr[7:0] == `RIB_CLINT_MTIMECMPH);
always_comb begin
s_clint_mtimecmp_d = s_clint_mtimecmp_q;
if (rib.addr[7:0] == `RIB_CLINT_MTIMECMPL) begin
if (rib.wstrb[0]) s_clint_mtimecmp_d[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_clint_mtimecmp_d[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_clint_mtimecmp_d[23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_clint_mtimecmp_d[31:24] = rib.wdata[31:24];
end else if (rib.addr[7:0] == `RIB_CLINT_MTIMECMPH) begin
if (rib.wstrb[0]) s_clint_mtimecmp_d[39:32] = rib.wdata[7:0];
if (rib.wstrb[1]) s_clint_mtimecmp_d[47:40] = rib.wdata[15:8];
if (rib.wstrb[2]) s_clint_mtimecmp_d[55:48] = rib.wdata[23:16];
if (rib.wstrb[3]) s_clint_mtimecmp_d[63:56] = rib.wdata[31:24];
end
end
dfferh #(64) u_clint_mtimecmp_dfferh (
clk_i,
rst_n_i,
s_clint_mtimecmp_en,
s_clint_mtimecmp_d,
s_clint_mtimecmp_q
);
assign s_clint_msip_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_CLINT_MSIP;
assign s_clint_msip_d = rib.wdata[0];
dffer #(1) u_clint_msip_dffer (
clk_i,
rst_n_i,
s_clint_msip_en,
s_clint_msip_d,
s_clint_msip_q
);
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
clk_i,
rst_n_i,
s_rib_ready_d,
s_rib_ready_q
);
assign s_rib_rdata_en = s_rib_rd_hdshk;
always_comb begin
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_CLINT_CLKDIV: s_rib_rdata_d = {24'd0, s_clint_clkdiv_q};
`RIB_CLINT_MTIMEL: s_rib_rdata_d = s_clint_mtime_q[31:0];
`RIB_CLINT_MTIMEH: s_rib_rdata_d = s_clint_mtime_q[63:32];
`RIB_CLINT_MTIMECMPL: s_rib_rdata_d = s_clint_mtimecmp_q[31:0];
`RIB_CLINT_MTIMECMPH: s_rib_rdata_d = s_clint_mtimecmp_q[63:32];
`RIB_CLINT_MSIP: s_rib_rdata_d = {31'd0, s_clint_msip_q};
default: s_rib_rdata_d = s_rib_rdata_q;
endcase
end
dffer #(32) u_rib_rdata_dffer (
clk_i,
rst_n_i,
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
);
endmodule
rtl/ip/rib/peripheral/gpio_define.svh
-32
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@@ -1,32 +0,0 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIB_GPIO_DEF_SV
`define RIB_GPIO_DEF_SV
// verilog_format: off
`define RIB_GPIO_NUM 32
`define RIB_GPIO_OE 8'h00 // rw
`define RIB_GPIO_CS 8'h04 // rw
`define RIB_GPIO_PU 8'h08 // rw
`define RIB_GPIO_PD 8'h0C // rw
`define RIB_GPIO_DO 8'h10 // rw
`define RIB_GPIO_DI 8'h14 // ro
`define RIB_GPIO_IEN 8'h18 // rw
`define RIB_GPIO_ITYPE0 8'h1c // rw
`define RIB_GPIO_ITYPE1 8'h20 // rw
`define RIB_GPIO_ISTAT 8'h24 // ro
`define RIB_GPIO_IOFCFG 8'h28 // rw
`define RIB_GPIO_PINMUX 8'h2c // rw
`define RIB_GPIO_USER_SEL 8'h30 // rw
`define RIB_GPIO_USER_LOCK 8'h34 // rw1s
`define RIB_GPIO_USER_STATUS 8'h38 // ro
// verilog_format: on
`endif
rtl/ip/rib/storage/spisd_reg.sv
-157
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@@ -1,157 +0,0 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIB_SPISD_DEF_SV
`define RIB_SPISD_DEF_SV
// verilog_format: off
`define RIB_SPISD_MODE 8'h00
`define RIB_SPISD_CLKDIV 8'h04
`define RIB_SPISD_ADDR 8'h08
`define RIB_SPISD_TXDATA 8'h0C
`define RIB_SPISD_RXDATA 8'h10
`define RIB_SPISD_STATUS 8'h14
`define RIB_SPISD_SYNC 8'h18
// verilog_format: on
`endif
module spisd_reg (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
input logic init_done_i,
output logic wr_sync_o,
input logic wr_sync_done_i,
output logic mode_o,
output logic [1:0] clkdiv_o,
rib_if.slave rib,
rib_if.master byp_rib
// verilog_format: on
);
// rib
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
// reg
logic s_spisd_mode_en;
logic s_spisd_mode_d, s_spisd_mode_q;
logic s_spisd_clkdiv_en;
logic [1:0] s_spisd_clkdiv_d, s_spisd_clkdiv_q;
logic s_spisd_addr_en;
logic [31:0] s_spisd_addr_d, s_spisd_addr_q;
logic [1:0] s_spisd_status_d, s_spisd_status_q;
// common
logic s_wr_byp, s_rd_byp;
// rib
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign s_wr_byp = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_SPISD_TXDATA;
assign s_rd_byp = s_rib_rd_hdshk && rib.addr[7:0] == `RIB_SPISD_RXDATA;
assign rib.ready = (s_wr_byp || s_rd_byp) ? byp_rib.ready : s_rib_ready_q;
assign rib.rdata = (s_wr_byp || s_rd_byp) ? byp_rib.rdata : s_rib_rdata_q;
// common
assign mode_o = s_spisd_mode_q;
assign clkdiv_o = s_spisd_clkdiv_q;
// byp
assign byp_rib.valid = s_wr_byp || s_rd_byp;
assign byp_rib.addr = s_spisd_addr_q;
assign byp_rib.wdata = rib.wdata;
assign byp_rib.wstrb = rib.wstrb;
assign s_spisd_mode_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_SPISD_MODE;
assign s_spisd_mode_d = rib.wdata[0];
dffer #(1) u_spisd_mode_dffer (
clk_i,
rst_n_i,
s_spisd_mode_en,
s_spisd_mode_d,
s_spisd_mode_q
);
assign s_spisd_clkdiv_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_SPISD_CLKDIV;
assign s_spisd_clkdiv_d = rib.wdata[1:0];
dffer #(2) u_spisd_clkdiv_dffer (
clk_i,
rst_n_i,
s_spisd_clkdiv_en,
s_spisd_clkdiv_d,
s_spisd_clkdiv_q
);
assign s_spisd_addr_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_SPISD_ADDR;
always_comb begin
s_spisd_addr_d = s_spisd_addr_q;
if (rib.wstrb[0]) s_spisd_addr_d[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_spisd_addr_d[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_spisd_addr_d[23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_spisd_addr_d[31:24] = rib.wdata[31:24];
end
dffer #(32) u_spisd_addr_dffer (
clk_i,
rst_n_i,
s_spisd_addr_en,
s_spisd_addr_d,
s_spisd_addr_q
);
// 0: init done
// 1: wr sync done
always_comb begin
s_spisd_status_d = s_spisd_status_q;
s_spisd_status_d[0] = init_done_i;
if (wr_sync_done_i && ~s_spisd_status_q[1]) begin
s_spisd_status_d[1] = 1'b1;
end else if (s_spisd_status_q[1] && s_rib_rd_hdshk && rib.addr[7:0] == `RIB_SPISD_STATUS) begin
s_spisd_status_d[1] = 1'b0;
end
end
dffr #(2) u_spisd_status_dffr (
clk_i,
rst_n_i,
s_spisd_status_d,
s_spisd_status_q
);
// software wr sync
assign wr_sync_o = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_SPISD_SYNC;
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
clk_i,
rst_n_i,
s_rib_ready_d,
s_rib_ready_q
);
assign s_rib_rdata_en = s_rib_rd_hdshk;
always_comb begin
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_SPISD_MODE: s_rib_rdata_d = {31'd0, s_spisd_mode_q};
`RIB_SPISD_CLKDIV: s_rib_rdata_d = {30'd0, s_spisd_clkdiv_q};
`RIB_SPISD_ADDR: s_rib_rdata_d = s_spisd_addr_q;
`RIB_SPISD_STATUS: s_rib_rdata_d = {30'd0, s_spisd_status_q};
default: s_rib_rdata_d = s_rib_rdata_q;
endcase
end
dffer #(32) u_rib_rdata_dffer (
clk_i,
rst_n_i,
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
);
endmodule
rtl/ip/rib/storage/xpi_define.svh
-58
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@@ -1,58 +0,0 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIB_XPI_DEF_SV
`define RIB_XPI_DEF_SV
// verilog_format: off
`define RIB_XPI_CFGIDX 8'h00
`define RIB_XPI_ACCMD 8'h04
`define RIB_XPI_MMSTAD 8'h08
`define RIB_XPI_MMOFFST 8'h0C
`define RIB_XPI_MODE 8'h10
`define RIB_XPI_NSS 8'h14
`define RIB_XPI_CLKDIV 8'h18
`define RIB_XPI_RDWR 8'h1C
`define RIB_XPI_REVDAT 8'h20
`define RIB_XPI_TXUPB 8'h24
`define RIB_XPI_TXLOWB 8'h28
`define RIB_XPI_RXUPB 8'h2C
`define RIB_XPI_RXLOWB 8'h30
`define RIB_XPI_FLUSH 8'h34
`define RIB_XPI_CMDTYP 8'h38
`define RIB_XPI_CMDLEN 8'h3C
`define RIB_XPI_CMDDAT 8'h40
`define RIB_XPI_ADRTYP 8'h44
`define RIB_XPI_ADRLEN 8'h48
`define RIB_XPI_ADRDAT 8'h4C
`define RIB_XPI_ALTTYP 8'h50
`define RIB_XPI_ALTLEN 8'h54
`define RIB_XPI_ALTDAT 8'h58
`define RIB_XPI_TDULEN 8'h5C
`define RIB_XPI_RDULEN 8'h60
`define RIB_XPI_DATTYP 8'h64
`define RIB_XPI_DATLEN 8'h68
`define RIB_XPI_DATBIT 8'h6C
`define RIB_XPI_HLVLEN 8'h70
`define RIB_XPI_TXDATA 8'h74
`define RIB_XPI_RXDATA 8'h78
`define RIB_XPI_XST 8'h7C
`define RIB_XPI_STATUS 8'h80
`define XPI_TYPE_NONE 2'd0
`define XPI_TYPE_SNGL 2'd1
`define XPI_TYPE_DUAL 2'd2
`define XPI_TYPE_QUAD 2'd3
`define XPI_NSS_NUM 4
`define XPI_LNS_NUM $clog2(`XPI_NSS_NUM)
// verilog_format: on
`endif
rtl/ip/rib/interconnect/ahbl2rib.sv → rtl/ip/ribp/interconnect/ahbl2ribp.sv
+31 -31
View File
@@ -9,9 +9,9 @@
// See the Mulan PSL v2 for more details.
module ahbl2rib (
ahbl_if.slave ahbl,
rib_if.master rib
module ahbl2ribp (
ahbl_if.slave ahbl,
ribp_if.master ribp
);
localparam AHBL_TRANS_IDLE = 2'b00;
@@ -39,61 +39,61 @@ module ahbl2rib (
// ahbl if
// NOTE: need to gurantee `ahbl.hready` and `ahbl.hrdata` sampled in same cycle
assign ahbl.hready = (s_fsm_q == STATE_IDLE) || rib.ready;
assign ahbl.hready = (s_fsm_q == STATE_IDLE) || ribp.ready;
assign ahbl.hresp = AHBL_RESP_OKAY;
assign ahbl.hrdata = rib.rdata;
assign ahbl.hrdata = ribp.rdata;
// rib if
assign rib.valid = s_fsm_q != STATE_IDLE;
assign rib.addr = {s_haddr_q[31:2], 2'b00};
// ribp if
assign ribp.valid = s_fsm_q != STATE_IDLE;
assign ribp.addr = {s_haddr_q[31:2], 2'b00};
always_comb begin
rib.wstrb = '0;
rib.wdata = '0;
ribp.wstrb = '0;
ribp.wdata = '0;
if (s_hwrite_q) begin
unique case (s_hsize_q)
AHBL_SIZE_BYTE: begin
unique case (s_haddr_q[1:0])
2'b00: begin
rib.wstrb = 4'b0001;
rib.wdata = {24'b0, ahbl.hwdata[7:0]};
ribp.wstrb = 4'b0001;
ribp.wdata = {24'b0, ahbl.hwdata[7:0]};
end
2'b01: begin
rib.wstrb = 4'b0010;
rib.wdata = {16'b0, ahbl.hwdata[7:0], 8'b0};
ribp.wstrb = 4'b0010;
ribp.wdata = {16'b0, ahbl.hwdata[7:0], 8'b0};
end
2'b10: begin
rib.wstrb = 4'b0100;
rib.wdata = {8'b0, ahbl.hwdata[7:0], 16'b0};
ribp.wstrb = 4'b0100;
ribp.wdata = {8'b0, ahbl.hwdata[7:0], 16'b0};
end
2'b11: begin
rib.wstrb = 4'b1000;
rib.wdata = {ahbl.hwdata[7:0], 24'b0};
ribp.wstrb = 4'b1000;
ribp.wdata = {ahbl.hwdata[7:0], 24'b0};
end
default: begin
rib.wstrb = 4'b0001;
rib.wdata = {24'b0, ahbl.hwdata[7:0]};
ribp.wstrb = 4'b0001;
ribp.wdata = {24'b0, ahbl.hwdata[7:0]};
end
endcase
end
AHBL_SIZE_HWRD: begin
unique case (s_haddr_q[1])
1'b0: begin
rib.wstrb = 4'b0011;
rib.wdata = {16'b0, ahbl.hwdata[15:0]};
ribp.wstrb = 4'b0011;
ribp.wdata = {16'b0, ahbl.hwdata[15:0]};
end
1'b1: begin
rib.wstrb = 4'b1100;
rib.wdata = {ahbl.hwdata[15:0], 16'd0};
ribp.wstrb = 4'b1100;
ribp.wdata = {ahbl.hwdata[15:0], 16'd0};
end
endcase
end
AHBL_SIZE_WORD: begin
rib.wstrb = 4'b1111;
rib.wdata = ahbl.hwdata;
ribp.wstrb = 4'b1111;
ribp.wdata = ahbl.hwdata;
end
default: begin
rib.wstrb = 4'b1111;
rib.wdata = ahbl.hwdata;
ribp.wstrb = 4'b1111;
ribp.wdata = ahbl.hwdata;
end
endcase
end
@@ -117,8 +117,8 @@ module ahbl2rib (
end
end
STATE_DATA: begin
if (~rib.ready) s_fsm_d = STATE_WAIT;
// rib.ready == 1'b1
if (~ribp.ready) s_fsm_d = STATE_WAIT;
// ribp.ready == 1'b1
else if (ahbl.htrans == AHBL_TRANS_NSEQ) begin
s_fsm_d = STATE_DATA;
s_haddr_d = ahbl.haddr;
@@ -127,7 +127,7 @@ module ahbl2rib (
end else s_fsm_d = STATE_IDLE;
end
STATE_WAIT: begin
if (rib.ready) begin
if (ribp.ready) begin
if (ahbl.htrans == AHBL_TRANS_NSEQ) begin
s_fsm_d = STATE_DATA;
s_haddr_d = ahbl.haddr;
rtl/ip/rib/interconnect/axi4l2rib.sv → rtl/ip/ribp/interconnect/axi4l2ribp.sv
+24 -24
View File
@@ -8,7 +8,7 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
module axi4l2rib (
module axi4l2ribp (
// verilog_format: off
input logic aclk_i,
input logic aresetn_i,
@@ -29,7 +29,7 @@ module axi4l2rib (
output logic [ 1:0] rresp_o,
output logic rvalid_o,
input logic rready_i,
rib_if.master rib
ribp_if.master ribp
// verilog_format: on
);
@@ -58,7 +58,7 @@ module axi4l2rib (
if (arvalid_i) s_rd_fsm_d = RD_DATA;
end
RD_DATA: begin
if (rib.ready) s_rd_fsm_d = RD_WAIT;
if (ribp.ready) s_rd_fsm_d = RD_WAIT;
end
RD_WAIT: begin
if (rready_i) s_rd_fsm_d = RD_IDLE;
@@ -83,7 +83,7 @@ module axi4l2rib (
if (wvalid_i) s_wr_fsm_d = WR_WAIT;
end
WR_WAIT: begin
if (rib.ready) s_wr_fsm_d = WR_RESP;
if (ribp.ready) s_wr_fsm_d = WR_RESP;
end
WR_RESP: begin
if (bready_i) s_wr_fsm_d = WR_IDLE;
@@ -99,13 +99,13 @@ module axi4l2rib (
);
always_comb begin
rib.addr = s_addr_q;
ribp.addr = s_addr_q;
if (s_rd_fsm_q == RD_IDLE && arvalid_i) begin
rib.addr = araddr_i;
s_addr_d = araddr_i;
ribp.addr = araddr_i;
s_addr_d = araddr_i;
end else if (s_wr_fsm_q == WR_IDLE && awvalid_i) begin
rib.addr = awaddr_i;
s_addr_d = awaddr_i;
ribp.addr = awaddr_i;
s_addr_d = awaddr_i;
end
end
dffer #(32) u_addr_dffer (
@@ -116,11 +116,11 @@ module axi4l2rib (
s_addr_q
);
assign s_rdata_d = rib.rdata;
assign s_rdata_d = ribp.rdata;
dffer #(32) u_rdata_dffer (
aclk_i,
aresetn_i,
s_rd_fsm_q == RD_DATA && rib.ready,
s_rd_fsm_q == RD_DATA && ribp.ready,
s_rdata_d,
s_rdata_q
);
@@ -144,19 +144,19 @@ module axi4l2rib (
);
// axil
assign arready_o = s_rd_fsm_q == RD_IDLE && arvalid_i;
assign rvalid_o = s_rd_fsm_q == RD_WAIT;
assign rresp_o = '0;
assign rdata_o = s_rdata_q;
assign arready_o = s_rd_fsm_q == RD_IDLE && arvalid_i;
assign rvalid_o = s_rd_fsm_q == RD_WAIT;
assign rresp_o = '0;
assign rdata_o = s_rdata_q;
assign awready_o = s_wr_fsm_q == WR_IDLE && awvalid_i;
assign wready_o = s_wr_fsm_q == WR_DATA && wvalid_i;
assign bvalid_o = s_wr_fsm_q == WR_RESP;
assign bresp_o = '0;
assign awready_o = s_wr_fsm_q == WR_IDLE && awvalid_i;
assign wready_o = s_wr_fsm_q == WR_DATA && wvalid_i;
assign bvalid_o = s_wr_fsm_q == WR_RESP;
assign bresp_o = '0;
assign s_rd_req = (s_rd_fsm_q == RD_DATA || s_rd_fsm_q == RD_WAIT);
assign s_wr_req = s_wr_fsm_q == WR_WAIT;
assign rib.valid = s_rd_req || s_wr_req;
assign rib.wdata = s_wdata_q;
assign rib.wstrb = (s_wr_fsm_q == WR_WAIT) ? s_wstrb_q : '0;
assign s_rd_req = (s_rd_fsm_q == RD_DATA || s_rd_fsm_q == RD_WAIT);
assign s_wr_req = s_wr_fsm_q == WR_WAIT;
assign ribp.valid = s_rd_req || s_wr_req;
assign ribp.wdata = s_wdata_q;
assign ribp.wstrb = (s_wr_fsm_q == WR_WAIT) ? s_wstrb_q : '0;
endmodule
rtl/ip/rib/interconnect/rib2apb.sv → rtl/ip/ribp/interconnect/ribp2apb.sv
+6 -6
View File
@@ -10,11 +10,11 @@
`include "mmap_define.svh"
module rib2apb (
module ribp2apb (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib,
ribp_if.slave ribp,
output logic resp_err_o,
`include "soc_apb_ports.svh"
// verilog_format: on
@@ -40,7 +40,7 @@ module rib2apb (
edge_det_sync_re #(1) u_mem_valid_edge_det_sync_re (
clk_i,
rst_n_i,
rib.valid,
ribp.valid,
s_mem_valid_re
);
// verilog_format: on
@@ -64,9 +64,9 @@ module rib2apb (
s_fsm_q
);
assign rib.ready = rib.valid && (s_fsm_q == FSM_ENAB) && s_xfer_ready;
assign rib.rdata = {32{rib.ready}} & s_rd_data;
assign resp_err_o = rib.ready && s_xfer_error;
assign ribp.ready = ribp.valid && (s_fsm_q == FSM_ENAB) && s_xfer_ready;
assign ribp.rdata = {32{ribp.ready}} & s_rd_data;
assign resp_err_o = ribp.ready && s_xfer_error;
// Capture slave-select one-hot at FSM_SETP for cleaner response mux.
`include "soc_apb_select_routes.svh"
rtl/ip/rib/interconnect/rib2rib.sv → rtl/ip/ribp/interconnect/ribp2ribp.sv
+1 -1
View File
@@ -8,7 +8,7 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
module rib2rib (
module ribp2ribp (
// mstr
input logic mstr_clk_i,
input logic mstr_rst_n_i,
rtl/ip/ribp/interconnect/ribp_regslice.sv
+136
View File
@@ -0,0 +1,136 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
module ribp_regslice (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp_slv,
ribp_if.master ribp_mst
// verilog_format: on
);
localparam FSM_IDLE = 2'd0;
localparam FSM_REQ = 2'd1;
localparam FSM_RESP = 2'd2;
logic [1:0] s_fsm_d, s_fsm_q;
logic s_ribp_mst_valid_d, s_ribp_mst_valid_q;
logic [31:0] s_ribp_mst_addr_d, s_ribp_mst_addr_q;
logic [31:0] s_ribp_mst_wdata_d, s_ribp_mst_wdata_q;
logic [3:0] s_ribp_mst_wstrb_d, s_ribp_mst_wstrb_q;
logic [31:0] s_ribp_mst_rdata_d, s_ribp_mst_rdata_q;
logic s_ribp_mst_ready_d, s_ribp_mst_ready_q;
// ribp mst if
assign ribp_mst.valid = s_ribp_mst_valid_q;
assign ribp_mst.addr = s_ribp_mst_addr_q;
assign ribp_mst.wdata = s_ribp_mst_wdata_q;
assign ribp_mst.wstrb = s_ribp_mst_wstrb_q;
always_comb begin
s_fsm_d = s_fsm_q;
s_ribp_mst_valid_d = s_ribp_mst_valid_q;
s_ribp_mst_addr_d = s_ribp_mst_addr_q;
s_ribp_mst_wdata_d = s_ribp_mst_wdata_q;
s_ribp_mst_wstrb_d = s_ribp_mst_wstrb_q;
s_ribp_mst_ready_d = s_ribp_mst_ready_q;
s_ribp_mst_rdata_d = s_ribp_mst_rdata_q;
ribp_slv.ready = '0;
ribp_slv.rdata = '0;
unique case (s_fsm_q)
FSM_IDLE: begin
if (ribp_slv.valid) begin
s_fsm_d = FSM_REQ;
s_ribp_mst_valid_d = ribp_slv.valid;
s_ribp_mst_addr_d = ribp_slv.addr;
s_ribp_mst_wdata_d = ribp_slv.wdata;
s_ribp_mst_wstrb_d = ribp_slv.wstrb;
end
end
FSM_REQ: begin
if (ribp_mst.ready) begin
s_fsm_d = FSM_RESP;
s_ribp_mst_valid_d = 1'b0;
s_ribp_mst_ready_d = ribp_mst.ready;
s_ribp_mst_rdata_d = ribp_mst.rdata;
end
end
FSM_RESP: begin
s_fsm_d = FSM_IDLE;
ribp_slv.ready = s_ribp_mst_ready_q;
ribp_slv.rdata = s_ribp_mst_rdata_q;
end
default: begin
s_fsm_d = s_fsm_q;
s_ribp_mst_valid_d = s_ribp_mst_valid_q;
s_ribp_mst_addr_d = s_ribp_mst_addr_q;
s_ribp_mst_wdata_d = s_ribp_mst_wdata_q;
s_ribp_mst_wstrb_d = s_ribp_mst_wstrb_q;
s_ribp_mst_ready_d = s_ribp_mst_ready_q;
s_ribp_mst_rdata_d = s_ribp_mst_rdata_q;
ribp_slv.ready = '0;
ribp_slv.rdata = '0;
end
endcase
end
dffr #(2) u_fsm_dffr (
clk_i,
rst_n_i,
s_fsm_d,
s_fsm_q
);
dffr #(1) u_ribp_mstr_valid_dffr (
clk_i,
rst_n_i,
s_ribp_mst_valid_d,
s_ribp_mst_valid_q
);
dffr #(32) u_ribp_mst_addr_dffr (
clk_i,
rst_n_i,
s_ribp_mst_addr_d,
s_ribp_mst_addr_q
);
dffr #(32) u_ribp_mst_wdata_dffr (
clk_i,
rst_n_i,
s_ribp_mst_wdata_d,
s_ribp_mst_wdata_q
);
dffr #(4) u_ribp_mst_wstrb_dffr (
clk_i,
rst_n_i,
s_ribp_mst_wstrb_d,
s_ribp_mst_wstrb_q
);
dffr #(32) u_ribp_mst_rdata_dffr (
clk_i,
rst_n_i,
s_ribp_mst_rdata_d,
s_ribp_mst_rdata_q
);
dffr #(1) u_ribp_mst_ready_dffr (
clk_i,
rst_n_i,
s_ribp_mst_ready_d,
s_ribp_mst_ready_q
);
endmodule
rtl/ip/rib/memory/opipsram.sv → rtl/ip/ribp/memory/opipsram.sv
+5 -5
View File
@@ -32,11 +32,11 @@ interface opipsram_if ();
);
endinterface
module rib_opipsram (
module ribp_opipsram (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib,
ribp_if.slave ribp,
opipsram_if.dut psram
// verilog_format: on
);
@@ -44,9 +44,9 @@ module rib_opipsram (
wire dummy0 = clk_i;
wire dummy1 = rst_n_i;
// rib
assign rib.rdata = '0;
assign rib.ready = '0;
// ribp
assign ribp.rdata = '0;
assign ribp.ready = '0;
// psram
assign psram.sck_o = '0;
assign psram.ce_o = '0;
rtl/ip/rib/memory/opipsram_core.sv → rtl/ip/ribp/memory/opipsram_core.sv
View File
File renamed without changes.
rtl/ip/rib/memory/psram.sv → rtl/ip/ribp/memory/psram.sv
+36 -36
View File
@@ -36,13 +36,13 @@
// tSP(min: 2ns) is meet
// data keeps 6.94 / 2 = 3.47ns low at least befer sclk
`ifndef RIB_PSRAM_DEF_SV
`define RIB_PSRAM_DEF_SV
`ifndef RIBP_PSRAM_DEF_SV
`define RIBP_PSRAM_DEF_SV
// verilog_format: off
`define RIB_PSRAM_WAIT 8'h00
`define RIB_PSRAM_CHD 8'h04
`define RIB_PSRAM_INIT 8'h08
`define RIBP_PSRAM_WAIT 8'h00
`define RIBP_PSRAM_CHD 8'h04
`define RIBP_PSRAM_INIT 8'h08
// verilog_format: on
`endif
@@ -69,11 +69,11 @@ interface psram_if ();
endinterface
module rib_psram (
module ribp_psram (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib,
ribp_if.slave ribp,
psram_if.dut psram
// verilog_format: on
);
@@ -113,10 +113,10 @@ module rib_psram (
// verilog_format: off
assign psram.nss_o[0] = (~s_init_done) || (s_init_done && rib.addr[24:23] == 2'd0) ? s_psram_ce : 1'b1;
assign psram.nss_o[1] = (~s_init_done) || (s_init_done && rib.addr[24:23] == 2'd1) ? s_psram_ce : 1'b1;
assign psram.nss_o[2] = (~s_init_done) || (s_init_done && rib.addr[24:23] == 2'd2) ? s_psram_ce : 1'b1;
assign psram.nss_o[3] = (~s_init_done) || (s_init_done && rib.addr[24:23] == 2'd3) ? s_psram_ce : 1'b1;
assign psram.nss_o[0] = (~s_init_done) || (s_init_done && ribp.addr[24:23] == 2'd0) ? s_psram_ce : 1'b1;
assign psram.nss_o[1] = (~s_init_done) || (s_init_done && ribp.addr[24:23] == 2'd1) ? s_psram_ce : 1'b1;
assign psram.nss_o[2] = (~s_init_done) || (s_init_done && ribp.addr[24:23] == 2'd2) ? s_psram_ce : 1'b1;
assign psram.nss_o[3] = (~s_init_done) || (s_init_done && ribp.addr[24:23] == 2'd3) ? s_psram_ce : 1'b1;
assign psram.io_oe_o[0] = ~s_psram_sio_oen;
assign psram.io_oe_o[1] = ~s_psram_sio_oen;
assign psram.io_oe_o[2] = ~s_psram_sio_oen;
@@ -125,48 +125,48 @@ module rib_psram (
// verilog_format: on
assign s_mem_sel = `SOC_ADDR_IS_PSRAM(rib.addr);
assign s_cfg_reg_sel = `SOC_ADDR_IS_RIB_PSRAM(rib.addr);
assign rib.ready = s_mem_sel ? s_mem_ready : 1'b1;
assign s_mem_sel = `SOC_ADDR_IS_PSRAM(ribp.addr);
assign s_cfg_reg_sel = `SOC_ADDR_IS_RIBP_PSRAM(ribp.addr);
assign ribp.ready = s_mem_sel ? s_mem_ready : 1'b1;
always_comb begin
rib.rdata = '0;
ribp.rdata = '0;
if (s_mem_sel) begin
rib.rdata = s_mem_rdata;
end else if (rib.addr[7:0] == `RIB_PSRAM_WAIT) begin
rib.rdata = {27'd0, r_cfg_wait};
end else if (rib.addr[7:0] == `RIB_PSRAM_CHD) begin
rib.rdata = {29'd0, r_cfg_chd};
end else if (rib.addr[7:0] == `RIB_PSRAM_INIT) begin
rib.rdata = {31'd0, r_cfg_init};
ribp.rdata = s_mem_rdata;
end else if (ribp.addr[7:0] == `RIBP_PSRAM_WAIT) begin
ribp.rdata = {27'd0, r_cfg_wait};
end else if (ribp.addr[7:0] == `RIBP_PSRAM_CHD) begin
ribp.rdata = {29'd0, r_cfg_chd};
end else if (ribp.addr[7:0] == `RIBP_PSRAM_INIT) begin
ribp.rdata = {31'd0, r_cfg_init};
end
end
// wait cycles(mmio)
always_ff @(posedge clk_i, negedge rst_n_i) begin
if (~rst_n_i) r_cfg_wait <= 5'd18;
else if (rib.valid && rib.wstrb[0] && s_cfg_reg_sel && rib.addr[7:0] == `RIB_PSRAM_WAIT) begin
r_cfg_wait <= rib.wdata[4:0];
else if (ribp.valid && ribp.wstrb[0] && s_cfg_reg_sel && ribp.addr[7:0] == `RIBP_PSRAM_WAIT) begin
r_cfg_wait <= ribp.wdata[4:0];
end
end
// extra cycle for tCHD(mmio)
always_ff @(posedge clk_i, negedge rst_n_i) begin
if (~rst_n_i) r_cfg_chd <= 3'd4;
else if (rib.valid && rib.wstrb[0] && s_cfg_reg_sel && rib.addr[7:0] == `RIB_PSRAM_CHD) begin
r_cfg_chd <= rib.wdata[2:0];
else if (ribp.valid && ribp.wstrb[0] && s_cfg_reg_sel && ribp.addr[7:0] == `RIBP_PSRAM_CHD) begin
r_cfg_chd <= ribp.wdata[2:0];
end
end
// init device/switch qpi mode
always_ff @(posedge clk_i, negedge rst_n_i) begin
if (~rst_n_i) r_cfg_init <= '0;
else if (rib.valid && rib.wstrb[0] && s_cfg_reg_sel && rib.addr[7:0] == `RIB_PSRAM_INIT) begin
r_cfg_init <= rib.wdata[0];
else if (ribp.valid && ribp.wstrb[0] && s_cfg_reg_sel && ribp.addr[7:0] == `RIBP_PSRAM_INIT) begin
r_cfg_init <= ribp.wdata[0];
end
end
edge_det_sync_re #(1) u_mem_valid_edge_det_sync_re (
clk_i,
rst_n_i,
rib.valid,
ribp.valid,
s_mem_valid_re
);
@@ -183,16 +183,16 @@ module rib_psram (
/* verilator lint_off CASEINCOMPLETE */
case (r_fsm_state)
FSM_IDLE: begin
if (s_mem_valid_re && (|rib.wstrb)) begin
if (s_mem_valid_re && (|ribp.wstrb)) begin
r_fsm_state <= FSM_WE_ST;
r_xfer_data_bit_cnt <= s_disp_xfer_bit_cnt;
r_mem_addr <= {1'b0, rib.addr[22:0]} + {22'd0, s_disp_addr_ofst};
r_mem_addr <= {1'b0, ribp.addr[22:0]} + {22'd0, s_disp_addr_ofst};
r_mem_wdata <= s_disp_wdata;
end else if (s_mem_valid_re && (~(|rib.wstrb))) begin
end else if (s_mem_valid_re && (~(|ribp.wstrb))) begin
r_fsm_state <= FSM_RD_ST;
r_xfer_data_bit_cnt <= 8'd32;
r_mem_addr <= {1'b0, rib.addr[22:0]};
r_mem_wdata <= rib.wdata; // NOTE: no used
r_mem_addr <= {1'b0, ribp.addr[22:0]};
r_mem_wdata <= ribp.wdata; // NOTE: no used
end
end
FSM_WE_ST: begin
@@ -248,8 +248,8 @@ module rib_psram (
);
wr_dispatcher u_wr_dispatcher (
.wstrb_i (rib.wstrb),
.wdata_i (rib.wdata),
.wstrb_i (ribp.wstrb),
.wdata_i (ribp.wdata),
.addr_ofst_o (s_disp_addr_ofst),
.xfer_bit_cnt_o(s_disp_xfer_bit_cnt),
.wdata_o (s_disp_wdata)
rtl/ip/rib/memory/psram_core.sv → rtl/ip/ribp/memory/psram_core.sv
View File
File renamed without changes.
rtl/ip/rib/memory/sdram.sv → rtl/ip/ribp/memory/sdram.sv
+20 -20
View File
@@ -42,11 +42,11 @@ interface sdram_if ();
endinterface
module rib_sdram (
module ribp_sdram (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib,
ribp_if.slave ribp,
sdram_if.dut sdram
// verilog_format: on
);
@@ -58,34 +58,34 @@ module rib_sdram (
logic s_sec_edge;
// interface
rib_if u_reg_rib_if ();
rib_if u_mem_rib_if ();
ribp_if u_reg_ribp_if ();
ribp_if u_mem_ribp_if ();
// rib mux
assign s_sdram_reg_sel = `SOC_ADDR_IS_RIB_SDRAM(rib.addr);
assign u_reg_rib_if.valid = rib.valid && s_sdram_reg_sel;
assign u_reg_rib_if.addr = rib.addr;
assign u_reg_rib_if.wdata = rib.wdata;
assign u_reg_rib_if.wstrb = rib.wstrb;
// ribp mux
assign s_sdram_reg_sel = `SOC_ADDR_IS_RIBP_SDRAM(ribp.addr);
assign u_reg_ribp_if.valid = ribp.valid && s_sdram_reg_sel;
assign u_reg_ribp_if.addr = ribp.addr;
assign u_reg_ribp_if.wdata = ribp.wdata;
assign u_reg_ribp_if.wstrb = ribp.wstrb;
assign u_mem_rib_if.valid = rib.valid && (~s_sdram_reg_sel);
assign u_mem_rib_if.addr = rib.addr;
assign u_mem_rib_if.wdata = rib.wdata;
assign u_mem_rib_if.wstrb = rib.wstrb;
assign u_mem_ribp_if.valid = ribp.valid && (~s_sdram_reg_sel);
assign u_mem_ribp_if.addr = ribp.addr;
assign u_mem_ribp_if.wdata = ribp.wdata;
assign u_mem_ribp_if.wstrb = ribp.wstrb;
// verilog_format: off
assign rib.ready = (u_reg_rib_if.valid & u_reg_rib_if.ready) |
(u_mem_rib_if.valid & u_mem_rib_if.ready);
assign ribp.ready = (u_reg_ribp_if.valid & u_reg_ribp_if.ready) |
(u_mem_ribp_if.valid & u_mem_ribp_if.ready);
assign rib.rdata = ({32{(u_reg_rib_if.valid & u_reg_rib_if.ready)}} & u_reg_rib_if.rdata) |
({32{(u_mem_rib_if.valid & u_mem_rib_if.ready)}} & u_mem_rib_if.rdata);
assign ribp.rdata = ({32{(u_reg_ribp_if.valid & u_reg_ribp_if.ready)}} & u_reg_ribp_if.rdata) |
({32{(u_mem_ribp_if.valid & u_mem_ribp_if.ready)}} & u_mem_ribp_if.rdata);
// verilog_format: on
sdram_reg u_sdram_reg (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.rib (u_reg_rib_if),
.ribp (u_reg_ribp_if),
.clkdiv_o(s_sdram_clkdiv)
);
@@ -106,7 +106,7 @@ module rib_sdram (
.fir_edge_i (s_fir_edge),
.sec_edge_i (s_sec_edge),
.sdram_clk_i(s_sdram_clk),
.rib (u_mem_rib_if),
.ribp (u_mem_ribp_if),
.sdram (sdram)
);
rtl/ip/rib/memory/sdram_clkgen.sv → rtl/ip/ribp/memory/sdram_clkgen.sv
View File
File renamed without changes.
rtl/ip/rib/memory/sdram_core.sv → rtl/ip/ribp/memory/sdram_core.sv
+72 -72
View File
@@ -36,7 +36,7 @@ module sdram_core (
input logic sdram_clk_i,
input logic fir_edge_i,
input logic sec_edge_i,
rib_if.slave rib,
ribp_if.slave ribp,
sdram_if.dut sdram
// verilog_format: on
);
@@ -136,14 +136,14 @@ module sdram_core (
logic [12:0] s_addr_d, s_addr_q;
logic s_upd_ready_d, s_upd_ready_q;
// Registered RIB inputs (captured at IDLE→ACT)
logic [24:0] s_rib_addr_d, s_rib_addr_q; // addr[24:0] (relevant bits)
logic [31:0] s_rib_wdata_d, s_rib_wdata_q;
logic [3:0] s_rib_wstrb_d, s_rib_wstrb_q;
logic [24:0] s_ribp_addr_d, s_ribp_addr_q; // addr[24:0] (relevant bits)
logic [31:0] s_ribp_wdata_d, s_ribp_wdata_q;
logic [3:0] s_ribp_wstrb_d, s_ribp_wstrb_q;
// rib
assign rib.ready = s_ready_q;
assign rib.rdata = s_rdata_q;
// ribp
assign ribp.ready = s_ready_q;
assign ribp.rdata = s_rdata_q;
// sdram
assign sdram.clk_o = sdram_clk_i;
assign sdram.cke_o = s_cke_q;
@@ -157,23 +157,23 @@ module sdram_core (
always_comb begin
s_state_d = s_state_q;
s_ret_state_d = s_ret_state_q;
s_wait_cnt_d = s_wait_cnt_q;
s_cmd_d = s_cmd_q;
s_ready_d = s_ready_q;
s_rdata_d = s_rdata_q;
s_state_d = s_state_q;
s_ret_state_d = s_ret_state_q;
s_wait_cnt_d = s_wait_cnt_q;
s_cmd_d = s_cmd_q;
s_ready_d = s_ready_q;
s_rdata_d = s_rdata_q;
// sdram
s_dqm_d = s_dqm_q;
s_dq_d = s_dq_q;
s_ba_d = s_ba_q;
s_oe_d = s_oe_q;
s_cke_d = s_cke_q;
s_addr_d = s_addr_q;
s_upd_ready_d = s_upd_ready_q;
s_rib_addr_d = s_rib_addr_q;
s_rib_wdata_d = s_rib_wdata_q;
s_rib_wstrb_d = s_rib_wstrb_q;
s_dqm_d = s_dqm_q;
s_dq_d = s_dq_q;
s_ba_d = s_ba_q;
s_oe_d = s_oe_q;
s_cke_d = s_cke_q;
s_addr_d = s_addr_q;
s_upd_ready_d = s_upd_ready_q;
s_ribp_addr_d = s_ribp_addr_q;
s_ribp_wdata_d = s_ribp_wdata_q;
s_ribp_wstrb_d = s_ribp_wstrb_q;
case (s_state_q)
RESET: begin
s_cke_d = 1'b0;
@@ -218,18 +218,18 @@ module sdram_core (
s_oe_d = 1'b0;
s_dqm_d = 2'b11;
s_ready_d = 1'b0;
if (rib.valid && !s_ready_q) begin
if (ribp.valid && !s_ready_q) begin
// Capture RIB inputs into holding registers
s_rib_addr_d = rib.addr[24:0];
s_rib_wdata_d = rib.wdata;
s_rib_wstrb_d = rib.wstrb;
s_cmd_d = CMD_ACT;
s_ba_d = rib.addr[22:21];
s_addr_d = {rib.addr[24:23], rib.addr[20:10]};
s_state_d = WAIT_STATE;
s_ret_state_d = |rib.wstrb ? COL_WRITEL : COL_READ;
s_wait_cnt_d = 16'(TRCD);
s_upd_ready_d = 1'b1;
s_ribp_addr_d = ribp.addr[24:0];
s_ribp_wdata_d = ribp.wdata;
s_ribp_wstrb_d = ribp.wstrb;
s_cmd_d = CMD_ACT;
s_ba_d = ribp.addr[22:21];
s_addr_d = {ribp.addr[24:23], ribp.addr[20:10]};
s_state_d = WAIT_STATE;
s_ret_state_d = |ribp.wstrb ? COL_WRITEL : COL_READ;
s_wait_cnt_d = 16'(TRCD);
s_upd_ready_d = 1'b1;
end else begin
// autorefresh
s_cmd_d = CMD_RFSH;
@@ -246,8 +246,8 @@ module sdram_core (
s_cmd_d = CMD_READ;
s_dqm_d = 2'b00;
// autoprecharge and column (use registered addr)
s_ba_d = s_rib_addr_q[22:21];
s_addr_d = {3'b001, s_rib_addr_q[10:2], 1'b0};
s_ba_d = s_ribp_addr_q[22:21];
s_addr_d = {3'b001, s_ribp_addr_q[10:2], 1'b0};
// $display("rd col addr: %0x", s_addr_d);
s_state_d = WAIT_STATE;
s_ret_state_d = COL_READL;
@@ -269,19 +269,19 @@ module sdram_core (
end
COL_WRITEL: begin
s_cmd_d = CMD_WRITE;
s_dqm_d = ~s_rib_wstrb_q[1:0];
s_dqm_d = ~s_ribp_wstrb_q[1:0];
// autoprecharge and column (use registered addr)
s_ba_d = s_rib_addr_q[22:21];
s_addr_d = {3'b001, s_rib_addr_q[10:2], 1'b0};
s_dq_d = s_rib_wdata_q[15:0];
s_ba_d = s_ribp_addr_q[22:21];
s_addr_d = {3'b001, s_ribp_addr_q[10:2], 1'b0};
s_dq_d = s_ribp_wdata_q[15:0];
s_oe_d = 1'b1;
s_state_d = COL_WRITEH;
end
COL_WRITEH: begin
s_cmd_d = CMD_NOP;
s_dqm_d = ~s_rib_wstrb_q[3:2];
s_dqm_d = ~s_ribp_wstrb_q[3:2];
// autoprecharge and column (use registered wdata)
s_dq_d = s_rib_wdata_q[31:16];
s_dq_d = s_ribp_wdata_q[31:16];
s_oe_d = 1'b1;
s_state_d = WAIT_STATE;
s_ret_state_d = IDLE;
@@ -316,44 +316,44 @@ module sdram_core (
always_ff @(posedge clk_i, negedge rst_n_i) begin
if (~rst_n_i) begin
s_state_q <= RESET;
s_ret_state_q <= RESET;
s_wait_cnt_q <= '0;
s_cmd_q <= CMD_NOP;
s_ready_q <= '0;
s_rdata_q <= '0;
s_state_q <= RESET;
s_ret_state_q <= RESET;
s_wait_cnt_q <= '0;
s_cmd_q <= CMD_NOP;
s_ready_q <= '0;
s_rdata_q <= '0;
// sdram
s_dqm_q <= '1;
s_dq_q <= '0;
s_ba_q <= '1;
s_oe_q <= '0;
s_cke_q <= '0;
s_addr_q <= '0;
s_upd_ready_q <= '0;
s_rib_addr_q <= '0;
s_rib_wdata_q <= '0;
s_rib_wstrb_q <= '0;
s_dqm_q <= '1;
s_dq_q <= '0;
s_ba_q <= '1;
s_oe_q <= '0;
s_cke_q <= '0;
s_addr_q <= '0;
s_upd_ready_q <= '0;
s_ribp_addr_q <= '0;
s_ribp_wdata_q <= '0;
s_ribp_wstrb_q <= '0;
end else begin
s_ready_q <= s_ready_d;
if (fir_edge_i) begin
s_rdata_q <= s_rdata_d;
end
if (sec_edge_i) begin
s_state_q <= s_state_d;
s_ret_state_q <= s_ret_state_d;
s_wait_cnt_q <= s_wait_cnt_d;
s_cmd_q <= s_cmd_d;
s_state_q <= s_state_d;
s_ret_state_q <= s_ret_state_d;
s_wait_cnt_q <= s_wait_cnt_d;
s_cmd_q <= s_cmd_d;
// sdram
s_dqm_q <= s_dqm_d;
s_dq_q <= s_dq_d;
s_ba_q <= s_ba_d;
s_oe_q <= s_oe_d;
s_cke_q <= s_cke_d;
s_addr_q <= s_addr_d;
s_upd_ready_q <= s_upd_ready_d;
s_rib_addr_q <= s_rib_addr_d;
s_rib_wdata_q <= s_rib_wdata_d;
s_rib_wstrb_q <= s_rib_wstrb_d;
s_dqm_q <= s_dqm_d;
s_dq_q <= s_dq_d;
s_ba_q <= s_ba_d;
s_oe_q <= s_oe_d;
s_cke_q <= s_cke_d;
s_addr_q <= s_addr_d;
s_upd_ready_q <= s_upd_ready_d;
s_ribp_addr_q <= s_ribp_addr_d;
s_ribp_wdata_q <= s_ribp_wdata_d;
s_ribp_wstrb_q <= s_ribp_wstrb_d;
end
end
end
rtl/ip/ribp/memory/sdram_reg.sv
+84
View File
@@ -0,0 +1,84 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIBP_SDRAM_DEF_SV
`define RIBP_SDRAM_DEF_SV
// verilog_format: off
`define RIBP_SDRAM_CLKDIV 8'h00
`define RIBP_SDRAM_CFG 8'h04
// verilog_format: on
`endif
module sdram_reg (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
output logic [1:0] clkdiv_o
// verilog_format: on
);
// ribp
logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_rdata_en;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
// register
logic s_sdram_clkdiv_en;
logic [1:0] s_sdram_clkdiv_d, s_sdram_clkdiv_q;
// ribp
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.rdata = s_ribp_rdata_q;
// reg
assign clkdiv_o = s_sdram_clkdiv_q;
assign s_sdram_clkdiv_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SDRAM_CLKDIV;
assign s_sdram_clkdiv_d = ribp.wdata[1:0];
dffer #(2) u_sdram_clkdiv_dffer (
clk_i,
rst_n_i,
s_sdram_clkdiv_en,
s_sdram_clkdiv_d,
s_sdram_clkdiv_q
);
// ribp resp
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
dffr #(1) u_ribp_ready_dffr (
clk_i,
rst_n_i,
s_ribp_ready_d,
s_ribp_ready_q
);
assign s_ribp_rdata_en = s_ribp_rd_hdshk;
always_comb begin
s_ribp_rdata_d = s_ribp_rdata_q;
unique case (ribp.addr[7:0])
`RIBP_SDRAM_CLKDIV: s_ribp_rdata_d = {30'd0, s_sdram_clkdiv_q};
default: s_ribp_rdata_d = s_ribp_rdata_q;
endcase
end
dffer #(32) u_ribp_rdata_dffer (
clk_i,
rst_n_i,
s_ribp_rdata_en,
s_ribp_rdata_d,
s_ribp_rdata_q
);
endmodule
rtl/ip/rib/multimedia/dvp.sv → rtl/ip/ribp/multimedia/dvp.sv
+37 -37
View File
@@ -8,12 +8,12 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIB_DVP_DEF_SV
`define RIB_DVP_DEF_SV
`ifndef RIBP_DVP_DEF_SV
`define RIBP_DVP_DEF_SV
`define RIB_DVP_RECVEN 8'h00
`define RIB_DVP_RXDATA 8'h04
`define RIB_DVP_STATUS 8'h08
`define RIBP_DVP_RECVEN 8'h00
`define RIBP_DVP_RXDATA 8'h04
`define RIBP_DVP_STATUS 8'h08
`endif
@@ -26,19 +26,19 @@ interface dvp_if ();
modport dut(input pclk_i, input href_i, input vsync_i, input dat_i);
endinterface
module rib_dvp (
module ribp_dvp (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib,
ribp_if.slave ribp,
dvp_if.dut dvp
// verilog_format: on
);
// rib
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
// ribp
logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_rdata_en;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
// register
logic s_dvp_recven_en;
logic s_dvp_recven_d, s_dvp_recven_q;
@@ -53,15 +53,15 @@ module rib_dvp (
logic [31:0] s_rx_push_data, s_rx_pop_data;
logic [7:0] s_rx_elem_num;
// rib
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && rib.wstrb[0];
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
// ribp
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && ribp.wstrb[0];
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.rdata = s_ribp_rdata_q;
assign s_dvp_recven_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DVP_RECVEN;
assign s_dvp_recven_d = rib.wdata[0];
assign s_dvp_recven_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DVP_RECVEN;
assign s_dvp_recven_d = ribp.wdata[0];
dffer #(1) u_dvp_recven_dffer (
clk_i,
rst_n_i,
@@ -78,37 +78,37 @@ module rib_dvp (
s_dvp_status_q
);
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
dffr #(1) u_ribp_ready_dffr (
clk_i,
rst_n_i,
s_rib_ready_d,
s_rib_ready_q
s_ribp_ready_d,
s_ribp_ready_q
);
assign s_rib_rdata_en = s_rib_rd_hdshk;
assign s_ribp_rdata_en = s_ribp_rd_hdshk;
always_comb begin
s_rx_pop_valid = '0;
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_DVP_RECVEN: s_rib_rdata_d = {31'd0, s_dvp_recven_q};
`RIB_DVP_RXDATA: begin
if (s_rib_rd_hdshk) begin
s_ribp_rdata_d = s_ribp_rdata_q;
unique case (ribp.addr[7:0])
`RIBP_DVP_RECVEN: s_ribp_rdata_d = {31'd0, s_dvp_recven_q};
`RIBP_DVP_RXDATA: begin
if (s_ribp_rd_hdshk) begin
s_rx_pop_valid = 1'b1;
if (!s_rx_empty) s_rib_rdata_d = s_rx_pop_data;
else s_rib_rdata_d = '0;
if (!s_rx_empty) s_ribp_rdata_d = s_rx_pop_data;
else s_ribp_rdata_d = '0;
end
end
`RIB_DVP_STATUS: s_rib_rdata_d = {31'd0, s_dvp_status_q};
default: s_rib_rdata_d = s_rib_rdata_q;
`RIBP_DVP_STATUS: s_ribp_rdata_d = {31'd0, s_dvp_status_q};
default: s_ribp_rdata_d = s_ribp_rdata_q;
endcase
end
dffer #(32) u_rib_rdata_dffer (
dffer #(32) u_ribp_rdata_dffer (
clk_i,
rst_n_i,
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
s_ribp_rdata_en,
s_ribp_rdata_d,
s_ribp_rdata_q
);
rtl/ip/rib/multimedia/dvp_core.sv → rtl/ip/ribp/multimedia/dvp_core.sv
View File
File renamed without changes.
rtl/ip/ribp/peripheral/clint.sv
+180
View File
@@ -0,0 +1,180 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef CLINT_DEF_SV
`define CLINT_DEF_SV
// verilog_format: off
`define RIBP_CLINT_MTIMEL 8'h00
`define RIBP_CLINT_MTIMEH 8'h04
`define RIBP_CLINT_MTIMECMPL 8'h08
`define RIBP_CLINT_MTIMECMPH 8'h0C
`define RIBP_CLINT_MSIP 8'h10
`define RIBP_CLINT_CLKDIV 8'h14
// verilog_format: on
`endif
interface simp_clint_if ();
logic tmr_irq_o;
logic sfr_irq_o;
modport dut(output tmr_irq_o, output sfr_irq_o);
endinterface
module ribp_clint (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
simp_clint_if.dut clint
// verilog_format: on
);
logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_rdata_en;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
logic s_clint_clkdiv_en;
logic [7:0] s_clint_clkdiv_d, s_clint_clkdiv_q;
logic s_clint_mtime_en;
logic [63:0] s_clint_mtime_d, s_clint_mtime_q;
logic s_clint_mtimecmp_en;
logic [63:0] s_clint_mtimecmp_d, s_clint_mtimecmp_q;
logic s_clint_msip_en;
logic s_clint_msip_d, s_clint_msip_q;
// utils
logic [7:0] s_clk_cnt_d, s_clk_cnt_q;
// pipelined 64-bit compare: split into hi32 and lo32 stages
logic s_tmr_hi_gt, s_tmr_hi_eq, s_tmr_lo_ge;
logic s_tmr_irq_d, s_tmr_irq_q;
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.rdata = s_ribp_rdata_q;
// pipelined 64-bit magnitude compare (registered output)
assign s_tmr_hi_gt = s_clint_mtime_q[63:32] > s_clint_mtimecmp_q[63:32];
assign s_tmr_hi_eq = s_clint_mtime_q[63:32] == s_clint_mtimecmp_q[63:32];
assign s_tmr_lo_ge = s_clint_mtime_q[31:0] >= s_clint_mtimecmp_q[31:0];
assign s_tmr_irq_d = s_tmr_hi_gt || (s_tmr_hi_eq && s_tmr_lo_ge);
dffr #(1) u_tmr_irq_dffr (
clk_i,
rst_n_i,
s_tmr_irq_d,
s_tmr_irq_q
);
assign clint.tmr_irq_o = s_tmr_irq_q;
assign clint.sfr_irq_o = s_clint_msip_q;
assign s_clint_clkdiv_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_CLINT_CLKDIV;
assign s_clint_clkdiv_d = ribp.wdata[7:0];
dffer #(8) u_clint_clkdiv_dffer (
clk_i,
rst_n_i,
s_clint_clkdiv_en,
s_clint_clkdiv_d,
s_clint_clkdiv_q
);
always_comb begin
s_clk_cnt_d = s_clk_cnt_q;
if (s_clk_cnt_q == s_clint_clkdiv_q) begin
s_clk_cnt_d = '0;
end else begin
s_clk_cnt_d = s_clk_cnt_q + 1'b1;
end
end
dffr #(8) u_clk_cnt_dffr (
clk_i,
rst_n_i,
s_clk_cnt_d,
s_clk_cnt_q
);
assign s_clint_mtime_en = s_clk_cnt_q == s_clint_clkdiv_q;
assign s_clint_mtime_d = s_clint_mtime_q + 1'b1;
dffer #(64) u_clint_mtime_dffer (
clk_i,
rst_n_i,
s_clint_mtime_en,
s_clint_mtime_d,
s_clint_mtime_q
);
assign s_clint_mtimecmp_en = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_CLINT_MTIMECMPL || ribp.addr[7:0] == `RIBP_CLINT_MTIMECMPH);
always_comb begin
s_clint_mtimecmp_d = s_clint_mtimecmp_q;
if (ribp.addr[7:0] == `RIBP_CLINT_MTIMECMPL) begin
if (ribp.wstrb[0]) s_clint_mtimecmp_d[7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_clint_mtimecmp_d[15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_clint_mtimecmp_d[23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_clint_mtimecmp_d[31:24] = ribp.wdata[31:24];
end else if (ribp.addr[7:0] == `RIBP_CLINT_MTIMECMPH) begin
if (ribp.wstrb[0]) s_clint_mtimecmp_d[39:32] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_clint_mtimecmp_d[47:40] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_clint_mtimecmp_d[55:48] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_clint_mtimecmp_d[63:56] = ribp.wdata[31:24];
end
end
dfferh #(64) u_clint_mtimecmp_dfferh (
clk_i,
rst_n_i,
s_clint_mtimecmp_en,
s_clint_mtimecmp_d,
s_clint_mtimecmp_q
);
assign s_clint_msip_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_CLINT_MSIP;
assign s_clint_msip_d = ribp.wdata[0];
dffer #(1) u_clint_msip_dffer (
clk_i,
rst_n_i,
s_clint_msip_en,
s_clint_msip_d,
s_clint_msip_q
);
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
dffr #(1) u_ribp_ready_dffr (
clk_i,
rst_n_i,
s_ribp_ready_d,
s_ribp_ready_q
);
assign s_ribp_rdata_en = s_ribp_rd_hdshk;
always_comb begin
s_ribp_rdata_d = s_ribp_rdata_q;
unique case (ribp.addr[7:0])
`RIBP_CLINT_CLKDIV: s_ribp_rdata_d = {24'd0, s_clint_clkdiv_q};
`RIBP_CLINT_MTIMEL: s_ribp_rdata_d = s_clint_mtime_q[31:0];
`RIBP_CLINT_MTIMEH: s_ribp_rdata_d = s_clint_mtime_q[63:32];
`RIBP_CLINT_MTIMECMPL: s_ribp_rdata_d = s_clint_mtimecmp_q[31:0];
`RIBP_CLINT_MTIMECMPH: s_ribp_rdata_d = s_clint_mtimecmp_q[63:32];
`RIBP_CLINT_MSIP: s_ribp_rdata_d = {31'd0, s_clint_msip_q};
default: s_ribp_rdata_d = s_ribp_rdata_q;
endcase
end
dffer #(32) u_ribp_rdata_dffer (
clk_i,
rst_n_i,
s_ribp_rdata_en,
s_ribp_rdata_d,
s_ribp_rdata_q
);
endmodule
rtl/ip/rib/peripheral/dma.sv → rtl/ip/ribp/peripheral/dma.sv
+76 -76
View File
@@ -8,23 +8,23 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIB_DMA_DEF_SV
`define RIB_DMA_DEF_SV
`ifndef RIBP_DMA_DEF_SV
`define RIBP_DMA_DEF_SV
// verilog_format: off
`define RIB_DMA_MODE 8'h00
`define RIB_DMA_SRCADDR 8'h04
`define RIB_DMA_SRCINCR 8'h08
`define RIB_DMA_DSTADDR 8'h0C
`define RIB_DMA_DSTINCR 8'h10
`define RIB_DMA_XFERLEN 8'h14
`define RIB_DMA_START 8'h18
`define RIB_DMA_STOP 8'h1C
`define RIB_DMA_RESET 8'h20
`define RIB_DMA_STATUS 8'h24
`define RIB_DMA_FSM 8'h28
`define RIB_DMA_ERROR_STATUS 8'h2C
`define RIB_DMA_ERROR_ADDR 8'h30
`define RIBP_DMA_MODE 8'h00
`define RIBP_DMA_SRCADDR 8'h04
`define RIBP_DMA_SRCINCR 8'h08
`define RIBP_DMA_DSTADDR 8'h0C
`define RIBP_DMA_DSTINCR 8'h10
`define RIBP_DMA_XFERLEN 8'h14
`define RIBP_DMA_START 8'h18
`define RIBP_DMA_STOP 8'h1C
`define RIBP_DMA_RESET 8'h20
`define RIBP_DMA_STATUS 8'h24
`define RIBP_DMA_FSM 8'h28
`define RIBP_DMA_ERROR_STATUS 8'h2C
`define RIBP_DMA_ERROR_ADDR 8'h30
// verilog_format: on
interface dma_hw_trg_if ();
@@ -38,21 +38,21 @@ endinterface
`endif
module rib_dma (
module ribp_dma (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
output logic dma_xfer_done_o,
dma_hw_trg_if.dut hw_trg,
rib_if.slave rib,
soc_rib_burst_if.master rib_dma
ribp_if.slave ribp,
soc_rib_if.master rib
// verilog_format: on
);
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_rdata_en;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
logic s_dma_mode_en;
logic [2:0] s_dma_mode_d, s_dma_mode_q;
@@ -78,16 +78,16 @@ module rib_dma (
logic [31:0] s_xfer_error_addr;
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.rdata = s_ribp_rdata_q;
assign dma_xfer_done_o = s_dma_status_q;
assign s_dma_mode_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DMA_MODE;
assign s_dma_mode_d = rib.wdata[2:0];
assign s_dma_mode_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_MODE;
assign s_dma_mode_d = ribp.wdata[2:0];
dffer #(3) u_dma_mode_dffer (
clk_i,
rst_n_i,
@@ -97,13 +97,13 @@ module rib_dma (
);
assign s_dma_srcaddr_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DMA_SRCADDR;
assign s_dma_srcaddr_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_SRCADDR;
always_comb begin
s_dma_srcaddr_d = s_dma_srcaddr_q;
if (rib.wstrb[0]) s_dma_srcaddr_d[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_dma_srcaddr_d[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_dma_srcaddr_d[23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_dma_srcaddr_d[31:24] = rib.wdata[31:24];
if (ribp.wstrb[0]) s_dma_srcaddr_d[7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_dma_srcaddr_d[15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_dma_srcaddr_d[23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_dma_srcaddr_d[31:24] = ribp.wdata[31:24];
end
dffer #(32) u_dma_srcaddr_dffer (
clk_i,
@@ -114,8 +114,8 @@ module rib_dma (
);
assign s_dma_srcincr_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DMA_SRCINCR;
assign s_dma_srcincr_d = rib.wdata[0];
assign s_dma_srcincr_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_SRCINCR;
assign s_dma_srcincr_d = ribp.wdata[0];
dffer #(1) u_dma_srcincr_dffer (
clk_i,
rst_n_i,
@@ -125,13 +125,13 @@ module rib_dma (
);
assign s_dma_dstaddr_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DMA_DSTADDR;
assign s_dma_dstaddr_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_DSTADDR;
always_comb begin
s_dma_dstaddr_d = s_dma_dstaddr_q;
if (rib.wstrb[0]) s_dma_dstaddr_d[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_dma_dstaddr_d[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_dma_dstaddr_d[23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_dma_dstaddr_d[31:24] = rib.wdata[31:24];
if (ribp.wstrb[0]) s_dma_dstaddr_d[7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_dma_dstaddr_d[15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_dma_dstaddr_d[23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_dma_dstaddr_d[31:24] = ribp.wdata[31:24];
end
dffer #(32) u_dma_dstaddr_dffer (
clk_i,
@@ -141,8 +141,8 @@ module rib_dma (
s_dma_dstaddr_q
);
assign s_dma_dstincr_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DMA_DSTINCR;
assign s_dma_dstincr_d = rib.wdata[0];
assign s_dma_dstincr_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_DSTINCR;
assign s_dma_dstincr_d = ribp.wdata[0];
dffer #(1) u_dma_dstincr_dffer (
clk_i,
rst_n_i,
@@ -151,13 +151,13 @@ module rib_dma (
s_dma_dstincr_q
);
assign s_dma_xferlen_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DMA_XFERLEN;
assign s_dma_xferlen_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_XFERLEN;
always_comb begin
s_dma_xferlen_d = s_dma_xferlen_q;
if (rib.wstrb[0]) s_dma_xferlen_d[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_dma_xferlen_d[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_dma_xferlen_d[23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_dma_xferlen_d[31:24] = rib.wdata[31:24];
if (ribp.wstrb[0]) s_dma_xferlen_d[7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_dma_xferlen_d[15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_dma_xferlen_d[23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_dma_xferlen_d[31:24] = ribp.wdata[31:24];
end
dffer #(32) u_dma_xferlen_dffer (
clk_i,
@@ -168,14 +168,14 @@ module rib_dma (
);
assign s_xfer_start = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DMA_START;
assign s_xfer_stop = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DMA_STOP;
assign s_xfer_reset = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DMA_RESET;
assign s_xfer_start = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_START;
assign s_xfer_stop = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_STOP;
assign s_xfer_reset = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_RESET;
always_comb begin
s_dma_status_d = s_dma_status_q;
if (s_rib_rd_hdshk && rib.addr[7:0] == `RIB_DMA_STATUS) begin
if (s_ribp_rd_hdshk && ribp.addr[7:0] == `RIBP_DMA_STATUS) begin
s_dma_status_d = '0;
end else if (s_xfer_done) begin
s_dma_status_d = 1'b1;
@@ -190,8 +190,8 @@ module rib_dma (
always_comb begin
s_dma_error_status_d = s_dma_error_status_q;
if (s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DMA_ERROR_STATUS && rib.wstrb[0] &&
rib.wdata[0]) begin
if (s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_DMA_ERROR_STATUS && ribp.wstrb[0] &&
ribp.wdata[0]) begin
s_dma_error_status_d = 1'b0;
end else if (s_xfer_error) begin
s_dma_error_status_d = 1'b1;
@@ -221,37 +221,37 @@ module rib_dma (
);
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
dffr #(1) u_ribp_ready_dffr (
clk_i,
rst_n_i,
s_rib_ready_d,
s_rib_ready_q
s_ribp_ready_d,
s_ribp_ready_q
);
assign s_rib_rdata_en = s_rib_rd_hdshk;
assign s_ribp_rdata_en = s_ribp_rd_hdshk;
always_comb begin
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_DMA_MODE: s_rib_rdata_d = {29'd0, s_dma_mode_q};
`RIB_DMA_SRCADDR: s_rib_rdata_d = s_dma_srcaddr_q;
`RIB_DMA_SRCINCR: s_rib_rdata_d = {31'd0, s_dma_srcincr_q};
`RIB_DMA_DSTADDR: s_rib_rdata_d = s_dma_dstaddr_q;
`RIB_DMA_DSTINCR: s_rib_rdata_d = {31'd0, s_dma_dstincr_q};
`RIB_DMA_XFERLEN: s_rib_rdata_d = s_dma_xferlen_q;
`RIB_DMA_STATUS: s_rib_rdata_d = {31'd0, s_dma_status_q};
`RIB_DMA_FSM: s_rib_rdata_d = {30'd0, s_xfer_fsm};
`RIB_DMA_ERROR_STATUS: s_rib_rdata_d = {28'd0, s_dma_error_code_q, s_dma_error_status_q};
`RIB_DMA_ERROR_ADDR: s_rib_rdata_d = s_dma_error_addr_q;
default: s_rib_rdata_d = s_rib_rdata_q;
s_ribp_rdata_d = s_ribp_rdata_q;
unique case (ribp.addr[7:0])
`RIBP_DMA_MODE: s_ribp_rdata_d = {29'd0, s_dma_mode_q};
`RIBP_DMA_SRCADDR: s_ribp_rdata_d = s_dma_srcaddr_q;
`RIBP_DMA_SRCINCR: s_ribp_rdata_d = {31'd0, s_dma_srcincr_q};
`RIBP_DMA_DSTADDR: s_ribp_rdata_d = s_dma_dstaddr_q;
`RIBP_DMA_DSTINCR: s_ribp_rdata_d = {31'd0, s_dma_dstincr_q};
`RIBP_DMA_XFERLEN: s_ribp_rdata_d = s_dma_xferlen_q;
`RIBP_DMA_STATUS: s_ribp_rdata_d = {31'd0, s_dma_status_q};
`RIBP_DMA_FSM: s_ribp_rdata_d = {30'd0, s_xfer_fsm};
`RIBP_DMA_ERROR_STATUS: s_ribp_rdata_d = {28'd0, s_dma_error_code_q, s_dma_error_status_q};
`RIBP_DMA_ERROR_ADDR: s_ribp_rdata_d = s_dma_error_addr_q;
default: s_ribp_rdata_d = s_ribp_rdata_q;
endcase
end
dffer #(32) u_rib_rdata_dffer (
dffer #(32) u_ribp_rdata_dffer (
clk_i,
rst_n_i,
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
s_ribp_rdata_en,
s_ribp_rdata_d,
s_ribp_rdata_q
);
@@ -273,7 +273,7 @@ module rib_dma (
.error_addr_o(s_xfer_error_addr),
.fsm_o (s_xfer_fsm),
.hw_trg (hw_trg),
.rib (rib_dma)
.rib (rib)
);
endmodule
rtl/ip/rib/peripheral/dma_core.sv → rtl/ip/ribp/peripheral/dma_core.sv
+2 -2
View File
@@ -30,7 +30,7 @@ module dma_core (
output logic [31:0] error_addr_o,
output logic [1:0] fsm_o,
dma_hw_trg_if.dut hw_trg,
soc_rib_burst_if.master rib
soc_rib_if.master rib
// verilog_format: on
);
@@ -78,7 +78,7 @@ module dma_core (
`SOC_ADDR_SUPPORTS_INCR4(s_dst_addr_q) &&
`SOC_ADDR_SUPPORTS_INCR4(s_dst_addr_q + 32'd12);
// verilog_format: on
assign s_chunk_len = s_use_burst ? `SOC_RIB_BURST_INCR4 : `SOC_RIB_BURST_INCR1;
assign s_chunk_len = s_use_burst ? `SOC_RIB_LEN_INCR4 : `SOC_RIB_LEN_INCR1;
assign s_chunk_words = s_use_burst ? 32'd4 : 32'd1;
always_comb begin
rtl/ip/rib/peripheral/gpio.sv → rtl/ip/ribp/peripheral/gpio.sv
+110 -110
View File
@@ -32,7 +32,7 @@
`include "gpio_define.svh"
interface gpio_if #(
parameter int DATA_WIDTH = `RIB_GPIO_NUM
parameter int DATA_WIDTH = `RIBP_GPIO_NUM
) ();
logic [DATA_WIDTH-1:0] oe_o;
logic [DATA_WIDTH-1:0] cs_o;
@@ -66,7 +66,7 @@ interface gpio_if #(
endinterface
interface user_gpio_if #(
parameter int DATA_WIDTH = `RIB_GPIO_NUM
parameter int DATA_WIDTH = `RIBP_GPIO_NUM
) ();
logic [DATA_WIDTH-1:0] do_o;
logic [DATA_WIDTH-1:0] oe_o;
@@ -76,80 +76,80 @@ interface user_gpio_if #(
modport padctrl(input do_o, input oe_o, output di_i);
endinterface
module rib_gpio (
module ribp_gpio (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib,
ribp_if.slave ribp,
gpio_if.dut gpio,
user_gpio_if.padctrl user_gpio
// verilog_format: on
);
// rib
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
// ribp
logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_rdata_en;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
// reg
logic s_gpio_oe_en;
logic [`RIB_GPIO_NUM-1:0] s_gpio_oe_d, s_gpio_oe_q;
logic [`RIBP_GPIO_NUM-1:0] s_gpio_oe_d, s_gpio_oe_q;
logic s_gpio_cs_en;
logic [`RIB_GPIO_NUM-1:0] s_gpio_cs_d, s_gpio_cs_q;
logic [`RIBP_GPIO_NUM-1:0] s_gpio_cs_d, s_gpio_cs_q;
logic s_gpio_pu_en;
logic [`RIB_GPIO_NUM-1:0] s_gpio_pu_d, s_gpio_pu_q;
logic [`RIBP_GPIO_NUM-1:0] s_gpio_pu_d, s_gpio_pu_q;
logic s_gpio_pd_en;
logic [`RIB_GPIO_NUM-1:0] s_gpio_pd_d, s_gpio_pd_q;
logic [`RIBP_GPIO_NUM-1:0] s_gpio_pd_d, s_gpio_pd_q;
logic s_gpio_do_en;
logic [`RIB_GPIO_NUM-1:0] s_gpio_do_d, s_gpio_do_q;
logic [`RIB_GPIO_NUM-1:0] s_gpio_di;
logic s_gpio_ien_en;
logic [`RIB_GPIO_NUM-1:0] s_gpio_ien_d, s_gpio_ien_q;
logic [`RIBP_GPIO_NUM-1:0] s_gpio_do_d, s_gpio_do_q;
logic [`RIBP_GPIO_NUM-1:0] s_gpio_di;
logic s_gpio_ien_en;
logic [`RIBP_GPIO_NUM-1:0] s_gpio_ien_d, s_gpio_ien_q;
logic s_gpio_itype0_en;
logic [`RIB_GPIO_NUM-1:0] s_gpio_itype0_d, s_gpio_itype0_q;
logic [`RIBP_GPIO_NUM-1:0] s_gpio_itype0_d, s_gpio_itype0_q;
logic s_gpio_itype1_en;
logic [`RIB_GPIO_NUM-1:0] s_gpio_itype1_d, s_gpio_itype1_q;
logic [`RIBP_GPIO_NUM-1:0] s_gpio_itype1_d, s_gpio_itype1_q;
logic s_gpio_istat_en;
logic [`RIB_GPIO_NUM-1:0] s_gpio_istat_d, s_gpio_istat_q;
logic [`RIBP_GPIO_NUM-1:0] s_gpio_istat_d, s_gpio_istat_q;
logic s_gpio_iofcfg_en;
logic [`RIB_GPIO_NUM-1:0] s_gpio_iofcfg_d, s_gpio_iofcfg_q;
logic [`RIBP_GPIO_NUM-1:0] s_gpio_iofcfg_d, s_gpio_iofcfg_q;
logic s_gpio_pinmux_en;
logic [`RIB_GPIO_NUM-1:0] s_gpio_pinmux_d, s_gpio_pinmux_q;
logic [`RIBP_GPIO_NUM-1:0] s_gpio_pinmux_d, s_gpio_pinmux_q;
logic s_gpio_user_sel_en;
logic [`RIB_GPIO_NUM-1:0] s_gpio_user_sel_d, s_gpio_user_sel_q;
logic [`RIBP_GPIO_NUM-1:0] s_gpio_user_sel_d, s_gpio_user_sel_q;
logic s_gpio_user_lock_en;
logic [`RIB_GPIO_NUM-1:0] s_gpio_user_lock_d, s_gpio_user_lock_q;
logic [`RIB_GPIO_NUM-1:0] s_gpio_user_handoff_d, s_gpio_user_handoff_q;
logic [`RIB_GPIO_NUM-1:0] s_gpio_user_status;
logic [`RIBP_GPIO_NUM-1:0] s_gpio_user_lock_d, s_gpio_user_lock_q;
logic [`RIBP_GPIO_NUM-1:0] s_gpio_user_handoff_d, s_gpio_user_handoff_q;
logic [`RIBP_GPIO_NUM-1:0] s_gpio_user_status;
// irq
logic [`RIB_GPIO_NUM-1:0] s_gpio_di_re, s_gpio_di_fe, s_gpio_irq;
logic [`RIB_GPIO_NUM-1:0] s_irq_rise, s_irq_fall;
logic [`RIB_GPIO_NUM-1:0] s_irq_lev0, s_irq_lev1;
logic [`RIB_GPIO_NUM-1:0] s_irq_masked;
logic [`RIBP_GPIO_NUM-1:0] s_gpio_di_re, s_gpio_di_fe, s_gpio_irq;
logic [`RIBP_GPIO_NUM-1:0] s_irq_rise, s_irq_fall;
logic [`RIBP_GPIO_NUM-1:0] s_irq_lev0, s_irq_lev1;
logic [`RIBP_GPIO_NUM-1:0] s_irq_masked;
logic s_irq_trg, s_irq_stat;
// alt
logic [`RIB_GPIO_NUM-1:0] s_gpio_alt_out, s_gpio_alt_oe;
logic [`RIB_GPIO_NUM-1:0] s_gpio_native_out, s_gpio_native_oe;
logic [`RIBP_GPIO_NUM-1:0] s_gpio_alt_out, s_gpio_alt_oe;
logic [`RIBP_GPIO_NUM-1:0] s_gpio_native_out, s_gpio_native_oe;
// shake
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.rdata = s_ribp_rdata_q;
// gpio
assign gpio.cs_o = s_gpio_cs_q; // 1: CMOS 0: SCHMI
assign gpio.pu_o = s_gpio_pu_q;
assign gpio.pd_o = s_gpio_pd_q;
for (genvar i = 0; i < `RIB_GPIO_NUM; i++) begin : ALT_PINMUX_BLOCK
assign gpio.cs_o = s_gpio_cs_q; // 1: CMOS 0: SCHMI
assign gpio.pu_o = s_gpio_pu_q;
assign gpio.pd_o = s_gpio_pd_q;
for (genvar i = 0; i < `RIBP_GPIO_NUM; i++) begin : ALT_PINMUX_BLOCK
assign s_gpio_alt_oe[i] = s_gpio_pinmux_q[i] ? gpio.alt1_oe_i[i] : gpio.alt0_oe_i[i];
assign s_gpio_alt_out[i] = s_gpio_pinmux_q[i] ? gpio.alt1_do_i[i] : gpio.alt0_do_i[i];
end
for (genvar i = 0; i < `RIB_GPIO_NUM; i++) begin : IOF_PINMUX_BLOCK
for (genvar i = 0; i < `RIBP_GPIO_NUM; i++) begin : IOF_PINMUX_BLOCK
assign s_gpio_native_oe[i] = s_gpio_iofcfg_q[i] ? s_gpio_alt_oe[i] : s_gpio_oe_q[i];
assign s_gpio_native_out[i] = s_gpio_iofcfg_q[i] ? s_gpio_alt_out[i] : s_gpio_do_q[i];
end
assign user_gpio.di_i = gpio.di_i;
for (genvar i = 0; i < `RIB_GPIO_NUM; i++) begin : USER_GPIO_MUX_BLOCK
for (genvar i = 0; i < `RIBP_GPIO_NUM; i++) begin : USER_GPIO_MUX_BLOCK
assign gpio.oe_o[i] = s_gpio_user_handoff_q[i]
? 1'b0
: (s_gpio_user_sel_q[i] ? user_gpio.oe_o[i] : s_gpio_native_oe[i]);
@@ -171,7 +171,7 @@ module rib_gpio (
edge_det #(
.STAGE (2),
.DATA_WIDTH(`RIB_GPIO_NUM)
.DATA_WIDTH(`RIBP_GPIO_NUM)
) u_gpio_di_edge_det (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
@@ -182,9 +182,9 @@ module rib_gpio (
);
// register
assign s_gpio_oe_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_OE;
assign s_gpio_oe_d = rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_oe_dffer (
assign s_gpio_oe_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_GPIO_OE;
assign s_gpio_oe_d = ribp.wdata[`RIBP_GPIO_NUM-1:0];
dffer #(`RIBP_GPIO_NUM) u_gpio_oe_dffer (
clk_i,
rst_n_i,
s_gpio_oe_en,
@@ -193,9 +193,9 @@ module rib_gpio (
);
assign s_gpio_cs_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_CS;
assign s_gpio_cs_d = rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_cs_dffer (
assign s_gpio_cs_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_GPIO_CS;
assign s_gpio_cs_d = ribp.wdata[`RIBP_GPIO_NUM-1:0];
dffer #(`RIBP_GPIO_NUM) u_gpio_cs_dffer (
clk_i,
rst_n_i,
s_gpio_cs_en,
@@ -204,9 +204,9 @@ module rib_gpio (
);
assign s_gpio_pu_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_PU;
assign s_gpio_pu_d = rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_pu_dffer (
assign s_gpio_pu_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_GPIO_PU;
assign s_gpio_pu_d = ribp.wdata[`RIBP_GPIO_NUM-1:0];
dffer #(`RIBP_GPIO_NUM) u_gpio_pu_dffer (
clk_i,
rst_n_i,
s_gpio_pu_en,
@@ -215,9 +215,9 @@ module rib_gpio (
);
assign s_gpio_pd_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_PD;
assign s_gpio_pd_d = rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_pd_dffer (
assign s_gpio_pd_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_GPIO_PD;
assign s_gpio_pd_d = ribp.wdata[`RIBP_GPIO_NUM-1:0];
dffer #(`RIBP_GPIO_NUM) u_gpio_pd_dffer (
clk_i,
rst_n_i,
s_gpio_pd_en,
@@ -226,9 +226,9 @@ module rib_gpio (
);
assign s_gpio_do_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_DO;
assign s_gpio_do_d = rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_do_dffer (
assign s_gpio_do_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_GPIO_DO;
assign s_gpio_do_d = ribp.wdata[`RIBP_GPIO_NUM-1:0];
dffer #(`RIBP_GPIO_NUM) u_gpio_do_dffer (
clk_i,
rst_n_i,
s_gpio_do_en,
@@ -237,9 +237,9 @@ module rib_gpio (
);
assign s_gpio_ien_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_IEN;
assign s_gpio_ien_d = rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_ien_dffer (
assign s_gpio_ien_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_GPIO_IEN;
assign s_gpio_ien_d = ribp.wdata[`RIBP_GPIO_NUM-1:0];
dffer #(`RIBP_GPIO_NUM) u_gpio_ien_dffer (
clk_i,
rst_n_i,
s_gpio_ien_en,
@@ -248,9 +248,9 @@ module rib_gpio (
);
assign s_gpio_itype0_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_ITYPE0;
assign s_gpio_itype0_d = rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_itype0_dffer (
assign s_gpio_itype0_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_GPIO_ITYPE0;
assign s_gpio_itype0_d = ribp.wdata[`RIBP_GPIO_NUM-1:0];
dffer #(`RIBP_GPIO_NUM) u_gpio_itype0_dffer (
clk_i,
rst_n_i,
s_gpio_itype0_en,
@@ -259,9 +259,9 @@ module rib_gpio (
);
assign s_gpio_itype1_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_ITYPE1;
assign s_gpio_itype1_d = rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_itype1_dffer (
assign s_gpio_itype1_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_GPIO_ITYPE1;
assign s_gpio_itype1_d = ribp.wdata[`RIBP_GPIO_NUM-1:0];
dffer #(`RIBP_GPIO_NUM) u_gpio_itype1_dffer (
clk_i,
rst_n_i,
s_gpio_itype1_en,
@@ -270,9 +270,9 @@ module rib_gpio (
);
assign s_gpio_iofcfg_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_IOFCFG;
assign s_gpio_iofcfg_d = rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_iocfg_dffer (
assign s_gpio_iofcfg_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_GPIO_IOFCFG;
assign s_gpio_iofcfg_d = ribp.wdata[`RIBP_GPIO_NUM-1:0];
dffer #(`RIBP_GPIO_NUM) u_gpio_iocfg_dffer (
clk_i,
rst_n_i,
s_gpio_iofcfg_en,
@@ -284,7 +284,7 @@ module rib_gpio (
always_comb begin
s_gpio_istat_en = 1'b0;
s_gpio_istat_d = s_gpio_istat_q;
if (s_irq_stat && s_rib_rd_hdshk && rib.addr[7:0] == `RIB_GPIO_ISTAT) begin
if (s_irq_stat && s_ribp_rd_hdshk && ribp.addr[7:0] == `RIBP_GPIO_ISTAT) begin
s_gpio_istat_en = 1'b1;
// HACK: clear all irq
s_gpio_istat_d = '0;
@@ -293,7 +293,7 @@ module rib_gpio (
s_gpio_istat_d = s_irq_masked;
end
end
dffer #(`RIB_GPIO_NUM) u_gpio_istat_dffer (
dffer #(`RIBP_GPIO_NUM) u_gpio_istat_dffer (
clk_i,
rst_n_i,
s_gpio_istat_en,
@@ -302,9 +302,9 @@ module rib_gpio (
);
assign s_gpio_pinmux_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_PINMUX;
assign s_gpio_pinmux_d = rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_pinmux_dffer (
assign s_gpio_pinmux_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_GPIO_PINMUX;
assign s_gpio_pinmux_d = ribp.wdata[`RIBP_GPIO_NUM-1:0];
dffer #(`RIBP_GPIO_NUM) u_gpio_pinmux_dffer (
clk_i,
rst_n_i,
s_gpio_pinmux_en,
@@ -312,10 +312,10 @@ module rib_gpio (
s_gpio_pinmux_q
);
assign s_gpio_user_sel_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_USER_SEL;
assign s_gpio_user_sel_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_GPIO_USER_SEL;
assign s_gpio_user_sel_d = (s_gpio_user_sel_q & s_gpio_user_lock_q) |
(rib.wdata[`RIB_GPIO_NUM-1:0] & ~s_gpio_user_lock_q);
dffer #(`RIB_GPIO_NUM) u_gpio_user_sel_dffer (
(ribp.wdata[`RIBP_GPIO_NUM-1:0] & ~s_gpio_user_lock_q);
dffer #(`RIBP_GPIO_NUM) u_gpio_user_sel_dffer (
clk_i,
rst_n_i,
s_gpio_user_sel_en,
@@ -323,9 +323,9 @@ module rib_gpio (
s_gpio_user_sel_q
);
assign s_gpio_user_lock_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_USER_LOCK;
assign s_gpio_user_lock_d = s_gpio_user_lock_q | rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_user_lock_dffer (
assign s_gpio_user_lock_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_GPIO_USER_LOCK;
assign s_gpio_user_lock_d = s_gpio_user_lock_q | ribp.wdata[`RIBP_GPIO_NUM-1:0];
dffer #(`RIBP_GPIO_NUM) u_gpio_user_lock_dffer (
clk_i,
rst_n_i,
s_gpio_user_lock_en,
@@ -334,7 +334,7 @@ module rib_gpio (
);
assign s_gpio_user_handoff_d = s_gpio_user_sel_en ? (s_gpio_user_sel_d ^ s_gpio_user_sel_q) : '0;
dffr #(`RIB_GPIO_NUM) u_gpio_user_handoff_dffr (
dffr #(`RIBP_GPIO_NUM) u_gpio_user_handoff_dffr (
clk_i,
rst_n_i,
s_gpio_user_handoff_d,
@@ -343,43 +343,43 @@ module rib_gpio (
assign s_gpio_user_status = s_gpio_user_sel_q & ~s_gpio_user_handoff_q;
// rib resp
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
// ribp resp
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
dffr #(1) u_ribp_ready_dffr (
clk_i,
rst_n_i,
s_rib_ready_d,
s_rib_ready_q
s_ribp_ready_d,
s_ribp_ready_q
);
assign s_rib_rdata_en = s_rib_rd_hdshk;
assign s_ribp_rdata_en = s_ribp_rd_hdshk;
always_comb begin
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_GPIO_OE: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_oe_q};
`RIB_GPIO_CS: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_cs_q};
`RIB_GPIO_PU: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_pu_q};
`RIB_GPIO_PD: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_pd_q};
`RIB_GPIO_DO: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_do_q};
`RIB_GPIO_DI: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_di};
`RIB_GPIO_IEN: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_ien_q};
`RIB_GPIO_ITYPE0: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_itype0_q};
`RIB_GPIO_ITYPE1: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_itype1_q};
`RIB_GPIO_ISTAT: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_istat_q};
`RIB_GPIO_IOFCFG: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_iofcfg_q};
`RIB_GPIO_PINMUX: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_pinmux_q};
`RIB_GPIO_USER_SEL: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_user_sel_q};
`RIB_GPIO_USER_LOCK: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_user_lock_q};
`RIB_GPIO_USER_STATUS: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_user_status};
default: s_rib_rdata_d = s_rib_rdata_q;
s_ribp_rdata_d = s_ribp_rdata_q;
unique case (ribp.addr[7:0])
`RIBP_GPIO_OE: s_ribp_rdata_d = {{(32 - `RIBP_GPIO_NUM) {1'b0}}, s_gpio_oe_q};
`RIBP_GPIO_CS: s_ribp_rdata_d = {{(32 - `RIBP_GPIO_NUM) {1'b0}}, s_gpio_cs_q};
`RIBP_GPIO_PU: s_ribp_rdata_d = {{(32 - `RIBP_GPIO_NUM) {1'b0}}, s_gpio_pu_q};
`RIBP_GPIO_PD: s_ribp_rdata_d = {{(32 - `RIBP_GPIO_NUM) {1'b0}}, s_gpio_pd_q};
`RIBP_GPIO_DO: s_ribp_rdata_d = {{(32 - `RIBP_GPIO_NUM) {1'b0}}, s_gpio_do_q};
`RIBP_GPIO_DI: s_ribp_rdata_d = {{(32 - `RIBP_GPIO_NUM) {1'b0}}, s_gpio_di};
`RIBP_GPIO_IEN: s_ribp_rdata_d = {{(32 - `RIBP_GPIO_NUM) {1'b0}}, s_gpio_ien_q};
`RIBP_GPIO_ITYPE0: s_ribp_rdata_d = {{(32 - `RIBP_GPIO_NUM) {1'b0}}, s_gpio_itype0_q};
`RIBP_GPIO_ITYPE1: s_ribp_rdata_d = {{(32 - `RIBP_GPIO_NUM) {1'b0}}, s_gpio_itype1_q};
`RIBP_GPIO_ISTAT: s_ribp_rdata_d = {{(32 - `RIBP_GPIO_NUM) {1'b0}}, s_gpio_istat_q};
`RIBP_GPIO_IOFCFG: s_ribp_rdata_d = {{(32 - `RIBP_GPIO_NUM) {1'b0}}, s_gpio_iofcfg_q};
`RIBP_GPIO_PINMUX: s_ribp_rdata_d = {{(32 - `RIBP_GPIO_NUM) {1'b0}}, s_gpio_pinmux_q};
`RIBP_GPIO_USER_SEL: s_ribp_rdata_d = {{(32 - `RIBP_GPIO_NUM) {1'b0}}, s_gpio_user_sel_q};
`RIBP_GPIO_USER_LOCK: s_ribp_rdata_d = {{(32 - `RIBP_GPIO_NUM) {1'b0}}, s_gpio_user_lock_q};
`RIBP_GPIO_USER_STATUS: s_ribp_rdata_d = {{(32 - `RIBP_GPIO_NUM) {1'b0}}, s_gpio_user_status};
default: s_ribp_rdata_d = s_ribp_rdata_q;
endcase
end
dffer #(32) u_rib_rdata_dffer (
dffer #(32) u_ribp_rdata_dffer (
clk_i,
rst_n_i,
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
s_ribp_rdata_en,
s_ribp_rdata_d,
s_ribp_rdata_q
);
endmodule
rtl/ip/ribp/peripheral/gpio_define.svh
+32
View File
@@ -0,0 +1,32 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIBP_GPIO_DEF_SV
`define RIBP_GPIO_DEF_SV
// verilog_format: off
`define RIBP_GPIO_NUM 32
`define RIBP_GPIO_OE 8'h00 // rw
`define RIBP_GPIO_CS 8'h04 // rw
`define RIBP_GPIO_PU 8'h08 // rw
`define RIBP_GPIO_PD 8'h0C // rw
`define RIBP_GPIO_DO 8'h10 // rw
`define RIBP_GPIO_DI 8'h14 // ro
`define RIBP_GPIO_IEN 8'h18 // rw
`define RIBP_GPIO_ITYPE0 8'h1c // rw
`define RIBP_GPIO_ITYPE1 8'h20 // rw
`define RIBP_GPIO_ISTAT 8'h24 // ro
`define RIBP_GPIO_IOFCFG 8'h28 // rw
`define RIBP_GPIO_PINMUX 8'h2c // rw
`define RIBP_GPIO_USER_SEL 8'h30 // rw
`define RIBP_GPIO_USER_LOCK 8'h34 // rw1s
`define RIBP_GPIO_USER_STATUS 8'h38 // ro
// verilog_format: on
`endif
rtl/ip/rib/peripheral/pll_ctrl_if.sv → rtl/ip/ribp/peripheral/pll_ctrl_if.sv
View File
File renamed without changes.
rtl/ip/rib/peripheral/sysctrl.sv → rtl/ip/ribp/peripheral/sysctrl.sv
+86 -86
View File
@@ -25,7 +25,7 @@ interface sysctrl_if ();
logic [ 63:0] perf_mgmt_wait_i;
logic [ 63:0] perf_user_wait_i;
logic [ 63:0] perf_dma_wait_i;
logic [ 63:0] perf_rib_wait_i;
logic [ 63:0] perf_ribp_wait_i;
logic [ 63:0] perf_apb_wait_i;
logic [ 63:0] perf_sdram_wait_i;
logic [ 63:0] perf_psram_wait_i;
@@ -40,7 +40,7 @@ interface sysctrl_if ();
input perf_mgmt_wait_i,
input perf_user_wait_i,
input perf_dma_wait_i,
input perf_rib_wait_i,
input perf_ribp_wait_i,
input perf_apb_wait_i,
input perf_sdram_wait_i,
input perf_psram_wait_i,
@@ -54,7 +54,7 @@ interface sysctrl_if ();
);
endinterface
module rib_sysctrl (
module ribp_sysctrl (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
@@ -62,7 +62,7 @@ module rib_sysctrl (
input logic [31:0] fault_addr_i,
input logic [3:0] fault_wstrb_i,
input logic fault_reserved_i,
rib_if.slave rib,
ribp_if.slave ribp,
sysctrl_if.dut sysctrl,
pll_ctrl_if.sysctrl pll_ctrl
// verilog_format: on
@@ -99,10 +99,10 @@ module rib_sysctrl (
sysctrl_offset_t'(`SOC_SYSCTRL_PERF_DMA_WAIT_LO_OFFSET);
localparam sysctrl_offset_t SYSCTRL_PERF_DMA_WAIT_HI_OFFSET =
sysctrl_offset_t'(`SOC_SYSCTRL_PERF_DMA_WAIT_HI_OFFSET);
localparam sysctrl_offset_t SYSCTRL_PERF_RIB_WAIT_LO_OFFSET =
sysctrl_offset_t'(`SOC_SYSCTRL_PERF_RIB_WAIT_LO_OFFSET);
localparam sysctrl_offset_t SYSCTRL_PERF_RIB_WAIT_HI_OFFSET =
sysctrl_offset_t'(`SOC_SYSCTRL_PERF_RIB_WAIT_HI_OFFSET);
localparam sysctrl_offset_t SYSCTRL_PERF_RIBP_WAIT_LO_OFFSET =
sysctrl_offset_t'(`SOC_SYSCTRL_PERF_RIBP_WAIT_LO_OFFSET);
localparam sysctrl_offset_t SYSCTRL_PERF_RIBP_WAIT_HI_OFFSET =
sysctrl_offset_t'(`SOC_SYSCTRL_PERF_RIBP_WAIT_HI_OFFSET);
localparam sysctrl_offset_t SYSCTRL_PERF_APB_WAIT_LO_OFFSET =
sysctrl_offset_t'(`SOC_SYSCTRL_PERF_APB_WAIT_LO_OFFSET);
localparam sysctrl_offset_t SYSCTRL_PERF_APB_WAIT_HI_OFFSET =
@@ -120,10 +120,10 @@ module rib_sysctrl (
localparam sysctrl_offset_t SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET =
sysctrl_offset_t'(`SOC_SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET);
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_rdata_en;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
logic [`USER_CORESEL_WIDTH-1:0] s_sysctrl_coresel_d, s_sysctrl_coresel_q;
logic s_sysctrl_coresel_en;
@@ -163,16 +163,16 @@ module rib_sysctrl (
logic [63:0] s_perf_mgmt_wait_q;
logic [63:0] s_perf_user_wait_q;
logic [63:0] s_perf_dma_wait_q;
logic [63:0] s_perf_rib_wait_q;
logic [63:0] s_perf_ribp_wait_q;
logic [63:0] s_perf_apb_wait_q;
logic [63:0] s_perf_sdram_wait_q;
logic [63:0] s_perf_psram_wait_q;
logic [63:0] s_perf_flash_wait_q;
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.rdata = s_ribp_rdata_q;
assign sysctrl.ip_sel_o = s_sysctrl_ipsel_q;
assign sysctrl.core_sel_o = s_sysctrl_coresel_q;
@@ -184,11 +184,11 @@ module rib_sysctrl (
assign pll_ctrl.req_valid_o = s_pll_req_valid_q;
assign pll_ctrl.rsp_ready_o = 1'b1;
assign s_sysctrl_coresel_write_valid = rib.wdata[`USER_CORESEL_WIDTH-1:0] < `USER_CORE_COUNT;
assign s_sysctrl_coresel_en = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_CORESEL_OFFSET &&
rib.wstrb[0] && s_sysctrl_coresel_write_valid &&
assign s_sysctrl_coresel_write_valid = ribp.wdata[`USER_CORESEL_WIDTH-1:0] < `USER_CORE_COUNT;
assign s_sysctrl_coresel_en = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_CORESEL_OFFSET &&
ribp.wstrb[0] && s_sysctrl_coresel_write_valid &&
(&s_user_reset_q) && sysctrl.user_bus_idle_i && ~s_user_running_q;
assign s_sysctrl_coresel_d = rib.wdata[`USER_CORESEL_WIDTH-1:0];
assign s_sysctrl_coresel_d = ribp.wdata[`USER_CORESEL_WIDTH-1:0];
dffer #(`USER_CORESEL_WIDTH) u_sysctrl_coresel_dffer (
clk_i,
rst_n_i,
@@ -197,15 +197,15 @@ module rib_sysctrl (
s_sysctrl_coresel_q
);
assign s_user_reset_write_data = rib.wdata[`USER_CORE_COUNT-1:0];
assign s_user_reset_write_data = ribp.wdata[`USER_CORE_COUNT-1:0];
assign s_user_reset_write_legal = (&s_user_reset_write_data) ||
((s_sysctrl_coresel_q < `USER_CORE_COUNT) &&
((~s_user_reset_write_data) ==
({{(`USER_CORE_COUNT - 1){1'b0}}, 1'b1} << s_sysctrl_coresel_q)));
assign s_user_reset_en = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_USER_CORE_RESET_OFFSET &&
rib.wstrb[0];
assign s_user_config_error_clear = s_rib_wr_hdshk &&
rib.addr[7:0] == SYSCTRL_USER_CORE_STATUS_OFFSET && rib.wstrb[1] && rib.wdata[11];
assign s_user_reset_en = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_USER_CORE_RESET_OFFSET &&
ribp.wstrb[0];
assign s_user_config_error_clear = s_ribp_wr_hdshk &&
ribp.addr[7:0] == SYSCTRL_USER_CORE_STATUS_OFFSET && ribp.wstrb[1] && ribp.wdata[11];
always_comb begin
s_user_reset_d = s_user_reset_q;
@@ -215,7 +215,7 @@ module rib_sysctrl (
if (s_user_config_error_clear) begin
s_user_config_error_d = 1'b0;
end
if (s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_CORESEL_OFFSET && ~s_sysctrl_coresel_en) begin
if (s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_CORESEL_OFFSET && ~s_sysctrl_coresel_en) begin
s_user_config_error_d = 1'b1;
end
if (s_user_reset_en) begin
@@ -267,8 +267,8 @@ module rib_sysctrl (
s_user_config_error_q
);
assign s_sysctrl_ipsel_en = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_IPSEL_OFFSET;
assign s_sysctrl_ipsel_d = rib.wdata[`USER_IPSEL_WIDTH-1:0];
assign s_sysctrl_ipsel_en = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_IPSEL_OFFSET;
assign s_sysctrl_ipsel_d = ribp.wdata[`USER_IPSEL_WIDTH-1:0];
dffer #(`USER_IPSEL_WIDTH) u_sysctrl_ipsel_dffer (
clk_i,
rst_n_i,
@@ -277,8 +277,8 @@ module rib_sysctrl (
s_sysctrl_ipsel_q
);
assign s_pll_cfg_en = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_PLL_CFG_OFFSET && rib.wstrb[0];
assign s_pll_cfg_d = rib.wdata[2:0];
assign s_pll_cfg_en = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_PLL_CFG_OFFSET && ribp.wstrb[0];
assign s_pll_cfg_d = ribp.wdata[2:0];
dffer #(3) u_pll_cfg_dffer (
clk_i,
rst_n_i,
@@ -287,10 +287,10 @@ module rib_sysctrl (
s_pll_cfg_q
);
assign s_pll_apply = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_PLL_CMD_OFFSET &&
rib.wstrb[0] && rib.wdata[0];
assign s_pll_clear_error = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_PLL_CMD_OFFSET &&
rib.wstrb[0] && rib.wdata[1];
assign s_pll_apply = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_PLL_CMD_OFFSET &&
ribp.wstrb[0] && ribp.wdata[0];
assign s_pll_clear_error = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_PLL_CMD_OFFSET &&
ribp.wstrb[0] && ribp.wdata[1];
assign s_pll_rsp_accept = pll_ctrl.rsp_valid_i && pll_ctrl.rsp_ready_o;
always_comb begin
@@ -382,11 +382,11 @@ module rib_sysctrl (
s_pll_lock_q
);
assign s_perf_enable_en = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_PERF_CTRL_OFFSET &&
rib.wstrb[0];
assign s_perf_enable_d = rib.wdata[0];
assign s_perf_clear = s_perf_enable_en && rib.wdata[1];
assign s_perf_snapshot = s_perf_enable_en && rib.wdata[2];
assign s_perf_enable_en = s_ribp_wr_hdshk && ribp.addr[7:0] == SYSCTRL_PERF_CTRL_OFFSET &&
ribp.wstrb[0];
assign s_perf_enable_d = ribp.wdata[0];
assign s_perf_clear = s_perf_enable_en && ribp.wdata[1];
assign s_perf_snapshot = s_perf_enable_en && ribp.wdata[2];
dffer #(1) u_perf_enable_dffer (
clk_i,
rst_n_i,
@@ -415,12 +415,12 @@ module rib_sysctrl (
sysctrl.perf_dma_wait_i,
s_perf_dma_wait_q
);
dffer #(64) u_perf_rib_wait_dffer (
dffer #(64) u_perf_ribp_wait_dffer (
clk_i,
rst_n_i,
s_perf_snapshot,
sysctrl.perf_rib_wait_i,
s_perf_rib_wait_q
sysctrl.perf_ribp_wait_i,
s_perf_ribp_wait_q
);
dffer #(64) u_perf_apb_wait_dffer (
clk_i,
@@ -451,9 +451,9 @@ module rib_sysctrl (
s_perf_flash_wait_q
);
assign s_fault_status_clear = s_rib_wr_hdshk &&
rib.addr[7:0] == SYSCTRL_FAULT_STATUS_OFFSET &&
rib.wstrb[0] && rib.wdata[0];
assign s_fault_status_clear = s_ribp_wr_hdshk &&
ribp.addr[7:0] == SYSCTRL_FAULT_STATUS_OFFSET &&
ribp.wstrb[0] && ribp.wdata[0];
always_comb begin
s_fault_pending_d = s_fault_pending_q;
s_fault_write_d = s_fault_write_q;
@@ -534,26 +534,26 @@ module rib_sysctrl (
s_fault_master_q
);
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
dffr #(1) u_ribp_ready_dffr (
clk_i,
rst_n_i,
s_rib_ready_d,
s_rib_ready_q
s_ribp_ready_d,
s_ribp_ready_q
);
assign s_rib_rdata_en = s_rib_rd_hdshk;
assign s_ribp_rdata_en = s_ribp_rd_hdshk;
always_comb begin
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
s_ribp_rdata_d = s_ribp_rdata_q;
unique case (ribp.addr[7:0])
// verilog_format: off
SYSCTRL_CORESEL_OFFSET: s_rib_rdata_d = {{(32 - `USER_CORESEL_WIDTH) {1'b0}}, s_sysctrl_coresel_q};
SYSCTRL_IPSEL_OFFSET: s_rib_rdata_d = {{(32 - `USER_IPSEL_WIDTH) {1'b0}}, s_sysctrl_ipsel_q};
SYSCTRL_PLL_CFG_OFFSET: s_rib_rdata_d = {29'd0, s_pll_cfg_q};
SYSCTRL_FAULT_STATUS_OFFSET: s_rib_rdata_d = {27'd0, s_fault_reason_q, s_fault_write_q, s_fault_pending_q};
SYSCTRL_FAULT_ADDR_OFFSET: s_rib_rdata_d = s_fault_addr_q;
SYSCTRL_FAULT_COUNT_OFFSET: s_rib_rdata_d = s_fault_count_q;
SYSCTRL_PLL_STATUS_OFFSET: s_rib_rdata_d = {
SYSCTRL_CORESEL_OFFSET: s_ribp_rdata_d = {{(32 - `USER_CORESEL_WIDTH) {1'b0}}, s_sysctrl_coresel_q};
SYSCTRL_IPSEL_OFFSET: s_ribp_rdata_d = {{(32 - `USER_IPSEL_WIDTH) {1'b0}}, s_sysctrl_ipsel_q};
SYSCTRL_PLL_CFG_OFFSET: s_ribp_rdata_d = {29'd0, s_pll_cfg_q};
SYSCTRL_FAULT_STATUS_OFFSET: s_ribp_rdata_d = {27'd0, s_fault_reason_q, s_fault_write_q, s_fault_pending_q};
SYSCTRL_FAULT_ADDR_OFFSET: s_ribp_rdata_d = s_fault_addr_q;
SYSCTRL_FAULT_COUNT_OFFSET: s_ribp_rdata_d = s_fault_count_q;
SYSCTRL_PLL_STATUS_OFFSET: s_ribp_rdata_d = {
21'd0,
pll_ctrl.capable_i,
s_pll_lock_q,
@@ -564,8 +564,8 @@ module rib_sysctrl (
s_pll_active_valid_q,
s_pll_active_sel_q
};
SYSCTRL_USER_CORE_RESET_OFFSET: s_rib_rdata_d = {{(32 - `USER_CORE_COUNT) {1'b0}}, s_user_reset_q};
SYSCTRL_USER_CORE_STATUS_OFFSET: s_rib_rdata_d = {
SYSCTRL_USER_CORE_RESET_OFFSET: s_ribp_rdata_d = {{(32 - `USER_CORE_COUNT) {1'b0}}, s_user_reset_q};
SYSCTRL_USER_CORE_STATUS_OFFSET: s_ribp_rdata_d = {
20'd0,
s_user_config_error_q,
s_user_draining_q,
@@ -574,35 +574,35 @@ module rib_sysctrl (
{ (8 - `USER_CORESEL_WIDTH) {1'b0} },
s_sysctrl_coresel_q
};
SYSCTRL_FAULT_MASTER_OFFSET: s_rib_rdata_d = {30'd0, s_fault_master_q};
SYSCTRL_FAULT_DETAIL_OFFSET: s_rib_rdata_d = {29'd0, s_fault_detail_q};
SYSCTRL_PERF_CTRL_OFFSET: s_rib_rdata_d = {31'd0, s_perf_enable_q};
SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_mgmt_wait_q[31:0];
SYSCTRL_PERF_MGMT_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_mgmt_wait_q[63:32];
SYSCTRL_PERF_USER_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_user_wait_q[31:0];
SYSCTRL_PERF_USER_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_user_wait_q[63:32];
SYSCTRL_PERF_DMA_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_dma_wait_q[31:0];
SYSCTRL_PERF_DMA_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_dma_wait_q[63:32];
SYSCTRL_PERF_RIB_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_rib_wait_q[31:0];
SYSCTRL_PERF_RIB_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_rib_wait_q[63:32];
SYSCTRL_PERF_APB_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_apb_wait_q[31:0];
SYSCTRL_PERF_APB_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_apb_wait_q[63:32];
SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_sdram_wait_q[31:0];
SYSCTRL_PERF_SDRAM_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_sdram_wait_q[63:32];
SYSCTRL_PERF_PSRAM_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_psram_wait_q[31:0];
SYSCTRL_PERF_PSRAM_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_psram_wait_q[63:32];
SYSCTRL_PERF_FLASH_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_flash_wait_q[31:0];
SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_flash_wait_q[63:32];
default: s_rib_rdata_d = s_rib_rdata_q;
SYSCTRL_FAULT_MASTER_OFFSET: s_ribp_rdata_d = {30'd0, s_fault_master_q};
SYSCTRL_FAULT_DETAIL_OFFSET: s_ribp_rdata_d = {29'd0, s_fault_detail_q};
SYSCTRL_PERF_CTRL_OFFSET: s_ribp_rdata_d = {31'd0, s_perf_enable_q};
SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET: s_ribp_rdata_d = s_perf_mgmt_wait_q[31:0];
SYSCTRL_PERF_MGMT_WAIT_HI_OFFSET: s_ribp_rdata_d = s_perf_mgmt_wait_q[63:32];
SYSCTRL_PERF_USER_WAIT_LO_OFFSET: s_ribp_rdata_d = s_perf_user_wait_q[31:0];
SYSCTRL_PERF_USER_WAIT_HI_OFFSET: s_ribp_rdata_d = s_perf_user_wait_q[63:32];
SYSCTRL_PERF_DMA_WAIT_LO_OFFSET: s_ribp_rdata_d = s_perf_dma_wait_q[31:0];
SYSCTRL_PERF_DMA_WAIT_HI_OFFSET: s_ribp_rdata_d = s_perf_dma_wait_q[63:32];
SYSCTRL_PERF_RIBP_WAIT_LO_OFFSET: s_ribp_rdata_d = s_perf_ribp_wait_q[31:0];
SYSCTRL_PERF_RIBP_WAIT_HI_OFFSET: s_ribp_rdata_d = s_perf_ribp_wait_q[63:32];
SYSCTRL_PERF_APB_WAIT_LO_OFFSET: s_ribp_rdata_d = s_perf_apb_wait_q[31:0];
SYSCTRL_PERF_APB_WAIT_HI_OFFSET: s_ribp_rdata_d = s_perf_apb_wait_q[63:32];
SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET: s_ribp_rdata_d = s_perf_sdram_wait_q[31:0];
SYSCTRL_PERF_SDRAM_WAIT_HI_OFFSET: s_ribp_rdata_d = s_perf_sdram_wait_q[63:32];
SYSCTRL_PERF_PSRAM_WAIT_LO_OFFSET: s_ribp_rdata_d = s_perf_psram_wait_q[31:0];
SYSCTRL_PERF_PSRAM_WAIT_HI_OFFSET: s_ribp_rdata_d = s_perf_psram_wait_q[63:32];
SYSCTRL_PERF_FLASH_WAIT_LO_OFFSET: s_ribp_rdata_d = s_perf_flash_wait_q[31:0];
SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET: s_ribp_rdata_d = s_perf_flash_wait_q[63:32];
default: s_ribp_rdata_d = s_ribp_rdata_q;
endcase
// verilog_format: on
end
dffer #(32) u_rib_rdata_dffer (
dffer #(32) u_ribp_rdata_dffer (
clk_i,
rst_n_i,
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
s_ribp_rdata_en,
s_ribp_rdata_d,
s_ribp_rdata_q
);
endmodule
rtl/ip/rib/peripheral/timer.sv → rtl/ip/ribp/peripheral/timer.sv
+49 -49
View File
@@ -30,32 +30,32 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIB_TIMER_DEF_SV
`define RIB_TIMER_DEF_SV
`ifndef RIBP_TIMER_DEF_SV
`define RIBP_TIMER_DEF_SV
// verilog_format: off
`define RIB_TIMER_CFG 8'h00
`define RIB_TIMER_RLD 8'h04
`define RIB_TIMER_VAL 8'h08
`define RIBP_TIMER_CFG 8'h00
`define RIBP_TIMER_RLD 8'h04
`define RIBP_TIMER_VAL 8'h08
// verilog_format: on
`endif
module rib_timer (
module ribp_timer (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib,
ribp_if.slave ribp,
output logic irq_o
// verilog_format: on
);
// rib
// ribp
logic s_irq_d, s_irq_q;
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_rdata_en;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
// register
logic s_tim_cfg_en;
logic [3:0] s_tim_cfg_d, s_tim_cfg_q;
@@ -69,37 +69,37 @@ module rib_timer (
logic s_bit_en, s_bit_oneshot;
logic s_bit_updown, s_bit_irq_en;
// irq
assign irq_o = s_irq_q;
assign irq_o = s_irq_q;
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.rdata = s_ribp_rdata_q;
assign s_bit_en = s_tim_cfg_q[0];
assign s_bit_oneshot = s_tim_cfg_q[1];
assign s_bit_updown = s_tim_cfg_q[2];
assign s_bit_irq_en = s_tim_cfg_q[3];
assign s_bit_en = s_tim_cfg_q[0];
assign s_bit_oneshot = s_tim_cfg_q[1];
assign s_bit_updown = s_tim_cfg_q[2];
assign s_bit_irq_en = s_tim_cfg_q[3];
// register
assign s_tim_cfg_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_TIMER_CFG;
assign s_tim_cfg_d = rib.wdata[3:0];
assign s_tim_cfg_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_TIMER_CFG;
assign s_tim_cfg_d = ribp.wdata[3:0];
dffer #(4) u_tim_cfg_dffer (
clk_i,
rst_n_i,
s_tim_cfg_en && rib.wstrb[0],
s_tim_cfg_en && ribp.wstrb[0],
s_tim_cfg_d,
s_tim_cfg_q
);
assign s_tim_rld_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_TIMER_RLD;
assign s_tim_rld_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_TIMER_RLD;
always_comb begin
s_tim_rld_d = s_tim_rld_q;
if (rib.wstrb[0]) s_tim_rld_d[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_tim_rld_d[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_tim_rld_d[23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_tim_rld_d[31:24] = rib.wdata[31:24];
if (ribp.wstrb[0]) s_tim_rld_d[7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_tim_rld_d[15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_tim_rld_d[23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_tim_rld_d[31:24] = ribp.wdata[31:24];
end
dffer #(32) u_tim_rld_dffer (
clk_i,
@@ -113,11 +113,11 @@ module rib_timer (
always_comb begin
s_tim_val_d = s_tim_val_q;
s_irq_d = s_irq_q;
if (s_rib_wr_hdshk && rib.addr[7:0] == `RIB_TIMER_VAL) begin
if (rib.wstrb[0]) s_tim_val_d[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_tim_val_d[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_tim_val_d[23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_tim_val_d[31:24] = rib.wdata[31:24];
if (s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_TIMER_VAL) begin
if (ribp.wstrb[0]) s_tim_val_d[7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_tim_val_d[15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_tim_val_d[23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_tim_val_d[31:24] = ribp.wdata[31:24];
end else if (s_bit_en) begin
if (s_bit_updown) begin
if (s_tim_val_q == s_tim_rld_q) begin
@@ -153,30 +153,30 @@ module rib_timer (
);
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
dffr #(1) u_ribp_ready_dffr (
clk_i,
rst_n_i,
s_rib_ready_d,
s_rib_ready_q
s_ribp_ready_d,
s_ribp_ready_q
);
assign s_rib_rdata_en = s_rib_rd_hdshk;
assign s_ribp_rdata_en = s_ribp_rd_hdshk;
always_comb begin
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_TIMER_CFG: s_rib_rdata_d = {28'd0, s_tim_cfg_q};
`RIB_TIMER_RLD: s_rib_rdata_d = s_tim_rld_q;
`RIB_TIMER_VAL: s_rib_rdata_d = s_tim_val_q;
default: s_rib_rdata_d = s_rib_rdata_q;
s_ribp_rdata_d = s_ribp_rdata_q;
unique case (ribp.addr[7:0])
`RIBP_TIMER_CFG: s_ribp_rdata_d = {28'd0, s_tim_cfg_q};
`RIBP_TIMER_RLD: s_ribp_rdata_d = s_tim_rld_q;
`RIBP_TIMER_VAL: s_ribp_rdata_d = s_tim_val_q;
default: s_ribp_rdata_d = s_ribp_rdata_q;
endcase
end
dffer #(32) u_rib_rdata_dffer (
dffer #(32) u_ribp_rdata_dffer (
clk_i,
rst_n_i,
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
s_ribp_rdata_en,
s_ribp_rdata_d,
s_ribp_rdata_q
);
endmodule
rtl/ip/rib/serial/i2c.sv → rtl/ip/ribp/serial/i2c.sv
+54 -54
View File
@@ -8,35 +8,35 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIB_I2C_DEF_SV
`define RIB_I2C_DEF_SV
`ifndef RIBP_I2C_DEF_SV
`define RIBP_I2C_DEF_SV
// verilog_format: off
`define RIB_I2C_CLKDIV 8'h00
`define RIB_I2C_DEVADDR 8'h04
`define RIB_I2C_REGADDR 8'h08
`define RIB_I2C_TXDATA 8'h0C
`define RIB_I2C_RXDATA 8'h10
`define RIB_I2C_XFER 8'h14
`define RIB_I2C_CFG 8'h18
`define RIB_I2C_STATUS 8'h1C
`define RIBP_I2C_CLKDIV 8'h00
`define RIBP_I2C_DEVADDR 8'h04
`define RIBP_I2C_REGADDR 8'h08
`define RIBP_I2C_TXDATA 8'h0C
`define RIBP_I2C_RXDATA 8'h10
`define RIBP_I2C_XFER 8'h14
`define RIBP_I2C_CFG 8'h18
`define RIBP_I2C_STATUS 8'h1C
// verilog_format: on
`endif
module rib_i2c (
module ribp_i2c (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib,
ribp_if.slave ribp,
i2c_if.dut i2c
// verilog_format: on
);
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_rdata_en;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
//2^7=128
logic s_i2c_clkdiv_en;
@@ -63,14 +63,14 @@ module rib_i2c (
assign s_bit_start = s_i2c_xfer_q[1];
assign s_bit_extn_addr = s_i2c_cfg_q;
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.rdata = s_ribp_rdata_q;
assign s_i2c_clkdiv_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2C_CLKDIV;
assign s_i2c_clkdiv_d = rib.wdata[6:0];
assign s_i2c_clkdiv_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2C_CLKDIV;
assign s_i2c_clkdiv_d = ribp.wdata[6:0];
dffer #(7) u_i2c_clkdiv_dffer (
clk_i,
rst_n_i,
@@ -79,8 +79,8 @@ module rib_i2c (
s_i2c_clkdiv_q
);
assign s_i2c_devaddr_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2C_DEVADDR;
assign s_i2c_devaddr_d = rib.wdata[6:0];
assign s_i2c_devaddr_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2C_DEVADDR;
assign s_i2c_devaddr_d = ribp.wdata[6:0];
dffer #(7) u_i2c_devaddr_dffer (
clk_i,
rst_n_i,
@@ -90,11 +90,11 @@ module rib_i2c (
);
assign s_i2c_regaddr_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2C_REGADDR;
assign s_i2c_regaddr_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2C_REGADDR;
always_comb begin
s_i2c_regaddr_d = s_i2c_regaddr_q;
if (rib.wstrb[0]) s_i2c_regaddr_d[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_i2c_regaddr_d[15:8] = rib.wdata[15:8];
if (ribp.wstrb[0]) s_i2c_regaddr_d[7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_i2c_regaddr_d[15:8] = ribp.wdata[15:8];
end
dffer #(16) u_i2c_regaddr_dffer (
clk_i,
@@ -105,8 +105,8 @@ module rib_i2c (
);
assign s_i2c_txdata_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2C_TXDATA;
assign s_i2c_txdata_d = rib.wdata[7:0];
assign s_i2c_txdata_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2C_TXDATA;
assign s_i2c_txdata_d = ribp.wdata[7:0];
dffer #(8) u_i2c_txdata_dffer (
clk_i,
rst_n_i,
@@ -118,8 +118,8 @@ module rib_i2c (
always_comb begin
s_i2c_xfer_d = s_i2c_xfer_q;
if (s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2C_XFER) begin
s_i2c_xfer_d = rib.wdata[1:0];
if (s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2C_XFER) begin
s_i2c_xfer_d = ribp.wdata[1:0];
end else if (s_oper_clk_pos && (|s_i2c_xfer_q)) begin
s_i2c_xfer_d = '0;
end
@@ -132,8 +132,8 @@ module rib_i2c (
);
assign s_i2c_cfg_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2C_CFG;
assign s_i2c_cfg_d = rib.wdata[0];
assign s_i2c_cfg_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2C_CFG;
assign s_i2c_cfg_d = ribp.wdata[0];
dffer #(1) u_i2c_cfg_dffer (
clk_i,
rst_n_i,
@@ -152,7 +152,7 @@ module rib_i2c (
always_comb begin
s_i2c_status_d = s_i2c_status_q;
if (s_bit_end_re) s_i2c_status_d = 1'b1;
else if (s_rib_rd_hdshk && rib.addr[7:0] == `RIB_I2C_STATUS) begin
else if (s_ribp_rd_hdshk && ribp.addr[7:0] == `RIBP_I2C_STATUS) begin
s_i2c_status_d = 1'b0;
end
end
@@ -164,35 +164,35 @@ module rib_i2c (
);
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
dffr #(1) u_ribp_ready_dffr (
clk_i,
rst_n_i,
s_rib_ready_d,
s_rib_ready_q
s_ribp_ready_d,
s_ribp_ready_q
);
assign s_rib_rdata_en = s_rib_rd_hdshk;
assign s_ribp_rdata_en = s_ribp_rd_hdshk;
always_comb begin
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_I2C_CLKDIV: s_rib_rdata_d = {25'd0, s_i2c_clkdiv_q};
`RIB_I2C_DEVADDR: s_rib_rdata_d = {25'd0, s_i2c_devaddr_q};
`RIB_I2C_REGADDR: s_rib_rdata_d = {16'd0, s_i2c_regaddr_q};
`RIB_I2C_TXDATA: s_rib_rdata_d = {24'd0, s_i2c_txdata_q};
`RIB_I2C_RXDATA: s_rib_rdata_d = {24'd0, s_i2c_rxdata};
`RIB_I2C_XFER: s_rib_rdata_d = {30'd0, s_i2c_xfer_q};
`RIB_I2C_CFG: s_rib_rdata_d = {31'd0, s_i2c_cfg_q};
`RIB_I2C_STATUS: s_rib_rdata_d = {31'd0, s_i2c_status_q};
default: s_rib_rdata_d = s_rib_rdata_q;
s_ribp_rdata_d = s_ribp_rdata_q;
unique case (ribp.addr[7:0])
`RIBP_I2C_CLKDIV: s_ribp_rdata_d = {25'd0, s_i2c_clkdiv_q};
`RIBP_I2C_DEVADDR: s_ribp_rdata_d = {25'd0, s_i2c_devaddr_q};
`RIBP_I2C_REGADDR: s_ribp_rdata_d = {16'd0, s_i2c_regaddr_q};
`RIBP_I2C_TXDATA: s_ribp_rdata_d = {24'd0, s_i2c_txdata_q};
`RIBP_I2C_RXDATA: s_ribp_rdata_d = {24'd0, s_i2c_rxdata};
`RIBP_I2C_XFER: s_ribp_rdata_d = {30'd0, s_i2c_xfer_q};
`RIBP_I2C_CFG: s_ribp_rdata_d = {31'd0, s_i2c_cfg_q};
`RIBP_I2C_STATUS: s_ribp_rdata_d = {31'd0, s_i2c_status_q};
default: s_ribp_rdata_d = s_ribp_rdata_q;
endcase
end
dffer #(32) u_rib_rdata_dffer (
dffer #(32) u_ribp_rdata_dffer (
clk_i,
rst_n_i,
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
s_ribp_rdata_en,
s_ribp_rdata_d,
s_ribp_rdata_q
);
rtl/ip/rib/serial/i2c_core.sv → rtl/ip/ribp/serial/i2c_core.sv
View File
File renamed without changes.
rtl/ip/rib/serial/i2s.sv → rtl/ip/ribp/serial/i2s.sv
+3 -3
View File
@@ -29,7 +29,7 @@ interface i2s_if ();
endinterface
module rib_i2s (
module ribp_i2s (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
@@ -37,7 +37,7 @@ module rib_i2s (
input logic rst_aud_n_i,
output logic dma_tx_stall_o,
output logic dma_rx_stall_o,
rib_if.slave rib,
ribp_if.slave ribp,
i2s_if.dut i2s
// verilog_format: on
);
@@ -60,7 +60,7 @@ module rib_i2s (
i2s_reg u_i2s_reg (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.rib (rib),
.ribp (ribp),
.mode_o (s_i2s_mode),
.format_o (s_i2s_format),
.recven_o (s_i2s_recven),
rtl/ip/rib/serial/i2s_clkgen.sv → rtl/ip/ribp/serial/i2s_clkgen.sv
View File
File renamed without changes.
rtl/ip/rib/serial/i2s_core.sv → rtl/ip/ribp/serial/i2s_core.sv
View File
File renamed without changes.
rtl/ip/rib/serial/i2s_define.svh → rtl/ip/ribp/serial/i2s_define.svh
+10 -10
View File
@@ -8,18 +8,18 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIB_I2S_DEF_SV
`define RIB_I2S_DEF_SV
`ifndef RIBP_I2S_DEF_SV
`define RIBP_I2S_DEF_SV
// verilog_format: off
`define RIB_I2S_MODE 8'h00
`define RIB_I2S_FORMAT 8'h04
`define RIB_I2S_UPBOUND 8'h08
`define RIB_I2S_LOWBOUND 8'h0C
`define RIB_I2S_RECVEN 8'h10
`define RIB_I2S_TXDATA 8'h14
`define RIB_I2S_RXDATA 8'h18
`define RIB_I2S_STATUS 8'h1C
`define RIBP_I2S_MODE 8'h00
`define RIBP_I2S_FORMAT 8'h04
`define RIBP_I2S_UPBOUND 8'h08
`define RIBP_I2S_LOWBOUND 8'h0C
`define RIBP_I2S_RECVEN 8'h10
`define RIBP_I2S_TXDATA 8'h14
`define RIBP_I2S_RXDATA 8'h18
`define RIBP_I2S_STATUS 8'h1C
// verilog_format: on
`define I2S_16b_48K 2'd0
rtl/ip/rib/serial/i2s_recv.sv → rtl/ip/ribp/serial/i2s_recv.sv
View File
File renamed without changes.
rtl/ip/rib/serial/i2s_reg.sv → rtl/ip/ribp/serial/i2s_reg.sv
+50 -50
View File
@@ -14,7 +14,7 @@ module i2s_reg (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib,
ribp_if.slave ribp,
output logic mode_o,
output logic [ 1:0] format_o,
output logic recven_o,
@@ -31,11 +31,11 @@ module i2s_reg (
// verilog_format: on
);
// rib
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
// ribp
logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_rdata_en;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
// register
logic s_i2s_mode_en;
logic s_i2s_mode_d, s_i2s_mode_q;
@@ -53,22 +53,22 @@ module i2s_reg (
logic s_rx_fifo_stall_d, s_rx_fifo_stall_q;
// rib
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
// ribp
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.rdata = s_ribp_rdata_q;
// reg
assign mode_o = s_i2s_mode_q;
assign format_o = s_i2s_format_q;
assign recven_o = s_i2s_recven_q;
assign mode_o = s_i2s_mode_q;
assign format_o = s_i2s_format_q;
assign recven_o = s_i2s_recven_q;
// dma
assign dma_tx_stall_o = s_tx_fifo_stall_q;
assign dma_rx_stall_o = s_rx_fifo_stall_q;
assign dma_tx_stall_o = s_tx_fifo_stall_q;
assign dma_rx_stall_o = s_rx_fifo_stall_q;
assign s_i2s_mode_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2S_MODE;
assign s_i2s_mode_d = rib.wdata[0];
assign s_i2s_mode_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_MODE;
assign s_i2s_mode_d = ribp.wdata[0];
dffer #(1) u_i2s_mode_dffer (
clk_i,
rst_n_i,
@@ -78,8 +78,8 @@ module i2s_reg (
);
assign s_i2s_format_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2S_FORMAT;
assign s_i2s_format_d = rib.wdata[1:0];
assign s_i2s_format_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_FORMAT;
assign s_i2s_format_d = ribp.wdata[1:0];
dffer #(2) u_i2s_format_dffer (
clk_i,
rst_n_i,
@@ -89,8 +89,8 @@ module i2s_reg (
);
assign s_i2s_upbound_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2S_UPBOUND;
assign s_i2s_upbound_d = rib.wdata[7:0];
assign s_i2s_upbound_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_UPBOUND;
assign s_i2s_upbound_d = ribp.wdata[7:0];
dfferh #(8) u_i2s_upbound_dfferh (
clk_i,
rst_n_i,
@@ -100,8 +100,8 @@ module i2s_reg (
);
assign s_i2s_lowbound_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2S_LOWBOUND;
assign s_i2s_lowbound_d = rib.wdata[7:0];
assign s_i2s_lowbound_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_LOWBOUND;
assign s_i2s_lowbound_d = ribp.wdata[7:0];
dffer #(8) u_i2s_lowbound_dffer (
clk_i,
rst_n_i,
@@ -111,8 +111,8 @@ module i2s_reg (
);
assign s_i2s_recven_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2S_RECVEN;
assign s_i2s_recven_d = rib.wdata[0];
assign s_i2s_recven_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_RECVEN;
assign s_i2s_recven_d = ribp.wdata[0];
dffer #(1) u_i2s_recven_dffer (
clk_i,
rst_n_i,
@@ -158,12 +158,12 @@ module i2s_reg (
always_comb begin
tx_push_valid_o = 1'b0;
tx_push_data_o = '0;
if (s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2S_TXDATA) begin
if (s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_I2S_TXDATA) begin
tx_push_valid_o = 1'b1;
if (rib.wstrb[0]) tx_push_data_o[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) tx_push_data_o[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) tx_push_data_o[23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) tx_push_data_o[31:24] = rib.wdata[31:24];
if (ribp.wstrb[0]) tx_push_data_o[7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) tx_push_data_o[15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) tx_push_data_o[23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) tx_push_data_o[31:24] = ribp.wdata[31:24];
end
end
@@ -179,38 +179,38 @@ module i2s_reg (
s_i2s_status_q
);
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
dffr #(1) u_ribp_ready_dffr (
clk_i,
rst_n_i,
s_rib_ready_d,
s_rib_ready_q
s_ribp_ready_d,
s_ribp_ready_q
);
assign s_rib_rdata_en = s_rib_rd_hdshk;
assign s_ribp_rdata_en = s_ribp_rd_hdshk;
always_comb begin
rx_pop_valid_o = 1'b0;
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_I2S_MODE: s_rib_rdata_d = {31'd0, s_i2s_mode_q};
`RIB_I2S_FORMAT: s_rib_rdata_d = {30'd0, s_i2s_format_q};
`RIB_I2S_RXDATA: begin
if (s_rib_rd_hdshk) begin
s_ribp_rdata_d = s_ribp_rdata_q;
unique case (ribp.addr[7:0])
`RIBP_I2S_MODE: s_ribp_rdata_d = {31'd0, s_i2s_mode_q};
`RIBP_I2S_FORMAT: s_ribp_rdata_d = {30'd0, s_i2s_format_q};
`RIBP_I2S_RXDATA: begin
if (s_ribp_rd_hdshk) begin
rx_pop_valid_o = 1'b1;
if (!rx_empty_i) s_rib_rdata_d = rx_pop_data_i;
else s_rib_rdata_d = '0;
if (!rx_empty_i) s_ribp_rdata_d = rx_pop_data_i;
else s_ribp_rdata_d = '0;
end
end
`RIB_I2S_STATUS: s_rib_rdata_d = {30'd0, s_i2s_status_q};
default: s_rib_rdata_d = s_rib_rdata_q;
`RIBP_I2S_STATUS: s_ribp_rdata_d = {30'd0, s_i2s_status_q};
default: s_ribp_rdata_d = s_ribp_rdata_q;
endcase
end
dffer #(32) u_rib_rdata_dffer (
dffer #(32) u_ribp_rdata_dffer (
clk_i,
rst_n_i,
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
s_ribp_rdata_en,
s_ribp_rdata_d,
s_ribp_rdata_q
);
endmodule
rtl/ip/rib/serial/i2s_send.sv → rtl/ip/ribp/serial/i2s_send.sv
View File
File renamed without changes.
rtl/ip/rib/serial/onewire.sv → rtl/ip/ribp/serial/onewire.sv
+49 -49
View File
@@ -12,13 +12,13 @@
`define ONEWIRE_DEF_SV
// verilog_format: off
`define RIB_ONEWIRE_CLKDIV 8'h00
`define RIB_ONEWIRE_ZEROCNT 8'h04
`define RIB_ONEWIRE_ONECNT 8'h08
`define RIB_ONEWIRE_RSTCNT 8'h0C
`define RIB_ONEWIRE_TXDATA 8'h10
`define RIB_ONEWIRE_CTRL 8'h14
`define RIB_ONEWIRE_STATUS 8'h18
`define RIBP_ONEWIRE_CLKDIV 8'h00
`define RIBP_ONEWIRE_ZEROCNT 8'h04
`define RIBP_ONEWIRE_ONECNT 8'h08
`define RIBP_ONEWIRE_RSTCNT 8'h0C
`define RIBP_ONEWIRE_TXDATA 8'h10
`define RIBP_ONEWIRE_CTRL 8'h14
`define RIBP_ONEWIRE_STATUS 8'h18
// verilog_format: on
`endif
@@ -30,19 +30,19 @@ interface onewire_if ();
endinterface
// generate 1250ns for ws2812x only
module rib_onewire (
module ribp_onewire (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib,
ribp_if.slave ribp,
onewire_if.dut onewire
// verilog_format: on
);
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_rdata_en;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
logic s_onewire_clkdiv_en;
logic [7:0] s_onewire_clkdiv_d, s_onewire_clkdiv_q;
@@ -61,14 +61,14 @@ module rib_onewire (
logic s_done;
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.rdata = s_ribp_rdata_q;
assign s_onewire_clkdiv_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_ONEWIRE_CLKDIV;
assign s_onewire_clkdiv_d = rib.wdata[7:0];
assign s_onewire_clkdiv_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_ONEWIRE_CLKDIV;
assign s_onewire_clkdiv_d = ribp.wdata[7:0];
dffer #(8) u_onewire_clkdiv_dffer (
clk_i,
rst_n_i,
@@ -77,8 +77,8 @@ module rib_onewire (
s_onewire_clkdiv_q
);
assign s_onewire_zerocnt_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_ONEWIRE_ZEROCNT;
assign s_onewire_zerocnt_d = rib.wdata[7:0];
assign s_onewire_zerocnt_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_ONEWIRE_ZEROCNT;
assign s_onewire_zerocnt_d = ribp.wdata[7:0];
dffer #(8) u_onewire_zerocnt_dffer (
clk_i,
rst_n_i,
@@ -87,8 +87,8 @@ module rib_onewire (
s_onewire_zerocnt_q
);
assign s_onewire_onecnt_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_ONEWIRE_ONECNT;
assign s_onewire_onecnt_d = rib.wdata[7:0];
assign s_onewire_onecnt_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_ONEWIRE_ONECNT;
assign s_onewire_onecnt_d = ribp.wdata[7:0];
dffer #(8) u_onewire_onecnt_dffer (
clk_i,
rst_n_i,
@@ -97,8 +97,8 @@ module rib_onewire (
s_onewire_onecnt_q
);
assign s_onewire_rstcnt_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_ONEWIRE_RSTCNT;
assign s_onewire_rstcnt_d = rib.wdata[7:0];
assign s_onewire_rstcnt_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_ONEWIRE_RSTCNT;
assign s_onewire_rstcnt_d = ribp.wdata[7:0];
dffer #(8) u_onewire_rstcnt_dffer (
clk_i,
rst_n_i,
@@ -110,11 +110,11 @@ module rib_onewire (
always_comb begin
s_tx_push_valid = 1'b0;
s_tx_push_data = '0;
if (s_rib_wr_hdshk && rib.addr[7:0] == `RIB_ONEWIRE_TXDATA) begin
if (s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_ONEWIRE_TXDATA) begin
s_tx_push_valid = 1'b1;
if (rib.wstrb[0]) s_tx_push_data[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_tx_push_data[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_tx_push_data[23:16] = rib.wdata[23:16];
if (ribp.wstrb[0]) s_tx_push_data[7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_tx_push_data[15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_tx_push_data[23:16] = ribp.wdata[23:16];
end
end
@@ -138,8 +138,8 @@ module rib_onewire (
// [0] clear fifo [1] start
always_comb begin
if (s_rib_wr_hdshk && rib.addr[7:0] == `RIB_ONEWIRE_CTRL) begin
s_onewire_ctrl_d = rib.wdata[1:0];
if (s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_ONEWIRE_CTRL) begin
s_onewire_ctrl_d = ribp.wdata[1:0];
end else begin
s_onewire_ctrl_d = '0;
end
@@ -159,7 +159,7 @@ module rib_onewire (
s_onewire_status_d[2] = s_tx_empty;
if (s_done) begin
s_onewire_status_d[0] = 1'b1;
end else if (s_rib_rd_hdshk && rib.addr[7:0] == `RIB_ONEWIRE_STATUS) begin
end else if (s_ribp_rd_hdshk && ribp.addr[7:0] == `RIBP_ONEWIRE_STATUS) begin
s_onewire_status_d[0] = 1'b0;
end
end
@@ -170,32 +170,32 @@ module rib_onewire (
s_onewire_status_q
);
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
dffr #(1) u_ribp_ready_dffr (
clk_i,
rst_n_i,
s_rib_ready_d,
s_rib_ready_q
s_ribp_ready_d,
s_ribp_ready_q
);
assign s_rib_rdata_en = s_rib_rd_hdshk;
assign s_ribp_rdata_en = s_ribp_rd_hdshk;
always_comb begin
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_ONEWIRE_CLKDIV: s_rib_rdata_d = {24'd0, s_onewire_clkdiv_q};
`RIB_ONEWIRE_ZEROCNT: s_rib_rdata_d = {24'd0, s_onewire_zerocnt_q};
`RIB_ONEWIRE_ONECNT: s_rib_rdata_d = {24'd0, s_onewire_onecnt_q};
`RIB_ONEWIRE_RSTCNT: s_rib_rdata_d = {24'd0, s_onewire_rstcnt_q};
`RIB_ONEWIRE_STATUS: s_rib_rdata_d = {29'd0, s_onewire_status_q};
default: s_rib_rdata_d = s_rib_rdata_q;
s_ribp_rdata_d = s_ribp_rdata_q;
unique case (ribp.addr[7:0])
`RIBP_ONEWIRE_CLKDIV: s_ribp_rdata_d = {24'd0, s_onewire_clkdiv_q};
`RIBP_ONEWIRE_ZEROCNT: s_ribp_rdata_d = {24'd0, s_onewire_zerocnt_q};
`RIBP_ONEWIRE_ONECNT: s_ribp_rdata_d = {24'd0, s_onewire_onecnt_q};
`RIBP_ONEWIRE_RSTCNT: s_ribp_rdata_d = {24'd0, s_onewire_rstcnt_q};
`RIBP_ONEWIRE_STATUS: s_ribp_rdata_d = {29'd0, s_onewire_status_q};
default: s_ribp_rdata_d = s_ribp_rdata_q;
endcase
end
dffer #(32) u_rib_rdata_dffer (
dffer #(32) u_ribp_rdata_dffer (
clk_i,
rst_n_i,
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
s_ribp_rdata_en,
s_ribp_rdata_d,
s_ribp_rdata_q
);
onewire_core u_onewire_core (
rtl/ip/rib/serial/onewire_core.sv → rtl/ip/ribp/serial/onewire_core.sv
View File
File renamed without changes.
rtl/ip/rib/serial/uart.sv → rtl/ip/ribp/serial/uart.sv
+40 -40
View File
@@ -29,29 +29,29 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIB_UART_DEF_SV
`define RIB_UART_DEF_SV
`ifndef RIBP_UART_DEF_SV
`define RIBP_UART_DEF_SV
// verilog_format: off
`define RIB_UART_DIV 8'h00
`define RIB_UART_DAT 8'h04
`define RIBP_UART_DIV 8'h00
`define RIBP_UART_DAT 8'h04
// verilog_format: on
`endif
module rib_uart (
module ribp_uart (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib,
ribp_if.slave ribp,
uart_if.dut uart
// verilog_format: on
);
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_rdata_en;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
logic s_uart_div_en;
logic [31:0] s_uart_div_d, s_uart_div_q;
@@ -69,21 +69,21 @@ module rib_uart (
logic r_send_dummy;
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.rdata = s_ribp_rdata_q;
assign uart.tx_o = r_send_pattern[0];
assign uart.irq_o = r_recv_buf_valid;
assign uart.tx_o = r_send_pattern[0];
assign uart.irq_o = r_recv_buf_valid;
assign s_uart_div_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_UART_DIV;
assign s_uart_div_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_UART_DIV;
always_comb begin
s_uart_div_d = s_uart_div_q;
if (rib.wstrb[0]) s_uart_div_d[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_uart_div_d[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_uart_div_d[23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_uart_div_d[31:24] = rib.wdata[31:24];
if (ribp.wstrb[0]) s_uart_div_d[7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_uart_div_d[15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_uart_div_d[23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_uart_div_d[31:24] = ribp.wdata[31:24];
end
dfferh #(32) u_uart_div_dfferh (
clk_i,
@@ -93,31 +93,31 @@ module rib_uart (
s_uart_div_q
);
assign s_uart_dat_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_UART_DAT;
assign s_send_dat_wait = s_uart_dat_en && rib.wstrb[0] && ((|r_send_bitcnt) || r_send_dummy);
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q) && (~s_send_dat_wait);
dffr #(1) u_rib_ready_dffr (
assign s_uart_dat_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_UART_DAT;
assign s_send_dat_wait = s_uart_dat_en && ribp.wstrb[0] && ((|r_send_bitcnt) || r_send_dummy);
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q) && (~s_send_dat_wait);
dffr #(1) u_ribp_ready_dffr (
clk_i,
rst_n_i,
s_rib_ready_d,
s_rib_ready_q
s_ribp_ready_d,
s_ribp_ready_q
);
assign s_rib_rdata_en = s_rib_rd_hdshk;
assign s_ribp_rdata_en = s_ribp_rd_hdshk;
always_comb begin
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_UART_DIV: s_rib_rdata_d = s_uart_div_q;
`RIB_UART_DAT: s_rib_rdata_d = r_recv_buf_valid ? {24'd0, r_recv_buf_data} : '1;
default: s_rib_rdata_d = s_rib_rdata_q;
s_ribp_rdata_d = s_ribp_rdata_q;
unique case (ribp.addr[7:0])
`RIBP_UART_DIV: s_ribp_rdata_d = s_uart_div_q;
`RIBP_UART_DAT: s_ribp_rdata_d = r_recv_buf_valid ? {24'd0, r_recv_buf_data} : '1;
default: s_ribp_rdata_d = s_ribp_rdata_q;
endcase
end
dffer #(32) u_rib_rdata_dffer (
dffer #(32) u_ribp_rdata_dffer (
clk_i,
rst_n_i,
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
s_ribp_rdata_en,
s_ribp_rdata_d,
s_ribp_rdata_q
);
@@ -175,11 +175,11 @@ module rib_uart (
r_send_bitcnt <= 4'd15;
r_send_divcnt <= '0;
r_send_dummy <= '0;
end else if (s_uart_dat_en && rib.wstrb[0] && (~(|r_send_bitcnt))) begin
r_send_pattern <= {1'b1, rib.wdata[7:0], 1'b0};
end else if (s_uart_dat_en && ribp.wstrb[0] && (~(|r_send_bitcnt))) begin
r_send_pattern <= {1'b1, ribp.wdata[7:0], 1'b0};
`ifndef SYNTHESIS
`ifdef SIMU_VERILATOR
$write("%c", rib.wdata[7:0]); // NOTE: just for verilator sim
$write("%c", ribp.wdata[7:0]); // NOTE: just for verilator sim
`endif
`endif
r_send_bitcnt <= 4'd10;
rtl/ip/rib/storage/sdio.sv → rtl/ip/ribp/storage/sdio.sv
+5 -5
View File
@@ -31,20 +31,20 @@ interface sdio_if ();
endinterface
module rib_sdio (
module ribp_sdio (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib,
ribp_if.slave ribp,
sdio_if.dut sdio
// verilog_format: on
);
wire dummy0 = clk_i;
wire dummy1 = rst_n_i;
// rib
assign rib.rdata = '0;
assign rib.ready = '0;
// ribp
assign ribp.rdata = '0;
assign ribp.ready = '0;
// sdio
assign sdio.sck_o = '0;
assign sdio.cmd_oe_o = '0;
rtl/ip/rib/storage/spisd.sv → rtl/ip/ribp/storage/spisd.sv
+28 -28
View File
@@ -14,11 +14,11 @@
`include "mmap_define.svh"
module rib_spisd (
module ribp_spisd (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib,
ribp_if.slave ribp,
spi_if.dut spi
// verilog_format: on
);
@@ -40,25 +40,25 @@ module rib_spisd (
logic [ 7:0] s_sd_wr_data;
logic s_sd_wr_busy;
rib_if u_cfg_rib_if ();
rib_if u_cache_rib_if ();
rib_if u_cache_mem_rib_if ();
rib_if u_cache_byp_rib_if ();
ribp_if u_cfg_ribp_if ();
ribp_if u_cache_ribp_if ();
ribp_if u_cache_mem_ribp_if ();
ribp_if u_cache_byp_ribp_if ();
// verilog_format: off
assign s_cfg_reg_sel = `SOC_ADDR_IS_RIB_SPISD(rib.addr);
assign u_cfg_rib_if.valid = rib.valid && s_cfg_reg_sel;
assign u_cfg_rib_if.addr = rib.addr;
assign u_cfg_rib_if.wdata = rib.wdata;
assign u_cfg_rib_if.wstrb = rib.wstrb;
assign s_cfg_reg_sel = `SOC_ADDR_IS_RIBP_SPISD(ribp.addr);
assign u_cfg_ribp_if.valid = ribp.valid && s_cfg_reg_sel;
assign u_cfg_ribp_if.addr = ribp.addr;
assign u_cfg_ribp_if.wdata = ribp.wdata;
assign u_cfg_ribp_if.wstrb = ribp.wstrb;
assign u_cache_mem_rib_if.valid = rib.valid && (~s_cfg_reg_sel);
assign u_cache_mem_rib_if.addr = rib.addr;
assign u_cache_mem_rib_if.wdata = rib.wdata;
assign u_cache_mem_rib_if.wstrb = rib.wstrb;
assign u_cache_mem_ribp_if.valid = ribp.valid && (~s_cfg_reg_sel);
assign u_cache_mem_ribp_if.addr = ribp.addr;
assign u_cache_mem_ribp_if.wdata = ribp.wdata;
assign u_cache_mem_ribp_if.wstrb = ribp.wstrb;
assign rib.ready = s_cfg_reg_sel ? u_cfg_rib_if.ready : u_cache_mem_rib_if.ready;
assign rib.rdata = s_cfg_reg_sel ? u_cfg_rib_if.rdata : u_cache_mem_rib_if.rdata;
assign ribp.ready = s_cfg_reg_sel ? u_cfg_ribp_if.ready : u_cache_mem_ribp_if.ready;
assign ribp.rdata = s_cfg_reg_sel ? u_cfg_ribp_if.rdata : u_cache_mem_ribp_if.rdata;
// verilog_format: on
spisd_reg u_spisd_reg (
@@ -69,20 +69,20 @@ module rib_spisd (
.wr_sync_done_i(s_wr_sync_done),
.mode_o (s_mode),
.clkdiv_o (s_clkdiv),
.rib (u_cfg_rib_if),
.byp_rib (u_cache_byp_rib_if)
.ribp (u_cfg_ribp_if),
.byp_rib (u_cache_byp_ribp_if)
);
assign u_cache_rib_if.valid = s_mode ? u_cache_byp_rib_if.valid : u_cache_mem_rib_if.valid;
assign u_cache_rib_if.addr = s_mode ? u_cache_byp_rib_if.addr : u_cache_mem_rib_if.addr;
assign u_cache_rib_if.wdata = s_mode ? u_cache_byp_rib_if.wdata : u_cache_mem_rib_if.wdata;
assign u_cache_rib_if.wstrb = s_mode ? u_cache_byp_rib_if.wstrb : u_cache_mem_rib_if.wstrb;
assign u_cache_ribp_if.valid = s_mode ? u_cache_byp_ribp_if.valid : u_cache_mem_ribp_if.valid;
assign u_cache_ribp_if.addr = s_mode ? u_cache_byp_ribp_if.addr : u_cache_mem_ribp_if.addr;
assign u_cache_ribp_if.wdata = s_mode ? u_cache_byp_ribp_if.wdata : u_cache_mem_ribp_if.wdata;
assign u_cache_ribp_if.wstrb = s_mode ? u_cache_byp_ribp_if.wstrb : u_cache_mem_ribp_if.wstrb;
assign u_cache_byp_rib_if.ready = s_mode ? u_cache_rib_if.ready : '0;
assign u_cache_byp_rib_if.rdata = s_mode ? u_cache_rib_if.rdata : '0;
assign u_cache_mem_rib_if.ready = ~s_mode ? u_cache_rib_if.ready : '0;
assign u_cache_mem_rib_if.rdata = ~s_mode ? u_cache_rib_if.rdata : '0;
assign u_cache_byp_ribp_if.ready = s_mode ? u_cache_ribp_if.ready : '0;
assign u_cache_byp_ribp_if.rdata = s_mode ? u_cache_ribp_if.rdata : '0;
assign u_cache_mem_ribp_if.ready = ~s_mode ? u_cache_ribp_if.ready : '0;
assign u_cache_mem_ribp_if.rdata = ~s_mode ? u_cache_ribp_if.rdata : '0;
spisd_cache u_spisd_cache (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
@@ -100,7 +100,7 @@ module rib_spisd (
.sd_wr_data_req_i(s_sd_wr_data_req),
.sd_wr_data_o (s_sd_wr_data),
.sd_wr_busy_i (s_sd_wr_busy),
.rib (u_cache_rib_if)
.ribp (u_cache_ribp_if)
);
assign spi.irq_o = 1'b0; // TODO:
rtl/ip/rib/storage/spisd_cache.sv → rtl/ip/ribp/storage/spisd_cache.sv
+18 -18
View File
@@ -26,7 +26,7 @@ module spisd_cache (
input logic sd_wr_data_req_i,
output logic [7:0] sd_wr_data_o,
input logic sd_wr_busy_i,
rib_if.slave rib
ribp_if.slave ribp
// verilog_format: on
);
@@ -56,11 +56,11 @@ module spisd_cache (
// io
assign sd_wr_data_o = s_sd_wr_data_q;
assign rib.rdata = s_cache_data_q[s_cache_index];
assign ribp.rdata = s_cache_data_q[s_cache_index];
// cache
assign s_cache_index = rib.addr[8:2];
assign s_cache_mem_hit = ~mode_i && (rib.addr[27:9] == s_cache_tag_q[18:0]);
assign s_cache_byp_hit = mode_i && (rib.addr == s_cache_tag_q);
assign s_cache_index = ribp.addr[8:2];
assign s_cache_mem_hit = ~mode_i && (ribp.addr[27:9] == s_cache_tag_q[18:0]);
assign s_cache_byp_hit = mode_i && (ribp.addr == s_cache_tag_q);
always_comb begin
// cache
@@ -79,13 +79,13 @@ module spisd_cache (
s_sd_wr_data_d = s_sd_wr_data_q;
sd_addr_o = '0;
// mem_if
rib.ready = '0;
ribp.ready = '0;
// wr sync
wr_sync_done_o = '0;
unique case (s_cache_fsm_q)
FSM_IDLE: begin
if (init_done_i) begin
if (rib.valid) s_cache_fsm_d = FSM_COMP_TAG;
if (ribp.valid) s_cache_fsm_d = FSM_COMP_TAG;
// sw wr sync
else if (wr_sync_i && s_cache_dirty_q) begin
s_cache_fsm_d = FSM_WR_BACK;
@@ -98,26 +98,26 @@ module spisd_cache (
if ((s_cache_mem_hit || s_cache_byp_hit) && s_cache_valid_q) begin
if (s_wr_sync_q) wr_sync_done_o = 1'b1; // wr sync oper
else begin
rib.ready = 1'b1; // nomral oper
ribp.ready = 1'b1; // nomral oper
// write oper, set dirty
if (|rib.wstrb) begin
if (|ribp.wstrb) begin
s_cache_dirty_d = 1'b1;
if (rib.wstrb[0]) s_cache_data_d[s_cache_index][7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_cache_data_d[s_cache_index][15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_cache_data_d[s_cache_index][23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_cache_data_d[s_cache_index][31:24] = rib.wdata[31:24];
if (ribp.wstrb[0]) s_cache_data_d[s_cache_index][7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_cache_data_d[s_cache_index][15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_cache_data_d[s_cache_index][23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_cache_data_d[s_cache_index][31:24] = ribp.wdata[31:24];
end
end
s_cache_fsm_d = FSM_IDLE;
end else begin
// need to update tag line info
s_cache_valid_d = 1'b1;
s_cache_dirty_d = |rib.wstrb;
s_cache_dirty_d = |ribp.wstrb;
// tag line is clean
if (s_cache_valid_q == 1'b0 || s_cache_dirty_q == 1'b0) begin
s_cache_fsm_d = FSM_ALLOC;
if (~mode_i) s_cache_tag_d = {13'd0, rib.addr[27:9]};
else s_cache_tag_d = rib.addr;
if (~mode_i) s_cache_tag_d = {13'd0, ribp.addr[27:9]};
else s_cache_tag_d = ribp.addr;
end else begin
// need to flush data into sd card sectors
s_cache_fsm_d = FSM_WR_BACK;
@@ -159,8 +159,8 @@ module spisd_cache (
s_word_data_d = s_cache_data_q[s_line_cnt_d];
if (s_line_cnt_q == 7'd127) begin
s_cache_fsm_d = FSM_ALLOC;
if (~mode_i) s_cache_tag_d = {13'd0, rib.addr[27:9]};
else s_cache_tag_d = rib.addr;
if (~mode_i) s_cache_tag_d = {13'd0, ribp.addr[27:9]};
else s_cache_tag_d = ribp.addr;
end
end else begin
s_word_cnt_d = s_word_cnt_q + 1'b1;
rtl/ip/rib/storage/spisd_core.sv → rtl/ip/ribp/storage/spisd_core.sv
View File
File renamed without changes.
rtl/ip/rib/storage/spisd_data.sv → rtl/ip/ribp/storage/spisd_data.sv
View File
File renamed without changes.
rtl/ip/rib/storage/spisd_init.sv → rtl/ip/ribp/storage/spisd_init.sv
View File
File renamed without changes.
rtl/ip/rib/storage/spisd_read.sv → rtl/ip/ribp/storage/spisd_read.sv
View File
File renamed without changes.
rtl/ip/ribp/storage/spisd_reg.sv
+157
View File
@@ -0,0 +1,157 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIBP_SPISD_DEF_SV
`define RIBP_SPISD_DEF_SV
// verilog_format: off
`define RIBP_SPISD_MODE 8'h00
`define RIBP_SPISD_CLKDIV 8'h04
`define RIBP_SPISD_ADDR 8'h08
`define RIBP_SPISD_TXDATA 8'h0C
`define RIBP_SPISD_RXDATA 8'h10
`define RIBP_SPISD_STATUS 8'h14
`define RIBP_SPISD_SYNC 8'h18
// verilog_format: on
`endif
module spisd_reg (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
input logic init_done_i,
output logic wr_sync_o,
input logic wr_sync_done_i,
output logic mode_o,
output logic [1:0] clkdiv_o,
ribp_if.slave ribp,
ribp_if.master byp_rib
// verilog_format: on
);
// ribp
logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_rdata_en;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
// reg
logic s_spisd_mode_en;
logic s_spisd_mode_d, s_spisd_mode_q;
logic s_spisd_clkdiv_en;
logic [1:0] s_spisd_clkdiv_d, s_spisd_clkdiv_q;
logic s_spisd_addr_en;
logic [31:0] s_spisd_addr_d, s_spisd_addr_q;
logic [1:0] s_spisd_status_d, s_spisd_status_q;
// common
logic s_wr_byp, s_rd_byp;
// ribp
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign s_wr_byp = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SPISD_TXDATA;
assign s_rd_byp = s_ribp_rd_hdshk && ribp.addr[7:0] == `RIBP_SPISD_RXDATA;
assign ribp.ready = (s_wr_byp || s_rd_byp) ? byp_rib.ready : s_ribp_ready_q;
assign ribp.rdata = (s_wr_byp || s_rd_byp) ? byp_rib.rdata : s_ribp_rdata_q;
// common
assign mode_o = s_spisd_mode_q;
assign clkdiv_o = s_spisd_clkdiv_q;
// byp
assign byp_rib.valid = s_wr_byp || s_rd_byp;
assign byp_rib.addr = s_spisd_addr_q;
assign byp_rib.wdata = ribp.wdata;
assign byp_rib.wstrb = ribp.wstrb;
assign s_spisd_mode_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SPISD_MODE;
assign s_spisd_mode_d = ribp.wdata[0];
dffer #(1) u_spisd_mode_dffer (
clk_i,
rst_n_i,
s_spisd_mode_en,
s_spisd_mode_d,
s_spisd_mode_q
);
assign s_spisd_clkdiv_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SPISD_CLKDIV;
assign s_spisd_clkdiv_d = ribp.wdata[1:0];
dffer #(2) u_spisd_clkdiv_dffer (
clk_i,
rst_n_i,
s_spisd_clkdiv_en,
s_spisd_clkdiv_d,
s_spisd_clkdiv_q
);
assign s_spisd_addr_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SPISD_ADDR;
always_comb begin
s_spisd_addr_d = s_spisd_addr_q;
if (ribp.wstrb[0]) s_spisd_addr_d[7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_spisd_addr_d[15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_spisd_addr_d[23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_spisd_addr_d[31:24] = ribp.wdata[31:24];
end
dffer #(32) u_spisd_addr_dffer (
clk_i,
rst_n_i,
s_spisd_addr_en,
s_spisd_addr_d,
s_spisd_addr_q
);
// 0: init done
// 1: wr sync done
always_comb begin
s_spisd_status_d = s_spisd_status_q;
s_spisd_status_d[0] = init_done_i;
if (wr_sync_done_i && ~s_spisd_status_q[1]) begin
s_spisd_status_d[1] = 1'b1;
end else if (s_spisd_status_q[1] && s_ribp_rd_hdshk && ribp.addr[7:0] == `RIBP_SPISD_STATUS) begin
s_spisd_status_d[1] = 1'b0;
end
end
dffr #(2) u_spisd_status_dffr (
clk_i,
rst_n_i,
s_spisd_status_d,
s_spisd_status_q
);
// software wr sync
assign wr_sync_o = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_SPISD_SYNC;
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
dffr #(1) u_ribp_ready_dffr (
clk_i,
rst_n_i,
s_ribp_ready_d,
s_ribp_ready_q
);
assign s_ribp_rdata_en = s_ribp_rd_hdshk;
always_comb begin
s_ribp_rdata_d = s_ribp_rdata_q;
unique case (ribp.addr[7:0])
`RIBP_SPISD_MODE: s_ribp_rdata_d = {31'd0, s_spisd_mode_q};
`RIBP_SPISD_CLKDIV: s_ribp_rdata_d = {30'd0, s_spisd_clkdiv_q};
`RIBP_SPISD_ADDR: s_ribp_rdata_d = s_spisd_addr_q;
`RIBP_SPISD_STATUS: s_ribp_rdata_d = {30'd0, s_spisd_status_q};
default: s_ribp_rdata_d = s_ribp_rdata_q;
endcase
end
dffer #(32) u_ribp_rdata_dffer (
clk_i,
rst_n_i,
s_ribp_rdata_en,
s_ribp_rdata_d,
s_ribp_rdata_q
);
endmodule
rtl/ip/rib/storage/spisd_write.sv → rtl/ip/ribp/storage/spisd_write.sv
View File
File renamed without changes.
rtl/ip/rib/storage/xpi.sv → rtl/ip/ribp/storage/xpi.sv
+24 -24
View File
@@ -29,14 +29,14 @@ interface xpi_if ();
);
endinterface
module rib_xpi (
module ribp_xpi (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
input logic dma_xfer_done_i,
output logic dma_tx_stall_o,
output logic dma_rx_stall_o,
rib_if.slave rib,
ribp_if.slave ribp,
xpi_if.dut xpi
// verilog_format: on
);
@@ -102,28 +102,28 @@ module rib_xpi (
// ctrl
logic s_reg_xfer_start, s_xfer_done;
// interface
rib_if u_reg_rib_if ();
rib_if u_mm_rib_if ();
ribp_if u_reg_ribp_if ();
ribp_if u_mm_ribp_if ();
// rib mux
assign s_xpi_mm_sel = `SOC_ADDR_IS_FLASH(rib.addr) || `SOC_ADDR_IS_XPI(rib.addr);
assign u_reg_rib_if.valid = rib.valid && (~s_xpi_mm_sel);
assign u_reg_rib_if.addr = rib.addr;
assign u_reg_rib_if.wdata = rib.wdata;
assign u_reg_rib_if.wstrb = rib.wstrb;
// ribp mux
assign s_xpi_mm_sel = `SOC_ADDR_IS_FLASH(ribp.addr) || `SOC_ADDR_IS_XPI(ribp.addr);
assign u_reg_ribp_if.valid = ribp.valid && (~s_xpi_mm_sel);
assign u_reg_ribp_if.addr = ribp.addr;
assign u_reg_ribp_if.wdata = ribp.wdata;
assign u_reg_ribp_if.wstrb = ribp.wstrb;
assign u_mm_rib_if.valid = rib.valid && s_xpi_mm_sel;
assign u_mm_rib_if.addr = rib.addr;
assign u_mm_rib_if.wdata = rib.wdata;
assign u_mm_rib_if.wstrb = rib.wstrb;
assign u_mm_ribp_if.valid = ribp.valid && s_xpi_mm_sel;
assign u_mm_ribp_if.addr = ribp.addr;
assign u_mm_ribp_if.wdata = ribp.wdata;
assign u_mm_ribp_if.wstrb = ribp.wstrb;
// verilog_format: off
assign rib.ready = (u_reg_rib_if.valid & u_reg_rib_if.ready) |
(u_mm_rib_if.valid & u_mm_rib_if.ready);
assign ribp.ready = (u_reg_ribp_if.valid & u_reg_ribp_if.ready) |
(u_mm_ribp_if.valid & u_mm_ribp_if.ready);
assign rib.rdata = ({32{(u_reg_rib_if.valid & u_reg_rib_if.ready)}} & u_reg_rib_if.rdata) |
({32{(u_mm_rib_if.valid & u_mm_rib_if.ready)}} & u_mm_rib_if.rdata);
assign ribp.rdata = ({32{(u_reg_ribp_if.valid & u_reg_ribp_if.ready)}} & u_reg_ribp_if.rdata) |
({32{(u_mm_ribp_if.valid & u_mm_ribp_if.ready)}} & u_mm_ribp_if.rdata);
// verilog_format: on
// reg/mm mode nss
@@ -181,7 +181,7 @@ module rib_xpi (
// dma
.dma_tx_stall_o (dma_tx_stall_o),
.dma_rx_stall_o (dma_rx_stall_o),
.rib (u_reg_rib_if)
.ribp (u_reg_ribp_if)
);
@@ -206,7 +206,7 @@ module rib_xpi (
.rx_pop_ready_i (s_rx_pop_ready),
// ctrl
.xfer_done_i (s_xfer_done),
.rib (u_mm_rib_if)
.ribp (u_mm_ribp_if)
);
@@ -255,7 +255,7 @@ module rib_xpi (
.nss_i(s_xpi_nss),
.mode_i(s_xpi_mode[s_xpi_nss]),
.clkdiv_i(s_xpi_clkdiv[s_xpi_nss]),
.rdwr_i(u_mm_rib_if.valid ? s_xpi_mm_rdwr : s_xpi_rdwr[s_xpi_nss]),
.rdwr_i(u_mm_ribp_if.valid ? s_xpi_mm_rdwr : s_xpi_rdwr[s_xpi_nss]),
.revdat_i(s_xpi_revdat[s_xpi_nss]),
.cmdtyp_i(s_xpi_cmdtyp[s_xpi_nss]),
.cmdlen_i(s_xpi_cmdlen[s_xpi_nss]),
@@ -263,12 +263,12 @@ module rib_xpi (
.adrtyp_i(s_xpi_adrtyp[s_xpi_nss]),
.adrlen_i(s_xpi_adrlen[s_xpi_nss]),
// HACK:
.adrdat_i(u_mm_rib_if.valid ? {s_xpi_mm_addr[23:0], 8'hF0} : s_xpi_adrdat[s_xpi_nss]),
.adrdat_i(u_mm_ribp_if.valid ? {s_xpi_mm_addr[23:0], 8'hF0} : s_xpi_adrdat[s_xpi_nss]),
.tdulen_i(s_xpi_tdulen[s_xpi_nss]),
.rdulen_i(s_xpi_rdulen[s_xpi_nss]),
.dattyp_i(s_xpi_dattyp[s_xpi_nss]),
.datlen_i(s_xpi_datlen[s_xpi_nss]), // NOTE:
.datbit_i(u_mm_rib_if.valid ? s_xpi_mm_xfer_byte : s_xpi_datbit[s_xpi_nss]),
.datbit_i(u_mm_ribp_if.valid ? s_xpi_mm_xfer_byte : s_xpi_datbit[s_xpi_nss]),
.hlvlen_i(s_xpi_hlvlen[s_xpi_nss]),
.tx_data_req_o(s_tx_pop_valid),
.tx_data_rdy_i(s_tx_pop_ready),
@@ -276,7 +276,7 @@ module rib_xpi (
.rx_data_req_o(s_rx_push_valid),
.rx_data_rdy_i(s_rx_push_ready),
.rx_data_o(s_rx_push_data),
.start_i(u_mm_rib_if.valid ? s_xpi_mm_req : s_reg_xfer_start),
.start_i(u_mm_ribp_if.valid ? s_xpi_mm_req : s_reg_xfer_start),
.done_o(s_xfer_done),
.tx_elem_num_i(s_tx_elem_num[7:0]),
.dma_xfer_done_i(dma_xfer_done_i),
rtl/ip/rib/storage/xpi_clkgen.sv → rtl/ip/ribp/storage/xpi_clkgen.sv
View File
File renamed without changes.
rtl/ip/rib/storage/xpi_core.sv → rtl/ip/ribp/storage/xpi_core.sv
View File
File renamed without changes.
rtl/ip/ribp/storage/xpi_define.svh
+58
View File
@@ -0,0 +1,58 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIBP_XPI_DEF_SV
`define RIBP_XPI_DEF_SV
// verilog_format: off
`define RIBP_XPI_CFGIDX 8'h00
`define RIBP_XPI_ACCMD 8'h04
`define RIBP_XPI_MMSTAD 8'h08
`define RIBP_XPI_MMOFFST 8'h0C
`define RIBP_XPI_MODE 8'h10
`define RIBP_XPI_NSS 8'h14
`define RIBP_XPI_CLKDIV 8'h18
`define RIBP_XPI_RDWR 8'h1C
`define RIBP_XPI_REVDAT 8'h20
`define RIBP_XPI_TXUPB 8'h24
`define RIBP_XPI_TXLOWB 8'h28
`define RIBP_XPI_RXUPB 8'h2C
`define RIBP_XPI_RXLOWB 8'h30
`define RIBP_XPI_FLUSH 8'h34
`define RIBP_XPI_CMDTYP 8'h38
`define RIBP_XPI_CMDLEN 8'h3C
`define RIBP_XPI_CMDDAT 8'h40
`define RIBP_XPI_ADRTYP 8'h44
`define RIBP_XPI_ADRLEN 8'h48
`define RIBP_XPI_ADRDAT 8'h4C
`define RIBP_XPI_ALTTYP 8'h50
`define RIBP_XPI_ALTLEN 8'h54
`define RIBP_XPI_ALTDAT 8'h58
`define RIBP_XPI_TDULEN 8'h5C
`define RIBP_XPI_RDULEN 8'h60
`define RIBP_XPI_DATTYP 8'h64
`define RIBP_XPI_DATLEN 8'h68
`define RIBP_XPI_DATBIT 8'h6C
`define RIBP_XPI_HLVLEN 8'h70
`define RIBP_XPI_TXDATA 8'h74
`define RIBP_XPI_RXDATA 8'h78
`define RIBP_XPI_XST 8'h7C
`define RIBP_XPI_STATUS 8'h80
`define XPI_TYPE_NONE 2'd0
`define XPI_TYPE_SNGL 2'd1
`define XPI_TYPE_DUAL 2'd2
`define XPI_TYPE_QUAD 2'd3
`define XPI_NSS_NUM 4
`define XPI_LNS_NUM $clog2(`XPI_NSS_NUM)
// verilog_format: on
`endif
rtl/ip/rib/storage/xpi_mm.sv → rtl/ip/ribp/storage/xpi_mm.sv
+33 -33
View File
@@ -32,7 +32,7 @@ module xpi_mm (
input logic rx_pop_ready_i,
// ctrl
input logic xfer_done_i,
rib_if.slave rib
ribp_if.slave ribp
// verilog_format: on
);
// verilog_format: off
@@ -43,11 +43,11 @@ module xpi_mm (
localparam FSM_RD = 3'd4;
// verilog_format: on
// rib
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
// ribp
logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_rdata_en;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
// ctrl
logic r_rd_st;
logic r_wr_st;
@@ -62,34 +62,34 @@ module xpi_mm (
logic s_mem_valid_re;
logic [`XPI_LNS_NUM-1:0] s_nss_d, s_nss_q;
// rib
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
// rib rd
// ribp
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.rdata = s_ribp_rdata_q;
// ribp rd
always_comb begin
if (s_rib_rd_hdshk) s_rib_ready_d = rx_pop_ready_i;
else if (s_rib_wr_hdshk) s_rib_ready_d = xfer_done_i;
else s_rib_ready_d = 1'b0;
if (s_ribp_rd_hdshk) s_ribp_ready_d = rx_pop_ready_i;
else if (s_ribp_wr_hdshk) s_ribp_ready_d = xfer_done_i;
else s_ribp_ready_d = 1'b0;
end
dffr #(1) u_rib_ready_dffr (
dffr #(1) u_ribp_ready_dffr (
clk_i,
rst_n_i,
s_rib_ready_d,
s_rib_ready_q
s_ribp_ready_d,
s_ribp_ready_q
);
assign rx_pop_valid_o = s_rib_rd_hdshk;
assign s_rib_rdata_en = s_rib_rd_hdshk;
assign s_rib_rdata_d = (rib.valid && rx_pop_ready_i) ? rx_pop_data_i : s_rib_rdata_q;
dffer #(32) u_rib_rdata_dffer (
assign rx_pop_valid_o = s_ribp_rd_hdshk;
assign s_ribp_rdata_en = s_ribp_rd_hdshk;
assign s_ribp_rdata_d = (ribp.valid && rx_pop_ready_i) ? rx_pop_data_i : s_ribp_rdata_q;
dffer #(32) u_ribp_rdata_dffer (
clk_i,
rst_n_i,
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
s_ribp_rdata_en,
s_ribp_rdata_d,
s_ribp_rdata_q
);
@@ -109,7 +109,7 @@ module xpi_mm (
always_comb begin
s_nss_d = s_nss_q;
for (int i = 0; i < `XPI_NSS_NUM; i++) begin
if (xpi_mmstad_i[i] <= rib.addr && rib.addr <= xpi_mmstad_i[i] + xpi_mmoffst_i[i]) begin
if (xpi_mmstad_i[i] <= ribp.addr && ribp.addr <= xpi_mmstad_i[i] + xpi_mmoffst_i[i]) begin
s_nss_d = `XPI_LNS_NUM'(i);
break;
end
@@ -128,7 +128,7 @@ module xpi_mm (
edge_det_sync_re #(1) u_mem_valid_edge_det_sync_re (
clk_i,
rst_n_i,
rib.valid,
ribp.valid,
s_mem_valid_re
);
@@ -145,15 +145,15 @@ module xpi_mm (
unique case (r_fsm_state)
FSM_IDLE: begin
if (s_mem_valid_re) begin
if (|rib.wstrb) begin
if (|ribp.wstrb) begin
r_fsm_state <= FSM_WE_ST;
r_addr <= {4'd0, rib.addr[27:0]} + {30'd0, s_disp_addr_ofst};
r_addr <= {4'd0, ribp.addr[27:0]} + {30'd0, s_disp_addr_ofst};
r_wr_data <= s_disp_wdata;
r_xfer_byte_cnt <= s_disp_byte_cnt;
end else begin
r_fsm_state <= FSM_RD_ST;
r_addr <= {4'd0, rib.addr[27:0]};
r_wr_data <= rib.wdata; // NOTE: no used
r_addr <= {4'd0, ribp.addr[27:0]};
r_wr_data <= ribp.wdata; // NOTE: no used
r_xfer_byte_cnt <= 3'd4;
end
end
@@ -192,8 +192,8 @@ module xpi_mm (
end
xfer_dispatcher u_xfer_dispatcher (
.wstrb_i (rib.wstrb),
.wdata_i (rib.wdata),
.wstrb_i (ribp.wstrb),
.wdata_i (ribp.wdata),
.addr_ofst_o (s_disp_addr_ofst),
.xfer_byte_cnt_o(s_disp_byte_cnt),
.wdata_o (s_disp_wdata)
rtl/ip/rib/storage/xpi_reg.sv → rtl/ip/ribp/storage/xpi_reg.sv
+137 -137
View File
@@ -58,15 +58,15 @@ module xpi_reg (
// dma
output logic dma_tx_stall_o,
output logic dma_rx_stall_o,
rib_if.slave rib
ribp_if.slave ribp
// verilog_format: on
);
// rib
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
// ribp
logic s_ribp_wr_hdshk, s_ribp_rd_hdshk;
logic s_ribp_ready_d, s_ribp_ready_q;
logic s_ribp_rdata_en;
logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q;
// cfgidx
logic s_xpi_cfgidx_en;
logic [`XPI_LNS_NUM-1:0] s_xpi_cfgidx_d;
@@ -189,11 +189,11 @@ module xpi_reg (
logic s_tx_fifo_stall_d, s_tx_fifo_stall_q;
logic s_rx_fifo_stall_d, s_rx_fifo_stall_q;
// rib
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
// ribp
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.rdata = s_ribp_rdata_q;
// reg
assign xpi_accmd_o = s_xpi_accmd_q;
assign xpi_mmstad_o = s_xpi_mmstad_q;
@@ -225,8 +225,8 @@ module xpi_reg (
assign dma_rx_stall_o = s_rx_fifo_stall_q;
assign s_xpi_cfgidx_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_CFGIDX;
assign s_xpi_cfgidx_d = rib.wdata[`XPI_LNS_NUM-1:0];
assign s_xpi_cfgidx_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_CFGIDX;
assign s_xpi_cfgidx_d = ribp.wdata[`XPI_LNS_NUM-1:0];
dffer #(`XPI_LNS_NUM) u_xpi_cfgidx_dffer (
clk_i,
rst_n_i,
@@ -237,8 +237,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ACCMD_BLOCK
assign s_xpi_accmd_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_ACCMD && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_accmd_d[i] = rib.wdata[0];
assign s_xpi_accmd_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_ACCMD && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_accmd_d[i] = ribp.wdata[0];
end
dfferm #(`XPI_NSS_NUM, 1, 1'b1) u_xpi_accmd_dfferm (
clk_i,
@@ -251,13 +251,13 @@ module xpi_reg (
// 5000_0000 - 5FFF_FFFF
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_MMSTAD_BLOCK
assign s_xpi_mmstad_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_MMSTAD && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_mmstad_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_MMSTAD && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
always_comb begin
s_xpi_mmstad_d[i] = s_xpi_mmstad_q[i];
if (rib.wstrb[0]) s_xpi_mmstad_d[i][7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_xpi_mmstad_d[i][15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_xpi_mmstad_d[i][23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_xpi_mmstad_d[i][31:24] = rib.wdata[31:24];
if (ribp.wstrb[0]) s_xpi_mmstad_d[i][7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_xpi_mmstad_d[i][15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_xpi_mmstad_d[i][23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_xpi_mmstad_d[i][31:24] = ribp.wdata[31:24];
end
end
dfferm #(`XPI_NSS_NUM, 32, 32'd0) u_xpi_mmdstad_dfferm (
@@ -270,13 +270,13 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_MMOFFST_BLOCK
assign s_xpi_mmoffst_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_MMOFFST && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_mmoffst_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_MMOFFST && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
always_comb begin
s_xpi_mmoffst_d[i] = s_xpi_mmoffst_q[i];
if (rib.wstrb[0]) s_xpi_mmoffst_d[i][7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_xpi_mmoffst_d[i][15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_xpi_mmoffst_d[i][23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_xpi_mmoffst_d[i][31:24] = rib.wdata[31:24];
if (ribp.wstrb[0]) s_xpi_mmoffst_d[i][7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_xpi_mmoffst_d[i][15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_xpi_mmoffst_d[i][23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_xpi_mmoffst_d[i][31:24] = ribp.wdata[31:24];
end
end
dfferm #(`XPI_NSS_NUM, 32, 32'h0200_0000) u_xpi_mmoffst_dfferm (
@@ -289,8 +289,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_MODE_BLOCK
assign s_xpi_mode_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_MODE && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_mode_d[i] = rib.wdata[0];
assign s_xpi_mode_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_MODE && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_mode_d[i] = ribp.wdata[0];
end
dfferm #(`XPI_NSS_NUM, 1, 1'b0) u_xpi_mode_dfferm (
clk_i,
@@ -301,8 +301,8 @@ module xpi_reg (
);
assign s_xpi_nss_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_NSS;
assign s_xpi_nss_d = rib.wdata[`XPI_LNS_NUM-1:0];
assign s_xpi_nss_en = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_NSS;
assign s_xpi_nss_d = ribp.wdata[`XPI_LNS_NUM-1:0];
dffer #(`XPI_LNS_NUM) u_xpi_nss_dffer (
clk_i,
rst_n_i,
@@ -313,8 +313,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_CLKDIV_BLOCK
assign s_xpi_clkdiv_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_CLKDIV && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_clkdiv_d[i] = rib.wdata[7:0];
assign s_xpi_clkdiv_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_CLKDIV && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_clkdiv_d[i] = ribp.wdata[7:0];
end
dfferm #(`XPI_NSS_NUM, 8, 8'd0) u_xpi_clkdiv_dfferm (
clk_i,
@@ -326,8 +326,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_RDWR_BLOCK
assign s_xpi_rdwr_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_RDWR && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_rdwr_d[i] = rib.wdata[0];
assign s_xpi_rdwr_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_RDWR && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_rdwr_d[i] = ribp.wdata[0];
end
dfferm #(`XPI_NSS_NUM, 1, 1'b1) u_xpi_rdwr_dfferm (
clk_i,
@@ -339,8 +339,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_REVDAT_BLOCK
assign s_xpi_revdat_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_REVDAT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_revdat_d[i] = rib.wdata[0];
assign s_xpi_revdat_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_REVDAT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_revdat_d[i] = ribp.wdata[0];
end
dfferm #(`XPI_NSS_NUM, 1, 1'b0) u_xpi_revdat_dfferm (
clk_i,
@@ -352,8 +352,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_TXUPB_BLOCK
assign s_xpi_txupb_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_TXUPB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_txupb_d[i] = rib.wdata[7:0];
assign s_xpi_txupb_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_TXUPB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_txupb_d[i] = ribp.wdata[7:0];
end
dfferm #(`XPI_NSS_NUM, 8, 8'd0) u_xpi_txupb_dfferm (
clk_i,
@@ -365,8 +365,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_TXLOWB_BLOCK
assign s_xpi_txlowb_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_TXLOWB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_txlowb_d[i] = rib.wdata[7:0];
assign s_xpi_txlowb_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_TXLOWB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_txlowb_d[i] = ribp.wdata[7:0];
end
dfferm #(`XPI_NSS_NUM, 8, 8'd0) u_xpi_txlowb_dfferm (
clk_i,
@@ -378,8 +378,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_RXUPB_BLOCK
assign s_xpi_rxupb_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_RXUPB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_rxupb_d[i] = rib.wdata[5:0];
assign s_xpi_rxupb_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_RXUPB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_rxupb_d[i] = ribp.wdata[5:0];
end
dfferm #(`XPI_NSS_NUM, 6, 6'd0) u_xpi_rxupb_dfferm (
clk_i,
@@ -391,8 +391,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_RXLOWB_BLOCK
assign s_xpi_rxlowb_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_RXLOWB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_rxlowb_d[i] = rib.wdata[5:0];
assign s_xpi_rxlowb_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_RXLOWB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_rxlowb_d[i] = ribp.wdata[5:0];
end
dfferm #(`XPI_NSS_NUM, 6, 6'd0) u_xpi_rxlowb_dfferm (
clk_i,
@@ -403,13 +403,13 @@ module xpi_reg (
);
assign s_xpi_flush = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_FLUSH;
assign s_xpi_flush_val = rib.wdata[0];
assign s_xpi_flush = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_FLUSH;
assign s_xpi_flush_val = ribp.wdata[0];
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_CMDTYP_BLOCK
assign s_xpi_cmdtyp_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_CMDTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_cmdtyp_d[i] = rib.wdata[1:0];
assign s_xpi_cmdtyp_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_CMDTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_cmdtyp_d[i] = ribp.wdata[1:0];
end
dfferm #(`XPI_NSS_NUM, 2, 2'd1) u_xpi_cmdtyp_dfferm (
clk_i,
@@ -421,8 +421,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_CMDLEN_BLOCK
assign s_xpi_cmdlen_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_CMDLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_cmdlen_d[i] = rib.wdata[2:0];
assign s_xpi_cmdlen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_CMDLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_cmdlen_d[i] = ribp.wdata[2:0];
end
dfferm #(`XPI_NSS_NUM, 3, 3'd1) u_xpi_cmdlen_dfferm (
clk_i,
@@ -434,13 +434,13 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_CMDDAT_BLOCK
assign s_xpi_cmddat_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_CMDDAT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_cmddat_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_CMDDAT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
always_comb begin
s_xpi_cmddat_d[i] = s_xpi_cmddat_q[i];
if (rib.wstrb[0]) s_xpi_cmddat_d[i][7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_xpi_cmddat_d[i][15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_xpi_cmddat_d[i][23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_xpi_cmddat_d[i][31:24] = rib.wdata[31:24];
if (ribp.wstrb[0]) s_xpi_cmddat_d[i][7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_xpi_cmddat_d[i][15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_xpi_cmddat_d[i][23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_xpi_cmddat_d[i][31:24] = ribp.wdata[31:24];
end
end
dfferm #(`XPI_NSS_NUM, 32, 32'hEB00_0000) u_xpi_cmddat_dfferm (
@@ -453,8 +453,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ADRTYP_BLOCK
assign s_xpi_adrtyp_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_ADRTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_adrtyp_d[i] = rib.wdata[1:0];
assign s_xpi_adrtyp_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_ADRTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_adrtyp_d[i] = ribp.wdata[1:0];
end
dfferm #(`XPI_NSS_NUM, 2, 2'd3) u_xpi_adrtyp_dfferm (
clk_i,
@@ -466,8 +466,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ADRLEN_BLOCK
assign s_xpi_adrlen_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_ADRLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_adrlen_d[i] = rib.wdata[2:0];
assign s_xpi_adrlen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_ADRLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_adrlen_d[i] = ribp.wdata[2:0];
end
dfferm #(`XPI_NSS_NUM, 3, 3'd4) u_xpi_adrlen_dfferm (
clk_i,
@@ -479,13 +479,13 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ADRDAT_BLOCK
assign s_xpi_adrdat_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_ADRDAT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_adrdat_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_ADRDAT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
always_comb begin
s_xpi_adrdat_d[i] = s_xpi_adrdat_q[i];
if (rib.wstrb[0]) s_xpi_adrdat_d[i][7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_xpi_adrdat_d[i][15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_xpi_adrdat_d[i][23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_xpi_adrdat_d[i][31:24] = rib.wdata[31:24];
if (ribp.wstrb[0]) s_xpi_adrdat_d[i][7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_xpi_adrdat_d[i][15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_xpi_adrdat_d[i][23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_xpi_adrdat_d[i][31:24] = ribp.wdata[31:24];
end
end
dfferm #(`XPI_NSS_NUM, 32, 32'd0) u_xpi_adrdat_dfferm (
@@ -498,8 +498,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ALTTYP_BLOCK
assign s_xpi_alttyp_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_ALTTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_alttyp_d[i] = rib.wdata[1:0];
assign s_xpi_alttyp_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_ALTTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_alttyp_d[i] = ribp.wdata[1:0];
end
dfferm #(`XPI_NSS_NUM, 2, 2'd0) u_xpi_alttyp_dfferm (
clk_i,
@@ -511,8 +511,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ALTLEN_BLOCK
assign s_xpi_altlen_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_ALTLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_altlen_d[i] = rib.wdata[2:0];
assign s_xpi_altlen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_ALTLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_altlen_d[i] = ribp.wdata[2:0];
end
dfferm #(`XPI_NSS_NUM, 3, 3'd0) u_xpi_altlen_dfferm (
clk_i,
@@ -524,13 +524,13 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ALTDAT_BLOCK
assign s_xpi_altdat_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_ALTDAT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_altdat_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_ALTDAT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
always_comb begin
s_xpi_altdat_d[i] = s_xpi_altdat_q[i];
if (rib.wstrb[0]) s_xpi_altdat_d[i][7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_xpi_altdat_d[i][15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_xpi_altdat_d[i][23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_xpi_altdat_d[i][31:24] = rib.wdata[31:24];
if (ribp.wstrb[0]) s_xpi_altdat_d[i][7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) s_xpi_altdat_d[i][15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) s_xpi_altdat_d[i][23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) s_xpi_altdat_d[i][31:24] = ribp.wdata[31:24];
end
end
dfferm #(`XPI_NSS_NUM, 32, 32'd0) u_xpi_altdat_dfferm (
@@ -543,8 +543,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_TDULEN_BLOCK
assign s_xpi_tdulen_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_TDULEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_tdulen_d[i] = rib.wdata[7:0];
assign s_xpi_tdulen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_TDULEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_tdulen_d[i] = ribp.wdata[7:0];
end
dfferm #(`XPI_NSS_NUM, 8, 8'd4) u_xpi_tdulen_dfferm (
clk_i,
@@ -556,8 +556,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_RDULEN_BLOCK
assign s_xpi_rdulen_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_RDULEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_rdulen_d[i] = rib.wdata[7:0];
assign s_xpi_rdulen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_RDULEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_rdulen_d[i] = ribp.wdata[7:0];
end
dfferm #(`XPI_NSS_NUM, 8, 8'd4) u_xpi_rdulen_dfferm (
clk_i,
@@ -569,8 +569,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_DATTYP_BLOCK
assign s_xpi_dattyp_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_DATTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_dattyp_d[i] = rib.wdata[1:0];
assign s_xpi_dattyp_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_DATTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_dattyp_d[i] = ribp.wdata[1:0];
end
dfferm #(`XPI_NSS_NUM, 2, 2'd3) u_xpi_dattyp_dfferm (
clk_i,
@@ -582,8 +582,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_DATLEN_BLOCK
assign s_xpi_datlen_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_DATLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_datlen_d[i] = rib.wdata[7:0];
assign s_xpi_datlen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_DATLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_datlen_d[i] = ribp.wdata[7:0];
end
dfferm #(`XPI_NSS_NUM, 8, 8'd1) u_xpi_datlen_dfferm (
clk_i,
@@ -595,8 +595,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_DATBIT_BLOCK
assign s_xpi_datbit_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_DATBIT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_datbit_d[i] = rib.wdata[2:0];
assign s_xpi_datbit_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_DATBIT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_datbit_d[i] = ribp.wdata[2:0];
end
dfferm #(`XPI_NSS_NUM, 3, 3'd4) u_xpi_datbit_dfferm (
clk_i,
@@ -608,8 +608,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_HLVLEN_BLOCK
assign s_xpi_hlvlen_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_HLVLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_hlvlen_d[i] = rib.wdata[7:0];
assign s_xpi_hlvlen_en[i] = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_HLVLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_hlvlen_d[i] = ribp.wdata[7:0];
end
dfferm #(`XPI_NSS_NUM, 8, 8'd2) u_xpi_hlvlen_dfferm (
clk_i,
@@ -624,17 +624,17 @@ module xpi_reg (
always_comb begin
tx_push_valid_o = 1'b0;
tx_push_data_o = '0;
if (s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_TXDATA) begin
if (s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_TXDATA) begin
tx_push_valid_o = 1'b1;
if (rib.wstrb[0]) tx_push_data_o[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) tx_push_data_o[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) tx_push_data_o[23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) tx_push_data_o[31:24] = rib.wdata[31:24];
if (ribp.wstrb[0]) tx_push_data_o[7:0] = ribp.wdata[7:0];
if (ribp.wstrb[1]) tx_push_data_o[15:8] = ribp.wdata[15:8];
if (ribp.wstrb[2]) tx_push_data_o[23:16] = ribp.wdata[23:16];
if (ribp.wstrb[3]) tx_push_data_o[31:24] = ribp.wdata[31:24];
end
end
// start
assign xfer_start_o = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_XST;
assign xfer_start_o = s_ribp_wr_hdshk && ribp.addr[7:0] == `RIBP_XPI_XST;
// status
// [20:14] rx elem num
@@ -654,7 +654,7 @@ module xpi_reg (
s_xpi_status_d[20:14] = rx_elem_num_i;
if (xfer_done_i) begin
s_xpi_status_d[0] = 1'b1;
end else if (s_rib_rd_hdshk && rib.addr[7:0] == `RIB_XPI_STATUS) begin
end else if (s_ribp_rd_hdshk && ribp.addr[7:0] == `RIBP_XPI_STATUS) begin
s_xpi_status_d[0] = 1'b0;
end
end
@@ -699,67 +699,67 @@ module xpi_reg (
);
// rib rd
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
// ribp rd
assign s_ribp_ready_d = ribp.valid && (~s_ribp_ready_q);
dffr #(1) u_ribp_ready_dffr (
clk_i,
rst_n_i,
s_rib_ready_d,
s_rib_ready_q
s_ribp_ready_d,
s_ribp_ready_q
);
// verilog_format: off
assign s_rib_rdata_en = s_rib_rd_hdshk;
assign s_ribp_rdata_en = s_ribp_rd_hdshk;
always_comb begin
rx_pop_valid_o = '0;
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_XPI_CFGIDX: s_rib_rdata_d = {{(32 - `XPI_LNS_NUM) {1'b0}}, s_xpi_cfgidx_q};
`RIB_XPI_ACCMD: s_rib_rdata_d = {31'd0, s_xpi_accmd_q[s_xpi_cfgidx_q]};
`RIB_XPI_MMSTAD: s_rib_rdata_d = s_xpi_mmstad_q[s_xpi_cfgidx_q];
`RIB_XPI_MMOFFST: s_rib_rdata_d = s_xpi_mmoffst_q[s_xpi_cfgidx_q];
`RIB_XPI_MODE: s_rib_rdata_d = {31'd0, s_xpi_mode_q[s_xpi_cfgidx_q]};
`RIB_XPI_NSS: s_rib_rdata_d = {{(32 - `XPI_LNS_NUM) {1'b0}}, s_xpi_nss_q};
`RIB_XPI_CLKDIV: s_rib_rdata_d = {24'd0, s_xpi_clkdiv_q[s_xpi_cfgidx_q]};
`RIB_XPI_RDWR: s_rib_rdata_d = {31'd0, s_xpi_rdwr_q[s_xpi_cfgidx_q]};
`RIB_XPI_REVDAT: s_rib_rdata_d = {31'd0, s_xpi_revdat_q[s_xpi_cfgidx_q]};
`RIB_XPI_TXUPB: s_rib_rdata_d = {24'd0, s_xpi_txupb_q[s_xpi_cfgidx_q]};
`RIB_XPI_TXLOWB: s_rib_rdata_d = {24'd0, s_xpi_txlowb_q[s_xpi_cfgidx_q]};
`RIB_XPI_RXUPB: s_rib_rdata_d = {26'd0, s_xpi_rxupb_q[s_xpi_cfgidx_q]};
`RIB_XPI_RXLOWB: s_rib_rdata_d = {26'd0, s_xpi_rxlowb_q[s_xpi_cfgidx_q]};
`RIB_XPI_CMDTYP: s_rib_rdata_d = {30'd0, s_xpi_cmdtyp_q[s_xpi_cfgidx_q]};
`RIB_XPI_CMDLEN: s_rib_rdata_d = {29'd0, s_xpi_cmdlen_q[s_xpi_cfgidx_q]};
`RIB_XPI_CMDDAT: s_rib_rdata_d = s_xpi_cmddat_q[s_xpi_cfgidx_q];
`RIB_XPI_ADRTYP: s_rib_rdata_d = {30'd0, s_xpi_adrtyp_q[s_xpi_cfgidx_q]};
`RIB_XPI_ADRLEN: s_rib_rdata_d = {29'd0, s_xpi_adrlen_q[s_xpi_cfgidx_q]};
`RIB_XPI_ADRDAT: s_rib_rdata_d = s_xpi_adrdat_q[s_xpi_cfgidx_q];
`RIB_XPI_ALTTYP: s_rib_rdata_d = {30'd0, s_xpi_alttyp_q[s_xpi_cfgidx_q]};
`RIB_XPI_ALTLEN: s_rib_rdata_d = {29'd0, s_xpi_altlen_q[s_xpi_cfgidx_q]};
`RIB_XPI_ALTDAT: s_rib_rdata_d = s_xpi_altdat_q[s_xpi_cfgidx_q];
`RIB_XPI_TDULEN: s_rib_rdata_d = {24'd0, s_xpi_tdulen_q[s_xpi_cfgidx_q]};
`RIB_XPI_RDULEN: s_rib_rdata_d = {24'd0, s_xpi_rdulen_q[s_xpi_cfgidx_q]};
`RIB_XPI_DATTYP: s_rib_rdata_d = {30'd0, s_xpi_dattyp_q[s_xpi_cfgidx_q]};
`RIB_XPI_DATLEN: s_rib_rdata_d = {24'd0, s_xpi_datlen_q[s_xpi_cfgidx_q]};
`RIB_XPI_DATBIT: s_rib_rdata_d = {29'd0, s_xpi_datbit_q[s_xpi_cfgidx_q]};
`RIB_XPI_HLVLEN: s_rib_rdata_d = {24'd0, s_xpi_hlvlen_q[s_xpi_cfgidx_q]};
`RIB_XPI_RXDATA: begin
if (s_rib_rd_hdshk) begin
s_ribp_rdata_d = s_ribp_rdata_q;
unique case (ribp.addr[7:0])
`RIBP_XPI_CFGIDX: s_ribp_rdata_d = {{(32 - `XPI_LNS_NUM) {1'b0}}, s_xpi_cfgidx_q};
`RIBP_XPI_ACCMD: s_ribp_rdata_d = {31'd0, s_xpi_accmd_q[s_xpi_cfgidx_q]};
`RIBP_XPI_MMSTAD: s_ribp_rdata_d = s_xpi_mmstad_q[s_xpi_cfgidx_q];
`RIBP_XPI_MMOFFST: s_ribp_rdata_d = s_xpi_mmoffst_q[s_xpi_cfgidx_q];
`RIBP_XPI_MODE: s_ribp_rdata_d = {31'd0, s_xpi_mode_q[s_xpi_cfgidx_q]};
`RIBP_XPI_NSS: s_ribp_rdata_d = {{(32 - `XPI_LNS_NUM) {1'b0}}, s_xpi_nss_q};
`RIBP_XPI_CLKDIV: s_ribp_rdata_d = {24'd0, s_xpi_clkdiv_q[s_xpi_cfgidx_q]};
`RIBP_XPI_RDWR: s_ribp_rdata_d = {31'd0, s_xpi_rdwr_q[s_xpi_cfgidx_q]};
`RIBP_XPI_REVDAT: s_ribp_rdata_d = {31'd0, s_xpi_revdat_q[s_xpi_cfgidx_q]};
`RIBP_XPI_TXUPB: s_ribp_rdata_d = {24'd0, s_xpi_txupb_q[s_xpi_cfgidx_q]};
`RIBP_XPI_TXLOWB: s_ribp_rdata_d = {24'd0, s_xpi_txlowb_q[s_xpi_cfgidx_q]};
`RIBP_XPI_RXUPB: s_ribp_rdata_d = {26'd0, s_xpi_rxupb_q[s_xpi_cfgidx_q]};
`RIBP_XPI_RXLOWB: s_ribp_rdata_d = {26'd0, s_xpi_rxlowb_q[s_xpi_cfgidx_q]};
`RIBP_XPI_CMDTYP: s_ribp_rdata_d = {30'd0, s_xpi_cmdtyp_q[s_xpi_cfgidx_q]};
`RIBP_XPI_CMDLEN: s_ribp_rdata_d = {29'd0, s_xpi_cmdlen_q[s_xpi_cfgidx_q]};
`RIBP_XPI_CMDDAT: s_ribp_rdata_d = s_xpi_cmddat_q[s_xpi_cfgidx_q];
`RIBP_XPI_ADRTYP: s_ribp_rdata_d = {30'd0, s_xpi_adrtyp_q[s_xpi_cfgidx_q]};
`RIBP_XPI_ADRLEN: s_ribp_rdata_d = {29'd0, s_xpi_adrlen_q[s_xpi_cfgidx_q]};
`RIBP_XPI_ADRDAT: s_ribp_rdata_d = s_xpi_adrdat_q[s_xpi_cfgidx_q];
`RIBP_XPI_ALTTYP: s_ribp_rdata_d = {30'd0, s_xpi_alttyp_q[s_xpi_cfgidx_q]};
`RIBP_XPI_ALTLEN: s_ribp_rdata_d = {29'd0, s_xpi_altlen_q[s_xpi_cfgidx_q]};
`RIBP_XPI_ALTDAT: s_ribp_rdata_d = s_xpi_altdat_q[s_xpi_cfgidx_q];
`RIBP_XPI_TDULEN: s_ribp_rdata_d = {24'd0, s_xpi_tdulen_q[s_xpi_cfgidx_q]};
`RIBP_XPI_RDULEN: s_ribp_rdata_d = {24'd0, s_xpi_rdulen_q[s_xpi_cfgidx_q]};
`RIBP_XPI_DATTYP: s_ribp_rdata_d = {30'd0, s_xpi_dattyp_q[s_xpi_cfgidx_q]};
`RIBP_XPI_DATLEN: s_ribp_rdata_d = {24'd0, s_xpi_datlen_q[s_xpi_cfgidx_q]};
`RIBP_XPI_DATBIT: s_ribp_rdata_d = {29'd0, s_xpi_datbit_q[s_xpi_cfgidx_q]};
`RIBP_XPI_HLVLEN: s_ribp_rdata_d = {24'd0, s_xpi_hlvlen_q[s_xpi_cfgidx_q]};
`RIBP_XPI_RXDATA: begin
if (s_ribp_rd_hdshk) begin
rx_pop_valid_o = 1'b1;
if (~rx_empty_i) s_rib_rdata_d = rx_pop_data_i;
else s_rib_rdata_d = '0;
if (~rx_empty_i) s_ribp_rdata_d = rx_pop_data_i;
else s_ribp_rdata_d = '0;
end
end
`RIB_XPI_STATUS: s_rib_rdata_d = {11'd0, s_xpi_status_q};
default: s_rib_rdata_d = s_rib_rdata_q;
`RIBP_XPI_STATUS: s_ribp_rdata_d = {11'd0, s_xpi_status_q};
default: s_ribp_rdata_d = s_ribp_rdata_q;
endcase
end
// verilog_format: on
dffer #(32) u_rib_rdata_dffer (
dffer #(32) u_ribp_rdata_dffer (
clk_i,
rst_n_i,
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
s_ribp_rdata_en,
s_ribp_rdata_d,
s_ribp_rdata_q
);
endmodule
rtl/ip/rib/util/async_fifo.sv → rtl/ip/ribp/util/async_fifo.sv
View File
File renamed without changes.
rtl/mini/address_map/generate_memory_map.py
+2 -2
View File
@@ -12,7 +12,7 @@ from typing import Any
MAX_ADDRESS = 1 << 32
VALID_ROUTES = {"rib", "apb", "ram", "reserved"}
VALID_ROUTES = {"ribp", "apb", "ram", "reserved"}
VALID_KINDS = {"active", "reserved"}
VALID_USER_ACCESS = {"none", "ro", "rw"}
VALID_BURST = {"incr1", "incr4"}
@@ -160,7 +160,7 @@ def render_rtl(
f"{range_expression(symbol, region['base'], region['end'])}",
]
lines.append("")
for route in ("rib", "apb", "ram", "reserved"):
for route in ("ribp", "apb", "ram", "reserved"):
selected = [
f"`SOC_ADDR_IS_{region['symbol']}(addr)"
for region in regions
rtl/mini/address_map/memory_map.json
+27 -27
View File
@@ -21,8 +21,8 @@
{"symbol": "PERF_USER_WAIT_HI", "offset": "0x50"},
{"symbol": "PERF_DMA_WAIT_LO", "offset": "0x54"},
{"symbol": "PERF_DMA_WAIT_HI", "offset": "0x58"},
{"symbol": "PERF_RIB_WAIT_LO", "offset": "0x5C"},
{"symbol": "PERF_RIB_WAIT_HI", "offset": "0x60"},
{"symbol": "PERF_RIBP_WAIT_LO", "offset": "0x5C"},
{"symbol": "PERF_RIBP_WAIT_HI", "offset": "0x60"},
{"symbol": "PERF_APB_WAIT_LO", "offset": "0x64"},
{"symbol": "PERF_APB_WAIT_HI", "offset": "0x68"},
{"symbol": "PERF_SDRAM_WAIT_LO", "offset": "0x6C"},
@@ -33,27 +33,27 @@
{"symbol": "PERF_FLASH_WAIT_HI", "offset": "0x80"}
],
"regions": [
{"symbol": "FLASH", "base": "0x00000000", "size": "0x01000000", "route": "rib", "kind": "active", "public": true, "linker": "FLASH", "user_access": "ro", "burst": "incr4"},
{"symbol": "RIB_GPIO", "base": "0x10000000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIB_UART0", "base": "0x10001000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIB_TIM0", "base": "0x10002000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIB_TIM1", "base": "0x10003000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIB_PSRAM", "base": "0x10004000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIB_SPISD", "base": "0x10005000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIB_I2C0", "base": "0x10006000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIB_I2S", "base": "0x10007000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIB_ONEWIRE", "base": "0x10008000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIB_XPI", "base": "0x10009000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIB_DMA", "base": "0x1000A000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIB_SYSCTRL", "base": "0x1000B000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIB_CLINT", "base": "0x1000C000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIB_SDRAM", "base": "0x1000D000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIB_DVP", "base": "0x1000E000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIB_SDIO", "base": "0x1000F000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "RIB_OPIPSRAM", "base": "0x10010000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "RIB_I2C1", "base": "0x10011000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIB_GA", "base": "0x10012000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "RIB_APU", "base": "0x10013000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "FLASH", "base": "0x00000000", "size": "0x01000000", "route": "ribp", "kind": "active", "public": true, "linker": "FLASH", "user_access": "ro", "burst": "incr4"},
{"symbol": "RIBP_GPIO", "base": "0x10000000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIBP_UART0", "base": "0x10001000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIBP_TIM0", "base": "0x10002000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIBP_TIM1", "base": "0x10003000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIBP_PSRAM", "base": "0x10004000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIBP_SPISD", "base": "0x10005000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIBP_I2C0", "base": "0x10006000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIBP_I2S", "base": "0x10007000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIBP_ONEWIRE", "base": "0x10008000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIBP_XPI", "base": "0x10009000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIBP_DMA", "base": "0x1000A000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIBP_SYSCTRL", "base": "0x1000B000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIBP_CLINT", "base": "0x1000C000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIBP_SDRAM", "base": "0x1000D000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIBP_DVP", "base": "0x1000E000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIBP_SDIO", "base": "0x1000F000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "RIBP_OPIPSRAM", "base": "0x10010000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "RIBP_I2C1", "base": "0x10011000", "size": "0x00001000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIBP_GA", "base": "0x10012000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "RIBP_APU", "base": "0x10013000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "APB_ARCHINFO", "base": "0x20000000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "ro"},
{"symbol": "APB_RNG", "base": "0x20001000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "APB_UART1", "base": "0x20002000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "rw"},
@@ -65,10 +65,10 @@
{"symbol": "APB_TMR", "base": "0x20008000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "APB_USER_IP", "base": "0x2000F000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "SRAM", "base": "0x30000000", "size": "0x00020000", "route": "ram", "kind": "active", "public": true, "linker": "SRAM", "user_access": "rw", "burst": "incr4"},
{"symbol": "SDRAM", "base": "0x38000000", "size": "0x02000000", "route": "rib", "kind": "active", "public": true, "linker": "SDRAM", "user_access": "rw", "burst": "incr4"},
{"symbol": "PSRAM", "base": "0x40000000", "size": "0x00800000", "route": "rib", "kind": "active", "public": true, "linker": "PSRAM", "user_access": "rw", "burst": "incr4"},
{"symbol": "SDRAM", "base": "0x38000000", "size": "0x02000000", "route": "ribp", "kind": "active", "public": true, "linker": "SDRAM", "user_access": "rw", "burst": "incr4"},
{"symbol": "PSRAM", "base": "0x40000000", "size": "0x00800000", "route": "ribp", "kind": "active", "public": true, "linker": "PSRAM", "user_access": "rw", "burst": "incr4"},
{"symbol": "OPIPSRAM", "base": "0x48000000", "size": "0x08000000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "XPI", "base": "0x50000000", "size": "0x10000000", "route": "rib", "kind": "active", "public": true, "user_access": "rw", "burst": "incr4"},
{"symbol": "SPISD", "base": "0x60000000", "size": "0x40000000", "route": "rib", "kind": "active", "public": true, "user_access": "rw", "burst": "incr4"}
{"symbol": "XPI", "base": "0x50000000", "size": "0x10000000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw", "burst": "incr4"},
{"symbol": "SPISD", "base": "0x60000000", "size": "0x40000000", "route": "ribp", "kind": "active", "public": true, "user_access": "rw", "burst": "incr4"}
]
}
rtl/mini/dv/sva/soc_protocol_sva.sv
+5 -5
View File
@@ -49,7 +49,7 @@ bind bus soc_bus_sva u_soc_bus_sva (
.access_denied_i (s_access_denied),
.cmd_accepted_i (s_cmd_accepted_q),
.arb_owner_i (s_mstr_id_q),
.mgmt_valid_i (mgmt_rib.valid),
.mgmt_valid_i (mgmt_ribl.valid),
.user_valid_i (user_rib.cmd_valid),
.dma_valid_i (dma_rib.cmd_valid)
);
@@ -72,14 +72,14 @@ module soc_rib2apb_sva #(
endmodule
bind rib2apb soc_rib2apb_sva #(
bind ribp2apb soc_rib2apb_sva #(
.NSLV(NSLV)
) u_soc_rib2apb_sva (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.psel_comb_i (s_psel_comb),
.psel_q_i (s_psel_q),
.rib_ready_i (rib.ready),
.rib_ready_i (ribp.ready),
.xfer_ready_i(s_xfer_ready)
);
@@ -140,8 +140,8 @@ module soc_gpio_user_handoff_sva #(
endmodule
bind rib_gpio soc_gpio_user_handoff_sva #(
.DATA_WIDTH(`RIB_GPIO_NUM)
bind ribp_gpio soc_gpio_user_handoff_sva #(
.DATA_WIDTH(`RIBP_GPIO_NUM)
) u_soc_gpio_user_handoff_sva (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
rtl/mini/filelist/commonip.fl
+3 -2
View File
@@ -1,10 +1,10 @@
/clusterip/common/rtl/interface/apb4_if.sv
/clusterip/common/rtl/interface/apb4_pure_if.sv
/clusterip/common/rtl/interface/ahbl_if.sv
/clusterip/common/rtl/interface/rib_if.sv
/clusterip/common/rtl/interface/ribp_if.sv
/clusterip/common/rtl/interface/ram_if.sv
/top/soc_ribl_if.sv
/top/soc_rib_if.sv
/top/soc_rib_burst_if.sv
/clusterip/common/rtl/utils/register.sv
/top/soc_common_fifo.sv
/clusterip/common/rtl/utils/spill_register.sv
@@ -12,6 +12,7 @@
/clusterip/common/rtl/utils/gray2bin.sv
/clusterip/common/rtl/utils/edge_det.sv
/clusterip/common/rtl/cdc/cdc_sync.sv
/clusterip/common/rtl/cdc/cdc_rst_ctrlr.sv
/clusterip/common/rtl/cdc/cdc_2phase.sv
/clusterip/common/rtl/clkrst/clk_int_div.sv
/clusterip/common/rtl/clkrst/rst_sync.sv
rtl/mini/filelist/inc.fl
+7 -7
View File
@@ -16,11 +16,11 @@
+incdir+/clusterip/wdg/rtl
+incdir+/clusterip/crc/rtl
+incdir+/clusterip/timer/rtl
+incdir+/ip/rib/interconnect
+incdir+/ip/rib/util
+incdir+/ip/rib/memory
+incdir+/ip/rib/storage
+incdir+/ip/rib/serial
+incdir+/ip/rib/multimedia
+incdir+/ip/rib/peripheral
+incdir+/ip/ribp/interconnect
+incdir+/ip/ribp/util
+incdir+/ip/ribp/memory
+incdir+/ip/ribp/storage
+incdir+/ip/ribp/serial
+incdir+/ip/ribp/multimedia
+incdir+/ip/ribp/peripheral
+incdir+/third_party/model/sdram/
rtl/mini/filelist/ip.fl
+49 -49
View File
@@ -1,49 +1,49 @@
/ip/rib/memory/psram_core.sv
/ip/rib/memory/psram.sv
/ip/rib/memory/opipsram.sv
/ip/rib/memory/opipsram_core.sv
/ip/rib/storage/spisd_init.sv
/ip/rib/storage/spisd_read.sv
/ip/rib/storage/spisd_write.sv
/ip/rib/storage/spisd_reg.sv
/ip/rib/storage/spisd_cache.sv
/ip/rib/storage/spisd_core.sv
/ip/rib/storage/spisd_data.sv
/ip/rib/storage/spisd.sv
/ip/rib/storage/sdio.sv
/ip/rib/serial/i2c_core.sv
/ip/rib/serial/i2c.sv
/ip/rib/serial/i2s_reg.sv
/ip/rib/serial/i2s_clkgen.sv
/ip/rib/serial/i2s_recv.sv
/ip/rib/serial/i2s_send.sv
/ip/rib/serial/i2s_core.sv
/ip/rib/serial/i2s.sv
/ip/rib/serial/onewire_core.sv
/ip/rib/serial/onewire.sv
/ip/rib/storage/xpi_reg.sv
/ip/rib/storage/xpi_mm.sv
/ip/rib/storage/xpi_clkgen.sv
/ip/rib/storage/xpi_core.sv
/ip/rib/storage/xpi.sv
/ip/rib/peripheral/dma_core.sv
/ip/rib/peripheral/dma.sv
/ip/rib/peripheral/pll_ctrl_if.sv
/ip/rib/peripheral/sysctrl.sv
/ip/rib/peripheral/clint.sv
/ip/rib/memory/sdram_clkgen.sv
/ip/rib/memory/sdram_reg.sv
/ip/rib/memory/sdram_core.sv
/ip/rib/memory/sdram.sv
/ip/rib/multimedia/dvp_core.sv
/ip/rib/multimedia/dvp.sv
/ip/rib/peripheral/timer.sv
/ip/rib/serial/uart.sv
/ip/rib/peripheral/gpio.sv
/ip/rib/interconnect/rib2apb.sv
/ip/rib/interconnect/ahbl2rib.sv
/top/ahbl2soc_rib.sv
/ip/rib/interconnect/axi4l2rib.sv
/ip/rib/util/async_fifo.sv
/ip/rib/interconnect/rib_regslice.sv
/ip/rib/interconnect/rib2rib.sv
/ip/ribp/memory/psram_core.sv
/ip/ribp/memory/psram.sv
/ip/ribp/memory/opipsram.sv
/ip/ribp/memory/opipsram_core.sv
/ip/ribp/storage/spisd_init.sv
/ip/ribp/storage/spisd_read.sv
/ip/ribp/storage/spisd_write.sv
/ip/ribp/storage/spisd_reg.sv
/ip/ribp/storage/spisd_cache.sv
/ip/ribp/storage/spisd_core.sv
/ip/ribp/storage/spisd_data.sv
/ip/ribp/storage/spisd.sv
/ip/ribp/storage/sdio.sv
/ip/ribp/serial/i2c_core.sv
/ip/ribp/serial/i2c.sv
/ip/ribp/serial/i2s_reg.sv
/ip/ribp/serial/i2s_clkgen.sv
/ip/ribp/serial/i2s_recv.sv
/ip/ribp/serial/i2s_send.sv
/ip/ribp/serial/i2s_core.sv
/ip/ribp/serial/i2s.sv
/ip/ribp/serial/onewire_core.sv
/ip/ribp/serial/onewire.sv
/ip/ribp/storage/xpi_reg.sv
/ip/ribp/storage/xpi_mm.sv
/ip/ribp/storage/xpi_clkgen.sv
/ip/ribp/storage/xpi_core.sv
/ip/ribp/storage/xpi.sv
/ip/ribp/peripheral/dma_core.sv
/ip/ribp/peripheral/dma.sv
/ip/ribp/peripheral/pll_ctrl_if.sv
/ip/ribp/peripheral/sysctrl.sv
/ip/ribp/peripheral/clint.sv
/ip/ribp/memory/sdram_clkgen.sv
/ip/ribp/memory/sdram_reg.sv
/ip/ribp/memory/sdram_core.sv
/ip/ribp/memory/sdram.sv
/ip/ribp/multimedia/dvp_core.sv
/ip/ribp/multimedia/dvp.sv
/ip/ribp/peripheral/timer.sv
/ip/ribp/serial/uart.sv
/ip/ribp/peripheral/gpio.sv
/ip/ribp/interconnect/ribp2apb.sv
/ip/ribp/interconnect/ahbl2ribp.sv
/top/ahbl2soc_ribl.sv
/ip/ribp/interconnect/axi4l2ribp.sv
/ip/ribp/util/async_fifo.sv
/ip/ribp/interconnect/ribp_regslice.sv
/ip/ribp/interconnect/ribp2ribp.sv
rtl/mini/filelist/top.fl
+6 -6
View File
@@ -1,15 +1,15 @@
/top/apb4_if_bridge.sv
/top/gpio_pad_bridge.sv
/top/soc_rib_legacy_to_burst.sv
/top/rib_legacy_to_burst.sv
/top/soc_rib_burst_to_legacy.sv
/top/soc_rib_burst_error_slave.sv
/top/soc_rib_burst_ram.sv
/top/soc_ribl2rib.sv
/top/ribp2rib.sv
/top/soc_rib2ribp.sv
/top/soc_rib_error_slave.sv
/top/soc_rib_ram.sv
/top/core_wrapper.sv
/top/retrosoc.sv
/top/retrosoc_asic.sv
/top/onchip_ram.sv
/top/ip_rib_wrapper.sv
/top/ip_ribp_wrapper.sv
/top/ip_apb_wrapper.sv
/top/bus.sv
/top/rcu.sv
rtl/mini/formal/bus_formal.sv
+19 -19
View File
@@ -30,11 +30,11 @@ module bus_formal_design (
output logic terminal_rsp
);
soc_rib_if mgmt_rib ();
soc_rib_burst_if user_rib ();
soc_rib_burst_if dma_rib ();
soc_rib_burst_if rib ();
rib_if apb_rib ();
soc_ribl_if mgmt_ribl ();
soc_rib_if user_rib ();
soc_rib_if dma_rib ();
soc_rib_if rib ();
ribp_if apb_ribp ();
(* anyseq *)logic f_mgmt_valid;
(* anyseq *)logic [31:0] f_mgmt_addr;
@@ -71,10 +71,10 @@ module bus_formal_design (
logic [ 2:0] fault_code;
logic user_idle;
assign mgmt_rib.valid = f_mgmt_valid;
assign mgmt_rib.addr = f_mgmt_addr;
assign mgmt_rib.wdata = f_mgmt_wdata;
assign mgmt_rib.wstrb = f_mgmt_wstrb;
assign mgmt_ribl.valid = f_mgmt_valid;
assign mgmt_ribl.addr = f_mgmt_addr;
assign mgmt_ribl.wdata = f_mgmt_wdata;
assign mgmt_ribl.wstrb = f_mgmt_wstrb;
assign user_rib.cmd_valid = f_user_cmd_valid;
assign user_rib.cmd_addr = f_user_cmd_addr;
@@ -138,13 +138,13 @@ module bus_formal_design (
end
end
assign apb_rib.ready = apb_rib.valid;
assign apb_rib.rdata = 32'h1234_5678;
assign apb_ribp.ready = apb_ribp.valid;
assign apb_ribp.rdata = 32'h1234_5678;
assign mgmt_valid = mgmt_rib.valid;
assign mgmt_addr = mgmt_rib.addr;
assign mgmt_wstrb = mgmt_rib.wstrb;
assign mgmt_ready = mgmt_rib.ready;
assign mgmt_valid = mgmt_ribl.valid;
assign mgmt_addr = mgmt_ribl.addr;
assign mgmt_wstrb = mgmt_ribl.wstrb;
assign mgmt_ready = mgmt_ribl.ready;
assign user_cmd_valid = user_rib.cmd_valid;
assign user_cmd_ready = user_rib.cmd_ready;
assign user_cmd_addr = user_rib.cmd_addr;
@@ -157,18 +157,18 @@ module bus_formal_design (
assign dma_cmd_len = dma_rib.cmd_len;
assign rib_cmd_valid = rib.cmd_valid;
assign rib_cmd_len = rib.cmd_len;
assign apb_valid = apb_rib.valid;
assign apb_valid = apb_ribp.valid;
bus u_dut (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.mgmt_rib (mgmt_rib),
.mgmt_ribl (mgmt_ribl),
.user_rib (user_rib),
.dma_rib (dma_rib),
.user_bus_enable_i(1'b1),
.user_bus_idle_o (user_idle),
.rib (rib),
.apb_rib (apb_rib),
.apb_ribp (apb_ribp),
.apb_resp_err_i (1'b0),
.perf_enable_i (1'b0),
.perf_clear_i (1'b0),
@@ -182,7 +182,7 @@ module bus_formal_design (
.perf_mgmt_wait_o (),
.perf_user_wait_o (),
.perf_dma_wait_o (),
.perf_rib_wait_o (),
.perf_ribp_wait_o (),
.perf_apb_wait_o (),
.perf_sdram_wait_o(),
.perf_psram_wait_o(),
rtl/mini/formal/generate_formal_filelist.py
+17 -15
View File
@@ -17,8 +17,8 @@ from filelist import FileList, write_filelist # noqa: E402
COMMON_RTL = ROOT / "rtl/managed/clusterip/common/rtl"
INTERCONNECT = ROOT / "rtl/ip/rib/interconnect"
PERIPHERAL = ROOT / "rtl/ip/rib/peripheral"
INTERCONNECT = ROOT / "rtl/ip/ribp/interconnect"
PERIPHERAL = ROOT / "rtl/ip/ribp/peripheral"
TOP = ROOT / "rtl/mini/top"
@@ -28,28 +28,28 @@ def target_defines(target: str) -> list[str]:
def source_files(target: str) -> list[Path]:
common = [
COMMON_RTL / "interface/rib_if.sv",
COMMON_RTL / "interface/ribp_if.sv",
COMMON_RTL / "interface/ram_if.sv",
COMMON_RTL / "utils/register.sv",
TOP / "soc_ribl_if.sv",
TOP / "soc_rib_if.sv",
TOP / "soc_rib_burst_if.sv",
]
if target == "bus":
return [
*common,
COMMON_RTL / "utils/spill_register.sv",
TOP / "soc_rib_legacy_to_burst.sv",
TOP / "soc_rib_burst_to_legacy.sv",
TOP / "soc_rib_burst_error_slave.sv",
TOP / "soc_rib_burst_ram.sv",
TOP / "soc_ribl2rib.sv",
TOP / "soc_rib2ribp.sv",
TOP / "soc_rib_error_slave.sv",
TOP / "soc_rib_ram.sv",
TOP / "bus.sv",
SCRIPT_DIR / "bus_formal.sv",
]
if target == "rib_adapter":
return [
*common,
TOP / "soc_rib_legacy_to_burst.sv",
TOP / "soc_rib_burst_to_legacy.sv",
TOP / "soc_ribl2rib.sv",
TOP / "soc_rib2ribp.sv",
SCRIPT_DIR / "rib_adapter_formal.sv",
]
if target == "spill_register":
@@ -58,14 +58,14 @@ def source_files(target: str) -> list[Path]:
COMMON_RTL / "utils/spill_register.sv",
SCRIPT_DIR / "spill_register_formal.sv",
]
if target == "rib2apb":
if target == "ribp2apb":
return [
COMMON_RTL / "interface/rib_if.sv",
COMMON_RTL / "interface/ribp_if.sv",
COMMON_RTL / "interface/apb4_pure_if.sv",
COMMON_RTL / "utils/register.sv",
COMMON_RTL / "utils/edge_det.sv",
INTERCONNECT / "rib2apb.sv",
SCRIPT_DIR / "rib2apb_formal.sv",
INTERCONNECT / "ribp2apb.sv",
SCRIPT_DIR / "ribp2apb_formal.sv",
]
if target == "sysctrl":
return [
@@ -78,6 +78,7 @@ def source_files(target: str) -> list[Path]:
return [
*common,
COMMON_RTL / "cdc/cdc_sync.sv",
COMMON_RTL / "cdc/cdc_rst_ctrlr.sv",
COMMON_RTL / "cdc/cdc_2phase.sv",
PERIPHERAL / "pll_ctrl_if.sv",
TOP / "rcu.sv",
@@ -87,6 +88,7 @@ def source_files(target: str) -> list[Path]:
return [
*common,
COMMON_RTL / "cdc/cdc_sync.sv",
COMMON_RTL / "cdc/cdc_rst_ctrlr.sv",
COMMON_RTL / "utils/edge_det.sv",
PERIPHERAL / "gpio.sv",
SCRIPT_DIR / "gpio_user_formal.sv",
@@ -127,7 +129,7 @@ def parse_args() -> argparse.Namespace:
"bus",
"rib_adapter",
"spill_register",
"rib2apb",
"ribp2apb",
"sysctrl",
"pll_rcu",
"gpio_user",
rtl/mini/formal/gpio_user_formal.sv
+3 -3
View File
@@ -24,7 +24,7 @@ module gpio_user_formal_design (
output logic [31:0] native_do
);
rib_if rib ();
ribp_if rib ();
gpio_if gpio ();
user_gpio_if user_gpio ();
@@ -70,10 +70,10 @@ module gpio_user_formal_design (
assign native_oe = u_dut.s_gpio_native_oe;
assign native_do = u_dut.s_gpio_native_out;
rib_gpio u_dut (
ribp_gpio u_dut (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.rib (rib),
.ribp (rib),
.gpio (gpio),
.user_gpio(user_gpio)
);
rtl/mini/formal/rib_adapter_formal.sv
+80 -80
View File
@@ -21,11 +21,11 @@ module rib_adapter_formal_design (
output logic [ 2:0] rsp_code,
output logic [ 1:0] rsp_beat,
output logic rsp_last,
output logic legacy_valid,
output logic legacy_ready,
output logic [31:0] legacy_addr,
output logic [31:0] legacy_wdata,
output logic [ 3:0] legacy_wstrb,
output logic ribp_valid,
output logic ribp_ready,
output logic [31:0] ribp_addr,
output logic [31:0] ribp_wdata,
output logic [ 3:0] ribp_wstrb,
output logic source_valid,
output logic source_ready,
output logic [31:0] source_addr,
@@ -41,10 +41,10 @@ module rib_adapter_formal_design (
output logic adapted_wlast
);
soc_rib_burst_if burst_source ();
rib_if legacy_target ();
soc_rib_if legacy_source ();
soc_rib_burst_if burst_target ();
soc_rib_if rib_source ();
ribp_if ribp_target ();
soc_ribl_if ribl_source ();
soc_rib_if rib_target ();
(* anyseq *)logic f_cmd_valid;
(* anyseq *)logic [31:0] f_cmd_addr;
@@ -55,10 +55,10 @@ module rib_adapter_formal_design (
(* anyseq *)logic [ 3:0] f_wstrb;
(* anyseq *)logic f_wlast;
(* anyseq *)logic f_rsp_ready;
(* anyseq *)logic f_legacy_ready;
(* anyseq *)logic [31:0] f_legacy_rdata;
(* anyseq *)logic f_legacy_error;
(* anyseq *)logic [ 2:0] f_legacy_code;
(* anyseq *)logic f_ribp_ready;
(* anyseq *)logic [31:0] f_ribp_rdata;
(* anyseq *)logic f_ribp_error;
(* anyseq *)logic [ 2:0] f_ribp_code;
(* anyseq *)logic f_source_valid;
(* anyseq *)logic [31:0] f_source_addr;
@@ -71,82 +71,82 @@ module rib_adapter_formal_design (
(* anyseq *)logic f_target_error;
(* anyseq *)logic [ 2:0] f_target_code;
assign burst_source.cmd_valid = f_cmd_valid;
assign burst_source.cmd_addr = f_cmd_addr;
assign burst_source.cmd_write = f_cmd_write;
assign burst_source.cmd_len = f_cmd_len;
assign burst_source.w_valid = f_w_valid;
assign burst_source.wdata = f_wdata;
assign burst_source.wstrb = f_wstrb;
assign burst_source.wlast = f_wlast;
assign burst_source.rsp_ready = f_rsp_ready;
assign legacy_target.ready = f_legacy_ready;
assign legacy_target.rdata = f_legacy_rdata;
assign rib_source.cmd_valid = f_cmd_valid;
assign rib_source.cmd_addr = f_cmd_addr;
assign rib_source.cmd_write = f_cmd_write;
assign rib_source.cmd_len = f_cmd_len;
assign rib_source.w_valid = f_w_valid;
assign rib_source.wdata = f_wdata;
assign rib_source.wstrb = f_wstrb;
assign rib_source.wlast = f_wlast;
assign rib_source.rsp_ready = f_rsp_ready;
assign ribp_target.ready = f_ribp_ready;
assign ribp_target.rdata = f_ribp_rdata;
soc_rib_burst_to_legacy u_burst_to_legacy (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.legacy_resp_err_i (f_legacy_error),
.legacy_resp_code_i(f_legacy_code),
.burst (burst_source),
.legacy (legacy_target)
soc_rib2ribp u_rib2ribp (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.ribp_resp_err_i (f_ribp_error),
.ribp_resp_code_i(f_ribp_code),
.rib (rib_source),
.ribp (ribp_target)
);
assign legacy_source.valid = f_source_valid;
assign legacy_source.addr = f_source_addr;
assign legacy_source.wdata = f_source_wdata;
assign legacy_source.wstrb = f_source_wstrb;
assign burst_target.cmd_ready = f_target_cmd_ready;
assign burst_target.w_ready = f_target_w_ready;
assign burst_target.rsp_valid = f_target_rsp_valid;
assign burst_target.rdata = f_target_rdata;
assign burst_target.resp_err = f_target_error;
assign burst_target.resp_code = f_target_code;
assign burst_target.rsp_beat = '0;
assign burst_target.rsp_last = 1'b1;
assign ribl_source.valid = f_source_valid;
assign ribl_source.addr = f_source_addr;
assign ribl_source.wdata = f_source_wdata;
assign ribl_source.wstrb = f_source_wstrb;
assign rib_target.cmd_ready = f_target_cmd_ready;
assign rib_target.w_ready = f_target_w_ready;
assign rib_target.rsp_valid = f_target_rsp_valid;
assign rib_target.rdata = f_target_rdata;
assign rib_target.resp_err = f_target_error;
assign rib_target.resp_code = f_target_code;
assign rib_target.rsp_beat = '0;
assign rib_target.rsp_last = 1'b1;
soc_rib_legacy_to_burst u_legacy_to_burst (
soc_ribl2rib u_ribl2rib (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.legacy (legacy_source),
.burst (burst_target)
.ribl (ribl_source),
.rib (rib_target)
);
assign cmd_valid = burst_source.cmd_valid;
assign cmd_ready = burst_source.cmd_ready;
assign cmd_addr = burst_source.cmd_addr;
assign cmd_write = burst_source.cmd_write;
assign cmd_len = burst_source.cmd_len;
assign w_valid = burst_source.w_valid;
assign w_ready = burst_source.w_ready;
assign wdata = burst_source.wdata;
assign wstrb = burst_source.wstrb;
assign wlast = burst_source.wlast;
assign rsp_valid = burst_source.rsp_valid;
assign rsp_ready = burst_source.rsp_ready;
assign rsp_rdata = burst_source.rdata;
assign rsp_code = burst_source.resp_code;
assign rsp_beat = burst_source.rsp_beat;
assign rsp_last = burst_source.rsp_last;
assign legacy_valid = legacy_target.valid;
assign legacy_ready = legacy_target.ready;
assign legacy_addr = legacy_target.addr;
assign legacy_wdata = legacy_target.wdata;
assign legacy_wstrb = legacy_target.wstrb;
assign cmd_valid = rib_source.cmd_valid;
assign cmd_ready = rib_source.cmd_ready;
assign cmd_addr = rib_source.cmd_addr;
assign cmd_write = rib_source.cmd_write;
assign cmd_len = rib_source.cmd_len;
assign w_valid = rib_source.w_valid;
assign w_ready = rib_source.w_ready;
assign wdata = rib_source.wdata;
assign wstrb = rib_source.wstrb;
assign wlast = rib_source.wlast;
assign rsp_valid = rib_source.rsp_valid;
assign rsp_ready = rib_source.rsp_ready;
assign rsp_rdata = rib_source.rdata;
assign rsp_code = rib_source.resp_code;
assign rsp_beat = rib_source.rsp_beat;
assign rsp_last = rib_source.rsp_last;
assign ribp_valid = ribp_target.valid;
assign ribp_ready = ribp_target.ready;
assign ribp_addr = ribp_target.addr;
assign ribp_wdata = ribp_target.wdata;
assign ribp_wstrb = ribp_target.wstrb;
assign source_valid = legacy_source.valid;
assign source_ready = legacy_source.ready;
assign source_addr = legacy_source.addr;
assign source_wstrb = legacy_source.wstrb;
assign adapted_cmd_valid = burst_target.cmd_valid;
assign adapted_cmd_ready = burst_target.cmd_ready;
assign adapted_cmd_addr = burst_target.cmd_addr;
assign adapted_cmd_len = burst_target.cmd_len;
assign adapted_w_valid = burst_target.w_valid;
assign adapted_w_ready = burst_target.w_ready;
assign adapted_wdata = burst_target.wdata;
assign adapted_wstrb = burst_target.wstrb;
assign adapted_wlast = burst_target.wlast;
assign source_valid = ribl_source.valid;
assign source_ready = ribl_source.ready;
assign source_addr = ribl_source.addr;
assign source_wstrb = ribl_source.wstrb;
assign adapted_cmd_valid = rib_target.cmd_valid;
assign adapted_cmd_ready = rib_target.cmd_ready;
assign adapted_cmd_addr = rib_target.cmd_addr;
assign adapted_cmd_len = rib_target.cmd_len;
assign adapted_w_valid = rib_target.w_valid;
assign adapted_w_ready = rib_target.w_ready;
assign adapted_wdata = rib_target.wdata;
assign adapted_wstrb = rib_target.wstrb;
assign adapted_wlast = rib_target.wlast;
initial begin
rst_n_i = 1'b0;
rtl/mini/formal/rib_adapter_formal_props.v
+9 -9
View File
@@ -15,9 +15,9 @@ module rib_adapter_formal;
wire [31:0] rsp_rdata;
wire [ 2:0] rsp_code;
wire [ 1:0] rsp_beat;
wire legacy_valid, legacy_ready;
wire [31:0] legacy_addr, legacy_wdata;
wire [3:0] legacy_wstrb;
wire ribp_valid, ribp_ready;
wire [31:0] ribp_addr, ribp_wdata;
wire [3:0] ribp_wstrb;
wire source_valid, source_ready;
wire [31:0] source_addr;
wire [ 3:0] source_wstrb;
@@ -49,11 +49,11 @@ module rib_adapter_formal;
assume (source_wstrb == $past(source_wstrb));
end
if (rst_n_i) begin
if (f_past_valid && $past(rst_n_i && legacy_valid && !legacy_ready)) begin
assert (legacy_valid);
assert (legacy_addr == $past(legacy_addr));
assert (legacy_wdata == $past(legacy_wdata));
assert (legacy_wstrb == $past(legacy_wstrb));
if (f_past_valid && $past(rst_n_i && ribp_valid && !ribp_ready)) begin
assert (ribp_valid);
assert (ribp_addr == $past(ribp_addr));
assert (ribp_wdata == $past(ribp_wdata));
assert (ribp_wstrb == $past(ribp_wstrb));
end
if (f_past_valid && $past(rst_n_i && rsp_valid && !rsp_ready)) begin
assert (rsp_valid);
@@ -75,7 +75,7 @@ module rib_adapter_formal;
assert (adapted_wstrb == $past(adapted_wstrb));
assert (adapted_wlast);
end
cover (legacy_valid && cmd_len == 2'd3 && legacy_addr == cmd_addr + 32'd12);
cover (ribp_valid && cmd_len == 2'd3 && ribp_addr == cmd_addr + 32'd12);
cover (rsp_valid && rsp_last && rsp_beat == 2'd3);
cover (adapted_w_valid && adapted_wlast);
end
rtl/mini/formal/rib2apb_formal.sv → rtl/mini/formal/ribp2apb_formal.sv
+4 -4
View File
@@ -22,7 +22,7 @@ module formal_apb_slave (
endmodule
module rib2apb_formal_design (
module ribp2apb_formal_design (
input logic clk_i,
output logic rst_n_i,
output logic f_past_valid,
@@ -37,7 +37,7 @@ module rib2apb_formal_design (
output logic [ 1:0] fsm_q
);
rib_if rib ();
ribp_if rib ();
apb4_pure_if archinfo ();
apb4_pure_if rng ();
apb4_pure_if uart ();
@@ -75,10 +75,10 @@ module rib2apb_formal_design (
formal_apb_slave u_tmr_slave (.apb(tmr));
formal_apb_slave u_user_ip_slave (.apb(user_ip));
rib2apb u_dut (
ribp2apb u_dut (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.rib (rib),
.ribp (rib),
.archinfo(archinfo),
.rng (rng),
.uart (uart),
rtl/mini/formal/rib2apb_formal_props.v → rtl/mini/formal/ribp2apb_formal_props.v
+2 -2
View File
@@ -8,7 +8,7 @@
// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
module rib2apb_formal;
module ribp2apb_formal;
localparam [1:0] FSM_SETP = 2'd1;
localparam [1:0] FSM_ENAB = 2'd2;
@@ -26,7 +26,7 @@ module rib2apb_formal;
wire xfer_ready;
wire [ 1:0] fsm_q;
rib2apb_formal_design u_design (
ribp2apb_formal_design u_design (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.f_past_valid(f_past_valid),
rtl/mini/formal/spill_register_formal_props.v
+9 -6
View File
@@ -9,8 +9,8 @@ module spill_register_formal;
wire [31:0] data_i, data_o;
reg [1:0] count;
wire push = valid_i && ready_o;
wire pop = valid_o && ready_i;
wire push = valid_i && ready_o && !flush_i;
wire pop = valid_o && ready_i && !flush_i;
spill_register_formal_design u_design (.*);
@@ -22,16 +22,19 @@ module spill_register_formal;
if (!rst_n_i) begin
count <= 2'd0;
end else begin
assume (!(flush_i && valid_i));
if (f_past_valid && $past(rst_n_i && valid_i && !ready_o)) begin
assume (valid_i);
assume (data_i == $past(data_i));
end
assert (count <= 2'd2);
assert (valid_o == (count != 2'd0));
assert (ready_o == (count != 2'd2));
if (f_past_valid && $past(rst_n_i && valid_o && !ready_i && !flush_i)) begin
assert (valid_o == (!flush_i && (count != 2'd0)));
assert (ready_o == (!flush_i && (count != 2'd2)));
if (flush_i) begin
assert (!valid_o);
assert (!ready_o);
end
if (f_past_valid && !flush_i && $past(rst_n_i && valid_o && !ready_i && !flush_i)) begin
assert (valid_o);
assert (data_o == $past(data_o));
end
rtl/mini/formal/sysctrl_formal.sv
+4 -4
View File
@@ -33,7 +33,7 @@ module sysctrl_formal_design (
output logic [31:0] fault_count
);
rib_if rib ();
ribp_if rib ();
sysctrl_if sysctrl ();
pll_ctrl_if pll_ctrl ();
@@ -65,7 +65,7 @@ module sysctrl_formal_design (
assign sysctrl.perf_mgmt_wait_i = '0;
assign sysctrl.perf_user_wait_i = '0;
assign sysctrl.perf_dma_wait_i = '0;
assign sysctrl.perf_rib_wait_i = '0;
assign sysctrl.perf_ribp_wait_i = '0;
assign sysctrl.perf_apb_wait_i = '0;
assign sysctrl.perf_sdram_wait_i = '0;
assign sysctrl.perf_psram_wait_i = '0;
@@ -106,14 +106,14 @@ module sysctrl_formal_design (
assign fault_addr_q = u_dut.s_fault_addr_q;
assign fault_count = u_dut.s_fault_count_q;
rib_sysctrl u_dut (
ribp_sysctrl u_dut (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.fault_valid_i (f_fault_valid),
.fault_addr_i (f_fault_addr),
.fault_wstrb_i (f_fault_wstrb),
.fault_reserved_i(f_fault_reserved),
.rib (rib),
.ribp (rib),
.sysctrl (sysctrl),
.pll_ctrl (pll_ctrl)
);
rtl/mini/integration/README.md
+2 -2
View File
@@ -5,11 +5,11 @@ that is not part of the software address-map ABI or the package pad map.
The topology generator validates rib RIB and APB target ownership against
`../address_map/memory_map.json` and emits generated SystemVerilog include
files for `ip_rib_wrapper.sv`, `ip_apb_wrapper.sv`, `rib2apb.sv`, and
files for `ip_ribp_wrapper.sv`, `ip_apb_wrapper.sv`, `ribp2apb.sv`, and
`retrosoc.sv`. The output retains scalar interface instances and ports, so it
does not depend on interface-array support in FPGA or netlist simulation tools.
The `rib_targets` list uses stable response slots. Every active rib
The `ribp_targets` list uses stable response slots. Every active RIBP
memory-map region must appear exactly once. Disabled targets keep their slot
and interface declaration but cannot own an address region.
rtl/mini/integration/clock_reset_domains.json
+4 -4
View File
@@ -53,11 +53,11 @@
"reset": "s_dvp_pclk_rst_n_sync",
"reset_source": "rst_n_i",
"reset_primitive": "rst_sync",
"path": "rtl/ip/rib/multimedia/dvp.sv",
"path": "rtl/ip/ribp/multimedia/dvp.sv",
"instance": "u_dvp_pclk_rst_sync",
"sta": {
"source_port": "gpio_10_io_pad",
"pin": "u_retrosoc.u_ip_rib_wrapper/u_rib_dvp.u_dvp_pclk_clk_buf/clk_o",
"pin": "u_retrosoc.u_ip_ribp_wrapper.u_rib_dvp.u_dvp_pclk_clk_buf/clk_o",
"period_ns": 41.666666667,
"async_group": "dvp"
}
@@ -85,7 +85,7 @@
"source": "system",
"destination": "dvp",
"primitive": "cdc_sync",
"path": "rtl/ip/rib/multimedia/dvp.sv",
"path": "rtl/ip/ribp/multimedia/dvp.sv",
"instance": "u_dvp_recven_cdc_sync"
},
{
@@ -93,7 +93,7 @@
"source": "dvp",
"destination": "system",
"primitive": "async_fifo",
"path": "rtl/ip/rib/multimedia/dvp.sv",
"path": "rtl/ip/ribp/multimedia/dvp.sv",
"instance": "u_rx_async_fifo"
}
]
rtl/mini/integration/generate_soc_topology.py
+75 -75
View File
@@ -18,25 +18,25 @@ SV_REFERENCE_RE = re.compile(r"[A-Za-z_][A-Za-z0-9_]*(?:\.[A-Za-z_][A-Za-z0-9_]*
SV_CONSTANT_RE = re.compile(r"(?:1'[bB][01]|'[01])$")
FABRIC_LINK_NAMES = ("mgmt", "user", "dma", "rib", "apb")
FABRIC_PROTOCOLS = {
"mgmt": "soc_legacy",
"user": "burst",
"dma": "burst",
"rib": "burst",
"apb": "legacy",
"mgmt": "ribl",
"user": "rib",
"dma": "rib",
"rib": "rib",
"apb": "ribp",
}
IRQ_GROUP_NAMES = ("rib", "apb")
IRQ_GROUP_NAMES = ("ribp", "apb")
IRQ_VECTOR_WIDTH = 32
COMPATIBILITY_IRQ_BINDINGS = (
("clint_software", "rib", 0, 0, "u_clint_if.sfr_irq_o"),
("clint_timer", "rib", 1, 1, "u_clint_if.tmr_irq_o"),
("uart0", "rib", 2, 2, "uart.irq_o"),
("timer0", "rib", 3, 3, "s_tim0_irq"),
("timer1", "rib", 4, 4, "s_tim1_irq"),
("psram", "rib", 5, 5, "psram.irq_o"),
("spisd", "rib", 6, 6, "spisd.irq_o"),
("i2c0", "rib", 7, 7, "i2c0.irq_o"),
("i2s", "rib", 8, 8, "i2s.irq_o"),
("xpi", "rib", 9, 9, "xpi.irq_o"),
("clint_software", "ribp", 0, 0, "u_clint_if.sfr_irq_o"),
("clint_timer", "ribp", 1, 1, "u_clint_if.tmr_irq_o"),
("uart0", "ribp", 2, 2, "uart.irq_o"),
("timer0", "ribp", 3, 3, "s_tim0_irq"),
("timer1", "ribp", 4, 4, "s_tim1_irq"),
("psram", "ribp", 5, 5, "psram.irq_o"),
("spisd", "ribp", 6, 6, "spisd.irq_o"),
("i2c0", "ribp", 7, 7, "i2c0.irq_o"),
("i2s", "ribp", 8, 8, "i2s.irq_o"),
("xpi", "ribp", 9, 9, "xpi.irq_o"),
("uart1", "apb", 0, 10, "uart.irq_o"),
("pwm", "apb", 1, 11, "pwm.irq_o"),
("ps2", "apb", 2, 12, "ps2.irq_o"),
@@ -48,7 +48,7 @@ COMPATIBILITY_IRQ_BINDINGS = (
@dataclass(frozen=True)
class RIBTarget:
class RIBPTarget:
slot: int
name: str
interface: str
@@ -181,76 +181,76 @@ def parse_regions(value: Any, field: str) -> tuple[str, ...]:
return regions
def parse_rib_targets(
def parse_ribp_targets(
value: Any, memory_regions: dict[str, dict[str, Any]]
) -> list[RIBTarget]:
) -> list[RIBPTarget]:
if not isinstance(value, list) or not value:
raise ValueError("rib_targets must be a non-empty list")
targets: list[RIBTarget] = []
raise ValueError("ribp_targets must be a non-empty list")
targets: list[RIBPTarget] = []
claimed_regions: set[str] = set()
names: set[str] = set()
interfaces: set[str] = set()
slots: set[int] = set()
for index, entry in enumerate(value):
target = require_object(entry, f"rib_targets[{index}]")
target = require_object(entry, f"ribp_targets[{index}]")
slot = target.get("slot")
if not isinstance(slot, int) or slot < 0:
raise ValueError(f"rib_targets[{index}].slot must be a non-negative integer")
name = require_identifier(target.get("name"), f"rib_targets[{index}].name")
raise ValueError(f"ribp_targets[{index}].slot must be a non-negative integer")
name = require_identifier(target.get("name"), f"ribp_targets[{index}].name")
interface = require_identifier(
target.get("interface"), f"rib_targets[{index}].interface"
target.get("interface"), f"ribp_targets[{index}].interface"
)
disabled = target.get("disabled", False)
if not isinstance(disabled, bool):
raise ValueError(f"rib_targets[{index}].disabled must be boolean")
raise ValueError(f"ribp_targets[{index}].disabled must be boolean")
if disabled:
if "regions" in target:
raise ValueError(f"rib_targets[{index}] is disabled but declares regions")
raise ValueError(f"ribp_targets[{index}] is disabled but declares regions")
regions: tuple[str, ...] = ()
else:
regions = parse_regions(target.get("regions"), f"rib_targets[{index}].regions")
regions = parse_regions(target.get("regions"), f"ribp_targets[{index}].regions")
for region_name in regions:
region = memory_regions.get(region_name)
if region is None:
raise ValueError(
f"rib_targets[{index}] references unknown region {region_name}"
f"ribp_targets[{index}] references unknown region {region_name}"
)
if region.get("route") != "rib" or region.get("kind") != "active":
if region.get("route") != "ribp" or region.get("kind") != "active":
raise ValueError(
f"rib_targets[{index}] region {region_name} is not an active rib region"
f"ribp_targets[{index}] region {region_name} is not an active RIBP region"
)
if region_name in claimed_regions:
raise ValueError(f"rib region {region_name} has multiple targets")
raise ValueError(f"RIBP region {region_name} has multiple targets")
claimed_regions.add(region_name)
if name in names:
raise ValueError(f"rib target name {name} is duplicated")
raise ValueError(f"RIBP target name {name} is duplicated")
if interface in interfaces:
raise ValueError(f"rib target interface {interface} is duplicated")
raise ValueError(f"RIBP target interface {interface} is duplicated")
if slot in slots:
raise ValueError(f"rib target slot {slot} is duplicated")
raise ValueError(f"RIBP target slot {slot} is duplicated")
names.add(name)
interfaces.add(interface)
slots.add(slot)
targets.append(RIBTarget(slot, name, interface, regions, disabled))
targets.append(RIBPTarget(slot, name, interface, regions, disabled))
ordered = sorted(targets, key=lambda item: item.slot)
if [target.slot for target in ordered] != list(range(len(ordered))):
raise ValueError("rib target slots must be contiguous from zero")
active_rib_regions = {
raise ValueError("RIBP target slots must be contiguous from zero")
active_ribp_regions = {
symbol
for symbol, region in memory_regions.items()
if region.get("route") == "rib" and region.get("kind") == "active"
if region.get("route") == "ribp" and region.get("kind") == "active"
}
if claimed_regions != active_rib_regions:
missing = sorted(active_rib_regions - claimed_regions)
extra = sorted(claimed_regions - active_rib_regions)
if claimed_regions != active_ribp_regions:
missing = sorted(active_ribp_regions - claimed_regions)
extra = sorted(claimed_regions - active_ribp_regions)
details: list[str] = []
if missing:
details.append(f"missing {', '.join(missing)}")
if extra:
details.append(f"extra {', '.join(extra)}")
raise ValueError(
f"rib target regions do not cover the memory map ({'; '.join(details)})"
f"RIBP target regions do not cover the memory map ({'; '.join(details)})"
)
return ordered
@@ -496,7 +496,7 @@ def validate_compatibility_irq_bindings(interrupts: list[Interrupt]) -> None:
def read_topology(
topology_path: Path, memory_map_path: Path
) -> tuple[
list[RIBTarget],
list[RIBPTarget],
list[ApbTarget],
list[FabricLink],
list[GpioFunction],
@@ -518,7 +518,7 @@ def read_topology(
interrupts = parse_interrupts(document.get("interrupts"), irq_groups, irq_vector_width)
validate_compatibility_irq_bindings(interrupts)
return (
parse_rib_targets(document.get("rib_targets"), memory_regions),
parse_ribp_targets(document.get("ribp_targets"), memory_regions),
parse_apb_targets(document.get("apb_targets"), memory_regions),
parse_fabric_links(document.get("fabric_links")),
parse_gpio_functions(document.get("gpio_alt_functions"), gpio_pins),
@@ -528,21 +528,21 @@ def read_topology(
)
def render_rib_interfaces(targets: list[RIBTarget]) -> str:
def render_ribp_interfaces(targets: list[RIBPTarget]) -> str:
lines = ["// Generated by rtl/mini/integration/generate_soc_topology.py; do not edit."]
lines.extend(f" rib_if {target.interface} ();" for target in targets)
lines.extend(f" ribp_if {target.interface} ();" for target in targets)
return "\n".join(lines) + "\n"
def render_region_select(region: str, memory_region: dict[str, Any]) -> str:
base = int(require_string(memory_region.get("base"), f"memory map region {region}.base"), 0)
if base == 0:
return f"(rib.addr <= `SOC_ADDR_{region}_END)"
return f"`SOC_ADDR_IS_{region}(rib.addr)"
return f"(ribp.addr <= `SOC_ADDR_{region}_END)"
return f"`SOC_ADDR_IS_{region}(ribp.addr)"
def render_rib_routes(
targets: list[RIBTarget], memory_regions: dict[str, dict[str, Any]]
def render_ribp_routes(
targets: list[RIBPTarget], memory_regions: dict[str, dict[str, Any]]
) -> str:
count = len(targets)
lines = ["// Generated by rtl/mini/integration/generate_soc_topology.py; do not edit."]
@@ -568,13 +568,13 @@ def render_rib_routes(
f"{render_region_select(region, memory_regions[region])};"
)
lines.append(
f" assign {target.interface}.valid = rib.valid && (|s_{target.name}_region_sel);"
f" assign {target.interface}.valid = ribp.valid && (|s_{target.name}_region_sel);"
)
lines.extend(
[
f" assign {target.interface}.addr = rib.addr;",
f" assign {target.interface}.wdata = rib.wdata;",
f" assign {target.interface}.wstrb = rib.wstrb;",
f" assign {target.interface}.addr = ribp.addr;",
f" assign {target.interface}.wdata = ribp.wdata;",
f" assign {target.interface}.wstrb = ribp.wstrb;",
f" assign s_slv_sel_d[{target.slot}] = {target.interface}.valid;",
f" assign s_slv_ready[{target.slot}] = {target.interface}.ready;",
f" assign s_slv_rdata[{target.slot}] = {target.interface}.rdata;",
@@ -590,13 +590,13 @@ def render_rib_routes(
" s_slv_sel_q",
" );",
"",
" assign rib.ready = |(s_slv_sel_q & s_slv_ready);",
" assign ribp.ready = |(s_slv_sel_q & s_slv_ready);",
"",
" always_comb begin",
" rib.rdata = '0;",
" ribp.rdata = '0;",
f" for (int index = 0; index < {count}; index++) begin",
" if (s_slv_sel_q[index]) begin",
" rib.rdata = rib.rdata | s_slv_rdata[index];",
" ribp.rdata = ribp.rdata | s_slv_rdata[index];",
" end",
" end",
" end",
@@ -665,13 +665,13 @@ def render_apb_request_routes(targets: list[ApbTarget]) -> str:
for target in targets:
lines.extend(
[
f" assign {target.name}.paddr = rib.addr;",
f" assign {target.name}.paddr = ribp.addr;",
f" assign {target.name}.pprot = '0;",
f" assign {target.name}.psel = s_xfer_valid && `SOC_ADDR_IS_{target.region}(rib.addr);",
f" assign {target.name}.psel = s_xfer_valid && `SOC_ADDR_IS_{target.region}(ribp.addr);",
f" assign {target.name}.penable = s_fsm_q == FSM_ENAB;",
f" assign {target.name}.pwrite = |rib.wstrb;",
f" assign {target.name}.pwdata = rib.wdata;",
f" assign {target.name}.pstrb = rib.wstrb;",
f" assign {target.name}.pwrite = |ribp.wstrb;",
f" assign {target.name}.pwdata = ribp.wdata;",
f" assign {target.name}.pstrb = ribp.wstrb;",
"",
]
)
@@ -681,7 +681,7 @@ def render_apb_request_routes(targets: list[ApbTarget]) -> str:
def render_apb_select_routes(targets: list[ApbTarget]) -> str:
lines = ["// Generated by rtl/mini/integration/generate_soc_topology.py; do not edit."]
lines.extend(
f" assign s_psel_comb[{target.slot}] = `SOC_ADDR_IS_{target.region}(rib.addr);"
f" assign s_psel_comb[{target.slot}] = `SOC_ADDR_IS_{target.region}(ribp.addr);"
for target in targets
)
return "\n".join(lines) + "\n"
@@ -706,9 +706,9 @@ def render_apb_response_mux(targets: list[ApbTarget]) -> str:
def render_fabric_interfaces(links: list[FabricLink]) -> str:
lines = ["// Generated by rtl/mini/integration/generate_soc_topology.py; do not edit."]
interface_types = {
"soc_legacy": "soc_rib_if",
"burst": "soc_rib_burst_if",
"legacy": "rib_if",
"ribl": "soc_ribl_if",
"rib": "soc_rib_if",
"ribp": "ribp_if",
}
lines.extend(
f" {interface_types[link.protocol]} {link.interface} ();"
@@ -730,11 +730,11 @@ def render_fabric_connection(links: list[FabricLink], name: str, port: str) -> s
def render_bus_fabric_connections(links: list[FabricLink]) -> str:
port_names = {
"mgmt": "mgmt_rib",
"mgmt": "mgmt_ribl",
"user": "user_rib",
"dma": "dma_rib",
"rib": "rib",
"apb": "apb_rib",
"apb": "apb_ribp",
}
interfaces = {link.name: link.interface for link in links}
lines = ["// Generated by rtl/mini/integration/generate_soc_topology.py; do not edit."]
@@ -876,8 +876,8 @@ def generate(topology_path: Path, memory_map_path: Path, output_dir: Path) -> No
) = read_topology(topology_path, memory_map_path)
memory_regions = read_memory_regions(memory_map_path)
rtl_dir = output_dir / "rtl"
atomic_write(rtl_dir / "soc_rib_interfaces.svh", render_rib_interfaces(targets))
atomic_write(rtl_dir / "soc_rib_routes.svh", render_rib_routes(targets, memory_regions))
atomic_write(rtl_dir / "soc_ribp_interfaces.svh", render_ribp_interfaces(targets))
atomic_write(rtl_dir / "soc_ribp_routes.svh", render_ribp_routes(targets, memory_regions))
atomic_write(rtl_dir / "soc_apb_interfaces.svh", render_apb_interfaces(apb_targets))
atomic_write(rtl_dir / "soc_apb_bridges.svh", render_apb_bridges(apb_targets))
atomic_write(rtl_dir / "soc_apb_ports.svh", render_apb_ports(apb_targets))
@@ -889,7 +889,7 @@ def generate(topology_path: Path, memory_map_path: Path, output_dir: Path) -> No
atomic_write(rtl_dir / "soc_fabric_interfaces.svh", render_fabric_interfaces(fabric_links))
atomic_write(
rtl_dir / "soc_mgmt_core_wrapper_fabric.svh",
render_fabric_connection(fabric_links, "mgmt", "rib"),
render_fabric_connection(fabric_links, "mgmt", "ribl"),
)
atomic_write(
rtl_dir / "soc_user_core_fabric.svh",
@@ -897,13 +897,13 @@ def generate(topology_path: Path, memory_map_path: Path, output_dir: Path) -> No
)
atomic_write(rtl_dir / "soc_bus_fabric.svh", render_bus_fabric_connections(fabric_links))
atomic_write(
rtl_dir / "soc_ip_rib_wrapper_fabric.svh",
render_fabric_connection(fabric_links, "rib", "burst_rib")
rtl_dir / "soc_ip_ribp_wrapper_fabric.svh",
render_fabric_connection(fabric_links, "rib", "rib")
+ render_fabric_connection(fabric_links, "dma", "dma_rib"),
)
atomic_write(
rtl_dir / "soc_ip_apb_wrapper_fabric.svh",
render_fabric_connection(fabric_links, "apb", "rib"),
render_fabric_connection(fabric_links, "apb", "ribp"),
)
atomic_write(rtl_dir / "soc_gpio_alt_bindings.svh", render_gpio_bindings(gpio_functions))
atomic_write(rtl_dir / "soc_irq_config.svh", render_irq_config(irq_vector_width, irq_groups))
rtl/mini/integration/generate_user_extensions.py
+39 -39
View File
@@ -84,8 +84,8 @@ def parse_targets(
instance = require_identifier(target.get("instance"), f"{field}[{index}].instance")
if field == "core_targets":
bus = target.get("bus")
if bus not in {"legacy", "burst"}:
raise ValueError(f"{field}[{index}].bus must be legacy or burst")
if bus not in {"ribp", "rib"}:
raise ValueError(f"{field}[{index}].bus must be ribp or rib")
reset = target.get("reset")
if reset not in {"sync", "async"}:
raise ValueError(f"{field}[{index}].reset must be sync or async")
@@ -130,21 +130,21 @@ def render_core_bindings(extensions: ExtensionMap) -> str:
for target in extensions.core_targets:
lines.extend(
[
f" soc_rib_burst_if u_user_{target.slot}_burst_rib_if ();",
f" soc_rib_if u_user_{target.slot}_rib_if ();",
f" logic [31:0] s_user_{target.slot}_irq;",
]
)
if target.bus == "legacy":
if target.bus == "ribp":
lines.extend(
[
f" rib_if u_user_{target.slot}_legacy_rib_if ();",
" rib_legacy_to_burst #(",
f" ribp_if u_user_{target.slot}_ribp_if ();",
" ribp2rib #(",
f" .SYNC_RESET(1'b{int(target.reset == 'sync')})",
f" ) u_user_{target.slot}_legacy_to_burst (",
f" ) u_user_{target.slot}_ribp2rib (",
" .clk_i (clk_i),",
f" .rst_n_i(rst_n_i && ~core_reset_i[{target.slot}]),",
f" .legacy(u_user_{target.slot}_legacy_rib_if),",
f" .burst (u_user_{target.slot}_burst_rib_if)",
f" .ribp (u_user_{target.slot}_ribp_if),",
f" .rib (u_user_{target.slot}_rib_if)",
" );",
]
)
@@ -166,14 +166,14 @@ def render_core_bindings(extensions: ExtensionMap) -> str:
for target in extensions.core_targets:
lines.extend(
[
f" u_user_{target.slot}_burst_rib_if.cmd_ready = '0;",
f" u_user_{target.slot}_burst_rib_if.w_ready = '0;",
f" u_user_{target.slot}_burst_rib_if.rsp_valid = '0;",
f" u_user_{target.slot}_burst_rib_if.rdata = '0;",
f" u_user_{target.slot}_burst_rib_if.resp_err = '0;",
f" u_user_{target.slot}_burst_rib_if.resp_code = '0;",
f" u_user_{target.slot}_burst_rib_if.rsp_beat = '0;",
f" u_user_{target.slot}_burst_rib_if.rsp_last = '0;",
f" u_user_{target.slot}_rib_if.cmd_ready = '0;",
f" u_user_{target.slot}_rib_if.w_ready = '0;",
f" u_user_{target.slot}_rib_if.rsp_valid = '0;",
f" u_user_{target.slot}_rib_if.rdata = '0;",
f" u_user_{target.slot}_rib_if.resp_err = '0;",
f" u_user_{target.slot}_rib_if.resp_code = '0;",
f" u_user_{target.slot}_rib_if.rsp_beat = '0;",
f" u_user_{target.slot}_rib_if.rsp_last = '0;",
f" s_user_{target.slot}_irq = '0;",
]
)
@@ -182,23 +182,23 @@ def render_core_bindings(extensions: ExtensionMap) -> str:
lines.extend(
[
f" {extensions.core_selector_width}'d{target.slot}: begin",
f" rib.cmd_valid = u_user_{target.slot}_burst_rib_if.cmd_valid;",
f" rib.cmd_addr = u_user_{target.slot}_burst_rib_if.cmd_addr;",
f" rib.cmd_write = u_user_{target.slot}_burst_rib_if.cmd_write;",
f" rib.cmd_len = u_user_{target.slot}_burst_rib_if.cmd_len;",
f" rib.w_valid = u_user_{target.slot}_burst_rib_if.w_valid;",
f" rib.wdata = u_user_{target.slot}_burst_rib_if.wdata;",
f" rib.wstrb = u_user_{target.slot}_burst_rib_if.wstrb;",
f" rib.wlast = u_user_{target.slot}_burst_rib_if.wlast;",
f" rib.rsp_ready = u_user_{target.slot}_burst_rib_if.rsp_ready;",
f" u_user_{target.slot}_burst_rib_if.cmd_ready = rib.cmd_ready;",
f" u_user_{target.slot}_burst_rib_if.w_ready = rib.w_ready;",
f" u_user_{target.slot}_burst_rib_if.rsp_valid = rib.rsp_valid;",
f" u_user_{target.slot}_burst_rib_if.rdata = rib.rdata;",
f" u_user_{target.slot}_burst_rib_if.resp_err = rib.resp_err;",
f" u_user_{target.slot}_burst_rib_if.resp_code = rib.resp_code;",
f" u_user_{target.slot}_burst_rib_if.rsp_beat = rib.rsp_beat;",
f" u_user_{target.slot}_burst_rib_if.rsp_last = rib.rsp_last;",
f" rib.cmd_valid = u_user_{target.slot}_rib_if.cmd_valid;",
f" rib.cmd_addr = u_user_{target.slot}_rib_if.cmd_addr;",
f" rib.cmd_write = u_user_{target.slot}_rib_if.cmd_write;",
f" rib.cmd_len = u_user_{target.slot}_rib_if.cmd_len;",
f" rib.w_valid = u_user_{target.slot}_rib_if.w_valid;",
f" rib.wdata = u_user_{target.slot}_rib_if.wdata;",
f" rib.wstrb = u_user_{target.slot}_rib_if.wstrb;",
f" rib.wlast = u_user_{target.slot}_rib_if.wlast;",
f" rib.rsp_ready = u_user_{target.slot}_rib_if.rsp_ready;",
f" u_user_{target.slot}_rib_if.cmd_ready = rib.cmd_ready;",
f" u_user_{target.slot}_rib_if.w_ready = rib.w_ready;",
f" u_user_{target.slot}_rib_if.rsp_valid = rib.rsp_valid;",
f" u_user_{target.slot}_rib_if.rdata = rib.rdata;",
f" u_user_{target.slot}_rib_if.resp_err = rib.resp_err;",
f" u_user_{target.slot}_rib_if.resp_code = rib.resp_code;",
f" u_user_{target.slot}_rib_if.rsp_beat = rib.rsp_beat;",
f" u_user_{target.slot}_rib_if.rsp_last = rib.rsp_last;",
f" s_user_{target.slot}_irq = irq_i;",
" end",
]
@@ -206,18 +206,18 @@ def render_core_bindings(extensions: ExtensionMap) -> str:
lines.extend([" default: ;", " endcase", " end", ""])
for target in extensions.core_targets:
interface = (
f"u_user_{target.slot}_legacy_rib_if"
if target.bus == "legacy"
else f"u_user_{target.slot}_burst_rib_if"
f"u_user_{target.slot}_ribp_if"
if target.bus == "ribp"
else f"u_user_{target.slot}_rib_if"
)
lines.extend(
[
f" // User core {target.slot} uses the {target.bus} RIB contract.",
f" // User core {target.slot} uses the {target.bus.upper()} contract.",
f" {target.module} #({target.slot}) {target.instance} (",
" .clk_i (clk_i),",
f" .rst_n_i(rst_n_i && ~core_reset_i[{target.slot}]),",
f" .irq_i (s_user_{target.slot}_irq),",
f" .rib ({interface})",
f" .{target.bus} ({interface})",
" );",
"",
]
rtl/mini/integration/soc_topology.json
+35 -35
View File
@@ -3,20 +3,20 @@
"gpio_pins": 32,
"irq_vector_width": 32,
"irq_groups": [
{"name": "rib", "width": 10, "top_signal": "s_rib_irq"},
{"name": "ribp", "width": 10, "top_signal": "s_ribp_irq"},
{"name": "apb", "width": 7, "top_signal": "s_apb_irq"}
],
"interrupts": [
{"name": "clint_software", "description": "CLINT machine software interrupt", "group": "rib", "group_bit": 0, "core_bit": 0, "signal": "u_clint_if.sfr_irq_o"},
{"name": "clint_timer", "description": "CLINT machine timer interrupt", "group": "rib", "group_bit": 1, "core_bit": 1, "signal": "u_clint_if.tmr_irq_o"},
{"name": "uart0", "description": "RIB UART0 interrupt", "group": "rib", "group_bit": 2, "core_bit": 2, "signal": "uart.irq_o"},
{"name": "timer0", "description": "RIB timer0 interrupt", "group": "rib", "group_bit": 3, "core_bit": 3, "signal": "s_tim0_irq"},
{"name": "timer1", "description": "RIB timer1 interrupt", "group": "rib", "group_bit": 4, "core_bit": 4, "signal": "s_tim1_irq"},
{"name": "psram", "description": "PSRAM controller interrupt", "group": "rib", "group_bit": 5, "core_bit": 5, "signal": "psram.irq_o"},
{"name": "spisd", "description": "SPI SD controller interrupt", "group": "rib", "group_bit": 6, "core_bit": 6, "signal": "spisd.irq_o"},
{"name": "i2c0", "description": "RIB I2C0 interrupt", "group": "rib", "group_bit": 7, "core_bit": 7, "signal": "i2c0.irq_o"},
{"name": "i2s", "description": "RIB I2S interrupt", "group": "rib", "group_bit": 8, "core_bit": 8, "signal": "i2s.irq_o"},
{"name": "xpi", "description": "XPI controller interrupt", "group": "rib", "group_bit": 9, "core_bit": 9, "signal": "xpi.irq_o"},
{"name": "clint_software", "description": "CLINT machine software interrupt", "group": "ribp", "group_bit": 0, "core_bit": 0, "signal": "u_clint_if.sfr_irq_o"},
{"name": "clint_timer", "description": "CLINT machine timer interrupt", "group": "ribp", "group_bit": 1, "core_bit": 1, "signal": "u_clint_if.tmr_irq_o"},
{"name": "uart0", "description": "RIBP UART0 interrupt", "group": "ribp", "group_bit": 2, "core_bit": 2, "signal": "uart.irq_o"},
{"name": "timer0", "description": "RIBP timer0 interrupt", "group": "ribp", "group_bit": 3, "core_bit": 3, "signal": "s_tim0_irq"},
{"name": "timer1", "description": "RIBP timer1 interrupt", "group": "ribp", "group_bit": 4, "core_bit": 4, "signal": "s_tim1_irq"},
{"name": "psram", "description": "PSRAM controller interrupt", "group": "ribp", "group_bit": 5, "core_bit": 5, "signal": "psram.irq_o"},
{"name": "spisd", "description": "SPI SD controller interrupt", "group": "ribp", "group_bit": 6, "core_bit": 6, "signal": "spisd.irq_o"},
{"name": "i2c0", "description": "RIBP I2C0 interrupt", "group": "ribp", "group_bit": 7, "core_bit": 7, "signal": "i2c0.irq_o"},
{"name": "i2s", "description": "RIBP I2S interrupt", "group": "ribp", "group_bit": 8, "core_bit": 8, "signal": "i2s.irq_o"},
{"name": "xpi", "description": "XPI controller interrupt", "group": "ribp", "group_bit": 9, "core_bit": 9, "signal": "xpi.irq_o"},
{"name": "uart1", "description": "APB UART1 interrupt", "group": "apb", "group_bit": 0, "core_bit": 10, "signal": "uart.irq_o"},
{"name": "pwm", "description": "APB PWM interrupt", "group": "apb", "group_bit": 1, "core_bit": 11, "signal": "pwm.irq_o"},
{"name": "ps2", "description": "APB PS2 interrupt", "group": "apb", "group_bit": 2, "core_bit": 12, "signal": "ps2.irq_o"},
@@ -25,32 +25,32 @@
{"name": "advanced_timer", "description": "APB advanced timer interrupt", "group": "apb", "group_bit": 5, "core_bit": 15, "signal": "u_tmr_if.irq_o"},
{"name": "reserved", "description": "Reserved interrupt slot", "group": "apb", "group_bit": 6, "core_bit": 16, "signal": "1'b0"}
],
"rib_targets": [
{"slot": 0, "name": "uart0", "interface": "u_uart_rib_if", "regions": ["RIB_UART0"]},
{"slot": 1, "name": "gpio", "interface": "u_gpio_rib_if", "regions": ["RIB_GPIO"]},
{"slot": 2, "name": "tim0", "interface": "u_tim0_rib_if", "regions": ["RIB_TIM0"]},
{"slot": 3, "name": "tim1", "interface": "u_tim1_rib_if", "regions": ["RIB_TIM1"]},
{"slot": 4, "name": "psram", "interface": "u_psram_rib_if", "regions": ["RIB_PSRAM", "PSRAM"]},
{"slot": 5, "name": "spisd", "interface": "u_spisd_rib_if", "regions": ["RIB_SPISD", "SPISD"]},
{"slot": 6, "name": "i2c0", "interface": "u_i2c0_rib_if", "regions": ["RIB_I2C0"]},
{"slot": 7, "name": "i2s", "interface": "u_i2s_rib_if", "regions": ["RIB_I2S"]},
{"slot": 8, "name": "onewire", "interface": "u_onewire_rib_if", "regions": ["RIB_ONEWIRE"]},
{"slot": 9, "name": "xpi", "interface": "u_xpi_rib_if", "regions": ["RIB_XPI", "FLASH", "XPI"]},
{"slot": 10, "name": "dma", "interface": "u_dma_rib_if", "regions": ["RIB_DMA"]},
{"slot": 11, "name": "sysctrl", "interface": "u_sysctrl_rib_if", "regions": ["RIB_SYSCTRL"]},
{"slot": 12, "name": "clint", "interface": "u_clint_rib_if", "regions": ["RIB_CLINT"]},
{"slot": 13, "name": "sdram", "interface": "u_sdram_rib_if", "regions": ["RIB_SDRAM", "SDRAM"]},
{"slot": 14, "name": "dvp", "interface": "u_dvp_rib_if", "regions": ["RIB_DVP"]},
{"slot": 15, "name": "sdio", "interface": "u_sdio_rib_if", "disabled": true},
{"slot": 16, "name": "opipsram", "interface": "u_opipsram_rib_if", "disabled": true},
{"slot": 17, "name": "i2c1", "interface": "u_i2c1_rib_if", "regions": ["RIB_I2C1"]}
"ribp_targets": [
{"slot": 0, "name": "uart0", "interface": "u_uart_ribp_if", "regions": ["RIBP_UART0"]},
{"slot": 1, "name": "gpio", "interface": "u_gpio_ribp_if", "regions": ["RIBP_GPIO"]},
{"slot": 2, "name": "tim0", "interface": "u_tim0_ribp_if", "regions": ["RIBP_TIM0"]},
{"slot": 3, "name": "tim1", "interface": "u_tim1_ribp_if", "regions": ["RIBP_TIM1"]},
{"slot": 4, "name": "psram", "interface": "u_psram_ribp_if", "regions": ["RIBP_PSRAM", "PSRAM"]},
{"slot": 5, "name": "spisd", "interface": "u_spisd_ribp_if", "regions": ["RIBP_SPISD", "SPISD"]},
{"slot": 6, "name": "i2c0", "interface": "u_i2c0_ribp_if", "regions": ["RIBP_I2C0"]},
{"slot": 7, "name": "i2s", "interface": "u_i2s_ribp_if", "regions": ["RIBP_I2S"]},
{"slot": 8, "name": "onewire", "interface": "u_onewire_ribp_if", "regions": ["RIBP_ONEWIRE"]},
{"slot": 9, "name": "xpi", "interface": "u_xpi_ribp_if", "regions": ["RIBP_XPI", "FLASH", "XPI"]},
{"slot": 10, "name": "dma", "interface": "u_dma_ribp_if", "regions": ["RIBP_DMA"]},
{"slot": 11, "name": "sysctrl", "interface": "u_sysctrl_ribp_if", "regions": ["RIBP_SYSCTRL"]},
{"slot": 12, "name": "clint", "interface": "u_clint_ribp_if", "regions": ["RIBP_CLINT"]},
{"slot": 13, "name": "sdram", "interface": "u_sdram_ribp_if", "regions": ["RIBP_SDRAM", "SDRAM"]},
{"slot": 14, "name": "dvp", "interface": "u_dvp_ribp_if", "regions": ["RIBP_DVP"]},
{"slot": 15, "name": "sdio", "interface": "u_sdio_ribp_if", "disabled": true},
{"slot": 16, "name": "opipsram", "interface": "u_opipsram_ribp_if", "disabled": true},
{"slot": 17, "name": "i2c1", "interface": "u_i2c1_ribp_if", "regions": ["RIBP_I2C1"]}
],
"fabric_links": [
{"name": "mgmt", "interface": "u_mgmt_rib_if", "protocol": "soc_legacy"},
{"name": "user", "interface": "u_user_rib_if", "protocol": "burst"},
{"name": "dma", "interface": "u_dma_rib_if", "protocol": "burst"},
{"name": "rib", "interface": "u_rib_if", "protocol": "burst"},
{"name": "apb", "interface": "u_apb_rib_if", "protocol": "legacy"}
{"name": "mgmt", "interface": "u_mgmt_ribl_if", "protocol": "ribl"},
{"name": "user", "interface": "u_user_rib_if", "protocol": "rib"},
{"name": "dma", "interface": "u_dma_rib_if", "protocol": "rib"},
{"name": "rib", "interface": "u_rib_if", "protocol": "rib"},
{"name": "apb", "interface": "u_apb_ribp_if", "protocol": "ribp"}
],
"apb_targets": [
{"slot": 0, "name": "archinfo", "timed_interface": "u_archinfo_apb_if", "pure_interface": "u_archinfo_apb_pure_if", "region": "APB_ARCHINFO"},
rtl/mini/integration/user_extensions.json
+6 -6
View File
@@ -4,12 +4,12 @@
"ip_selector_width": 8,
"gpio_width": 32,
"core_targets": [
{"slot": 0, "module": "user_core_design_username1", "instance": "u_user_core_design_username1", "bus": "legacy", "reset": "sync"},
{"slot": 1, "module": "user_core_design_username2", "instance": "u_user_core_design_username2", "bus": "legacy", "reset": "sync"},
{"slot": 2, "module": "user_core_design_username3", "instance": "u_user_core_design_username3", "bus": "legacy", "reset": "async"},
{"slot": 3, "module": "user_core_design_username4", "instance": "u_user_core_design_username4", "bus": "legacy", "reset": "async"},
{"slot": 4, "module": "user_core_design_username5", "instance": "u_user_core_design_username5", "bus": "legacy", "reset": "async"},
{"slot": 5, "module": "user_core_design_username6", "instance": "u_user_core_design_username6", "bus": "legacy", "reset": "async"}
{"slot": 0, "module": "user_core_design_username1", "instance": "u_user_core_design_username1", "bus": "ribp", "reset": "sync"},
{"slot": 1, "module": "user_core_design_username2", "instance": "u_user_core_design_username2", "bus": "ribp", "reset": "sync"},
{"slot": 2, "module": "user_core_design_username3", "instance": "u_user_core_design_username3", "bus": "ribp", "reset": "async"},
{"slot": 3, "module": "user_core_design_username4", "instance": "u_user_core_design_username4", "bus": "ribp", "reset": "async"},
{"slot": 4, "module": "user_core_design_username5", "instance": "u_user_core_design_username5", "bus": "ribp", "reset": "async"},
{"slot": 5, "module": "user_core_design_username6", "instance": "u_user_core_design_username6", "bus": "ribp", "reset": "async"}
],
"ip_targets": [
{"slot": 1, "module": "user_ip_design_username1", "instance": "u_user_ip_design_username1"},
rtl/mini/mk/formal.mk
+18 -16
View File
@@ -6,7 +6,7 @@ FORMAL_SOLVER_DIR := $(FORMAL_DIR)/bin
FORMAL_SOLVER_WRAPPER := $(FORMAL_SOLVER_DIR)/bitwuzla
FORMAL_DEPTH ?= 20
FORMAL_TIMEOUT ?= 60
FORMAL_TARGETS := bus rib_adapter spill_register rib2apb sysctrl pll_rcu gpio_user
FORMAL_TARGETS := bus rib_adapter spill_register ribp2apb sysctrl pll_rcu gpio_user
FORMAL_FILELIST_GENERATOR := $(RTL_PATH)/formal/generate_formal_filelist.py
FORMAL_SBY_GENERATOR := $(RTL_PATH)/formal/generate_sby_config.py
FORMAL_RESULT_GENERATOR := $(RTL_PATH)/formal/formal_results.py
@@ -16,8 +16,8 @@ FORMAL_SOURCE_FILES := $(RTL_PATH)/formal/bus_formal.sv \
$(RTL_PATH)/formal/rib_adapter_formal_props.v \
$(RTL_PATH)/formal/spill_register_formal.sv \
$(RTL_PATH)/formal/spill_register_formal_props.v \
$(RTL_PATH)/formal/rib2apb_formal.sv \
$(RTL_PATH)/formal/rib2apb_formal_props.v \
$(RTL_PATH)/formal/ribp2apb_formal.sv \
$(RTL_PATH)/formal/ribp2apb_formal_props.v \
$(RTL_PATH)/formal/sysctrl_formal.sv \
$(RTL_PATH)/formal/sysctrl_formal_props.v \
$(RTL_PATH)/formal/pll_rcu_formal.sv \
@@ -25,20 +25,22 @@ FORMAL_SOURCE_FILES := $(RTL_PATH)/formal/bus_formal.sv \
$(RTL_PATH)/formal/gpio_user_formal.sv \
$(RTL_PATH)/formal/gpio_user_formal_props.v \
$(RTL_PATH)/top/bus.sv \
$(RTL_PATH)/top/soc_rib_burst_error_slave.sv \
$(RTL_PATH)/top/soc_rib_burst_if.sv \
$(RTL_PATH)/top/soc_rib_burst_ram.sv \
$(RTL_PATH)/top/soc_rib_burst_to_legacy.sv \
$(RTL_PATH)/top/soc_rib_legacy_to_burst.sv \
$(ROOT_PATH)/rtl/ip/rib/interconnect/rib2apb.sv \
$(ROOT_PATH)/rtl/ip/rib/interconnect/rib_regslice.sv \
$(ROOT_PATH)/rtl/ip/rib/peripheral/gpio.sv \
$(ROOT_PATH)/rtl/ip/rib/peripheral/pll_ctrl_if.sv \
$(ROOT_PATH)/rtl/ip/rib/peripheral/sysctrl.sv \
$(RTL_PATH)/top/soc_rib_error_slave.sv \
$(RTL_PATH)/top/soc_ribl_if.sv \
$(RTL_PATH)/top/soc_rib_if.sv \
$(RTL_PATH)/top/soc_rib_ram.sv \
$(RTL_PATH)/top/soc_rib2ribp.sv \
$(RTL_PATH)/top/soc_ribl2rib.sv \
$(ROOT_PATH)/rtl/ip/ribp/interconnect/ribp2apb.sv \
$(ROOT_PATH)/rtl/ip/ribp/interconnect/ribp_regslice.sv \
$(ROOT_PATH)/rtl/ip/ribp/peripheral/gpio.sv \
$(ROOT_PATH)/rtl/ip/ribp/peripheral/pll_ctrl_if.sv \
$(ROOT_PATH)/rtl/ip/ribp/peripheral/sysctrl.sv \
$(RTL_PATH)/top/rcu.sv \
$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/interface/rib_if.sv \
$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/interface/ribp_if.sv \
$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/interface/apb4_pure_if.sv \
$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv \
$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/cdc/cdc_rst_ctrlr.sv \
$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv \
$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/utils/edge_det.sv \
$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/utils/register.sv \
@@ -119,7 +121,7 @@ formal-rib-adapter: $(FORMAL_DIR)/rib_adapter/.stamp | manifest
formal-spill-register: $(FORMAL_DIR)/spill_register/.stamp | manifest
formal-rib2apb: $(FORMAL_DIR)/rib2apb/.stamp | manifest
formal-ribp2apb: $(FORMAL_DIR)/ribp2apb/.stamp | manifest
formal-sysctrl: $(FORMAL_DIR)/sysctrl/.stamp | manifest
@@ -133,4 +135,4 @@ formal-doctor:
formal-clean:
python3 $(ROOT_PATH)/scripts/clean.py --root $(ROOT_PATH) --path $(FORMAL_DIR)
.PHONY: formal formal-bus formal-rib-adapter formal-spill-register formal-rib2apb formal-sysctrl formal-pll-rcu formal-gpio-user formal-doctor formal-clean
.PHONY: formal formal-bus formal-rib-adapter formal-spill-register formal-ribp2apb formal-sysctrl formal-pll-rcu formal-gpio-user formal-doctor formal-clean
rtl/mini/top/ahbl2soc_rib.sv → rtl/mini/top/ahbl2soc_ribl.sv
+27 -27
View File
@@ -11,10 +11,10 @@
`include "soc_rib_defs.svh"
// Management-core AHB-Lite to SoC RIB bridge. It is intentionally separate
// from the managed-compatible ahbl2rib used by externally supplied user cores.
module ahbl2soc_rib (
ahbl_if.slave ahbl,
soc_rib_if.master rib
// from the managed-compatible ahbl2ribp used by externally supplied user cores.
module ahbl2soc_ribl (
ahbl_if.slave ahbl,
soc_ribl_if.master ribl
);
localparam logic [1:0] AHBL_TRANS_NSEQ = 2'b10;
@@ -31,49 +31,49 @@ module ahbl2soc_rib (
logic s_hwrite_d, s_hwrite_q;
logic [2:0] s_hsize_d, s_hsize_q;
assign ahbl.hready = s_fsm_q == STATE_IDLE || rib.ready;
assign ahbl.hresp = rib.ready && rib.resp_err ? AHBL_RESP_ERROR : AHBL_RESP_OKAY;
assign ahbl.hrdata = rib.rdata;
assign rib.valid = s_fsm_q != STATE_IDLE;
assign rib.addr = {s_haddr_q[31:2], 2'b00};
assign ahbl.hready = s_fsm_q == STATE_IDLE || ribl.ready;
assign ahbl.hresp = ribl.ready && ribl.resp_err ? AHBL_RESP_ERROR : AHBL_RESP_OKAY;
assign ahbl.hrdata = ribl.rdata;
assign ribl.valid = s_fsm_q != STATE_IDLE;
assign ribl.addr = {s_haddr_q[31:2], 2'b00};
always_comb begin
rib.wstrb = '0;
rib.wdata = '0;
ribl.wstrb = '0;
ribl.wdata = '0;
if (s_hwrite_q) begin
unique case (s_hsize_q)
AHBL_SIZE_BYTE: begin
unique case (s_haddr_q[1:0])
2'd0: begin
rib.wstrb = 4'b0001;
rib.wdata = {24'd0, ahbl.hwdata[7:0]};
ribl.wstrb = 4'b0001;
ribl.wdata = {24'd0, ahbl.hwdata[7:0]};
end
2'd1: begin
rib.wstrb = 4'b0010;
rib.wdata = {16'd0, ahbl.hwdata[7:0], 8'd0};
ribl.wstrb = 4'b0010;
ribl.wdata = {16'd0, ahbl.hwdata[7:0], 8'd0};
end
2'd2: begin
rib.wstrb = 4'b0100;
rib.wdata = {8'd0, ahbl.hwdata[7:0], 16'd0};
ribl.wstrb = 4'b0100;
ribl.wdata = {8'd0, ahbl.hwdata[7:0], 16'd0};
end
default: begin
rib.wstrb = 4'b1000;
rib.wdata = {ahbl.hwdata[7:0], 24'd0};
ribl.wstrb = 4'b1000;
ribl.wdata = {ahbl.hwdata[7:0], 24'd0};
end
endcase
end
AHBL_SIZE_HWRD: begin
if (s_haddr_q[1]) begin
rib.wstrb = 4'b1100;
rib.wdata = {ahbl.hwdata[15:0], 16'd0};
ribl.wstrb = 4'b1100;
ribl.wdata = {ahbl.hwdata[15:0], 16'd0};
end else begin
rib.wstrb = 4'b0011;
rib.wdata = {16'd0, ahbl.hwdata[15:0]};
ribl.wstrb = 4'b0011;
ribl.wdata = {16'd0, ahbl.hwdata[15:0]};
end
end
default: begin
rib.wstrb = 4'b1111;
rib.wdata = ahbl.hwdata;
ribl.wstrb = 4'b1111;
ribl.wdata = ahbl.hwdata;
end
endcase
end
@@ -94,7 +94,7 @@ module ahbl2soc_rib (
end
end
STATE_DATA: begin
if (!rib.ready) begin
if (!ribl.ready) begin
s_fsm_d = STATE_WAIT;
end else if (ahbl.htrans == AHBL_TRANS_NSEQ) begin
s_haddr_d = ahbl.haddr;
@@ -105,7 +105,7 @@ module ahbl2soc_rib (
end
end
STATE_WAIT: begin
if (rib.ready) begin
if (ribl.ready) begin
if (ahbl.htrans == AHBL_TRANS_NSEQ) begin
s_fsm_d = STATE_DATA;
s_haddr_d = ahbl.haddr;
rtl/mini/top/bus.sv
+238 -238
View File
@@ -18,13 +18,13 @@ module bus (
`ifdef HAVE_SRAM_IF
ram_if.master ram,
`endif
soc_rib_if.slave mgmt_rib,
soc_rib_burst_if.slave user_rib,
soc_rib_burst_if.slave dma_rib,
soc_ribl_if.slave mgmt_ribl,
soc_rib_if.slave user_rib,
soc_rib_if.slave dma_rib,
input logic user_bus_enable_i,
output logic user_bus_idle_o,
soc_rib_burst_if.master rib,
rib_if.master apb_rib,
soc_rib_if.master rib,
ribp_if.master apb_ribp,
input logic apb_resp_err_i,
input logic perf_enable_i,
input logic perf_clear_i,
@@ -38,7 +38,7 @@ module bus (
output logic [63:0] perf_mgmt_wait_o,
output logic [63:0] perf_user_wait_o,
output logic [63:0] perf_dma_wait_o,
output logic [63:0] perf_rib_wait_o,
output logic [63:0] perf_ribp_wait_o,
output logic [63:0] perf_apb_wait_o,
output logic [63:0] perf_sdram_wait_o,
output logic [63:0] perf_psram_wait_o,
@@ -50,16 +50,16 @@ module bus (
localparam logic [1:0] MSTR_USER = 2'd1;
localparam logic [1:0] MSTR_DMA = 2'd2;
localparam logic [1:0] TARGET_RIB = 2'd0;
localparam logic [1:0] TARGET_RIBP = 2'd0;
localparam logic [1:0] TARGET_APB = 2'd1;
localparam logic [1:0] TARGET_RAM = 2'd2;
localparam logic [1:0] TARGET_FAULT = 2'd3;
soc_rib_burst_if u_mgmt_burst_if ();
soc_rib_burst_if u_mstr_burst_if ();
soc_rib_burst_if u_apb_burst_if ();
soc_rib_burst_if u_ram_burst_if ();
soc_rib_burst_if u_fault_burst_if ();
soc_rib_if u_mgmt_rib_if ();
soc_rib_if u_mstr_rib_if ();
soc_rib_if u_apb_rib_if ();
soc_rib_if u_ram_rib_if ();
soc_rib_if u_fault_rib_if ();
logic s_mstr_lock_d, s_mstr_lock_q;
logic s_cmd_accepted_d, s_cmd_accepted_q;
@@ -68,7 +68,7 @@ module bus (
logic [1:0] s_target_d, s_target_q;
logic s_user_request;
logic s_terminal_rsp;
logic s_rib_sel, s_apb_sel, s_ram_sel, s_fault_sel;
logic s_ribp_sel, s_apb_sel, s_ram_sel, s_fault_sel;
logic s_access_denied, s_burst_legal, s_length_legal;
logic s_user_access_allowed;
logic [31:0] s_last_addr;
@@ -85,58 +85,58 @@ module bus (
logic [63:0] s_perf_mgmt_wait_d, s_perf_mgmt_wait_q;
logic [63:0] s_perf_user_wait_d, s_perf_user_wait_q;
logic [63:0] s_perf_dma_wait_d, s_perf_dma_wait_q;
logic [63:0] s_perf_rib_wait_d, s_perf_rib_wait_q;
logic [63:0] s_perf_ribp_wait_d, s_perf_ribp_wait_q;
logic [63:0] s_perf_apb_wait_d, s_perf_apb_wait_q;
logic [63:0] s_perf_sdram_wait_d, s_perf_sdram_wait_q;
logic [63:0] s_perf_psram_wait_d, s_perf_psram_wait_q;
logic [63:0] s_perf_flash_wait_d, s_perf_flash_wait_q;
soc_rib_legacy_to_burst u_mgmt_legacy_to_burst (
soc_ribl2rib u_mgmt_ribl2rib (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.legacy (mgmt_rib),
.burst (u_mgmt_burst_if)
.ribl (mgmt_ribl),
.rib (u_mgmt_rib_if)
);
soc_rib_burst_to_legacy u_apb_burst_to_legacy (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.legacy_resp_err_i (apb_resp_err_i),
.legacy_resp_code_i(`SOC_RIB_RESP_SLVERR),
.burst (u_apb_burst_if),
.legacy (apb_rib)
soc_rib2ribp u_apb_rib2ribp (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.ribp_resp_err_i (apb_resp_err_i),
.ribp_resp_code_i(`SOC_RIB_RESP_SLVERR),
.rib (u_apb_rib_if),
.ribp (apb_ribp)
);
soc_rib_burst_error_slave u_fault_slave (
soc_rib_error_slave u_fault_slave (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.error_code_i(s_fault_code),
.burst (u_fault_burst_if)
.rib (u_fault_rib_if)
);
`ifdef HAVE_SRAM_IF
soc_rib_burst_ram u_ram_slave (
soc_rib_ram u_ram_slave (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.burst (u_ram_burst_if),
.rib (u_ram_rib_if),
.ram (ram)
);
`else
assign u_ram_burst_if.cmd_ready = 1'b0;
assign u_ram_burst_if.w_ready = 1'b0;
assign u_ram_burst_if.rsp_valid = 1'b0;
assign u_ram_burst_if.rdata = '0;
assign u_ram_burst_if.resp_err = 1'b0;
assign u_ram_burst_if.resp_code = `SOC_RIB_RESP_OK;
assign u_ram_burst_if.rsp_beat = '0;
assign u_ram_burst_if.rsp_last = 1'b0;
assign u_ram_rib_if.cmd_ready = 1'b0;
assign u_ram_rib_if.w_ready = 1'b0;
assign u_ram_rib_if.rsp_valid = 1'b0;
assign u_ram_rib_if.rdata = '0;
assign u_ram_rib_if.resp_err = 1'b0;
assign u_ram_rib_if.resp_code = `SOC_RIB_RESP_OK;
assign u_ram_rib_if.rsp_beat = '0;
assign u_ram_rib_if.rsp_last = 1'b0;
`endif
assign s_user_request = user_bus_enable_i && user_rib.cmd_valid;
assign user_bus_idle_o = ~s_mstr_lock_q || (s_mstr_id_q != MSTR_USER);
assign s_terminal_rsp = s_cmd_accepted_q && u_mstr_burst_if.rsp_valid &&
u_mstr_burst_if.rsp_ready &&
u_mstr_burst_if.rsp_last;
assign s_terminal_rsp = s_cmd_accepted_q && u_mstr_rib_if.rsp_valid &&
u_mstr_rib_if.rsp_ready &&
u_mstr_rib_if.rsp_last;
always_comb begin
s_mstr_lock_d = s_mstr_lock_q;
@@ -145,7 +145,7 @@ module bus (
if (~s_mstr_lock_q) begin
unique case (s_mstr_rr_q)
MSTR_MGMT: begin
if (u_mgmt_burst_if.cmd_valid) begin
if (u_mgmt_rib_if.cmd_valid) begin
s_mstr_lock_d = 1'b1;
s_mstr_id_d = MSTR_MGMT;
end else if (s_user_request) begin
@@ -163,7 +163,7 @@ module bus (
end else if (dma_rib.cmd_valid) begin
s_mstr_lock_d = 1'b1;
s_mstr_id_d = MSTR_DMA;
end else if (u_mgmt_burst_if.cmd_valid) begin
end else if (u_mgmt_rib_if.cmd_valid) begin
s_mstr_lock_d = 1'b1;
s_mstr_id_d = MSTR_MGMT;
end
@@ -172,7 +172,7 @@ module bus (
if (dma_rib.cmd_valid) begin
s_mstr_lock_d = 1'b1;
s_mstr_id_d = MSTR_DMA;
end else if (u_mgmt_burst_if.cmd_valid) begin
end else if (u_mgmt_rib_if.cmd_valid) begin
s_mstr_lock_d = 1'b1;
s_mstr_id_d = MSTR_MGMT;
end else if (s_user_request) begin
@@ -212,7 +212,7 @@ module bus (
always_comb begin
s_cmd_accepted_d = s_cmd_accepted_q;
if (u_mstr_burst_if.cmd_valid && u_mstr_burst_if.cmd_ready) begin
if (u_mstr_rib_if.cmd_valid && u_mstr_rib_if.cmd_ready) begin
s_cmd_accepted_d = 1'b1;
end else if (s_terminal_rsp) begin
s_cmd_accepted_d = 1'b0;
@@ -227,181 +227,181 @@ module bus (
// Master mux. The grant is held until the terminal response is consumed.
always_comb begin
u_mstr_burst_if.cmd_valid = 1'b0;
u_mstr_burst_if.cmd_addr = '0;
u_mstr_burst_if.cmd_write = 1'b0;
u_mstr_burst_if.cmd_len = `SOC_RIB_BURST_INCR1;
u_mstr_burst_if.w_valid = 1'b0;
u_mstr_burst_if.wdata = '0;
u_mstr_burst_if.wstrb = '0;
u_mstr_burst_if.wlast = 1'b0;
u_mstr_burst_if.rsp_ready = 1'b0;
u_mstr_rib_if.cmd_valid = 1'b0;
u_mstr_rib_if.cmd_addr = '0;
u_mstr_rib_if.cmd_write = 1'b0;
u_mstr_rib_if.cmd_len = `SOC_RIB_LEN_INCR1;
u_mstr_rib_if.w_valid = 1'b0;
u_mstr_rib_if.wdata = '0;
u_mstr_rib_if.wstrb = '0;
u_mstr_rib_if.wlast = 1'b0;
u_mstr_rib_if.rsp_ready = 1'b0;
if (s_mstr_lock_q) begin
unique case (s_mstr_id_q)
MSTR_MGMT: begin
u_mstr_burst_if.cmd_valid = u_mgmt_burst_if.cmd_valid;
u_mstr_burst_if.cmd_addr = u_mgmt_burst_if.cmd_addr;
u_mstr_burst_if.cmd_write = u_mgmt_burst_if.cmd_write;
u_mstr_burst_if.cmd_len = u_mgmt_burst_if.cmd_len;
u_mstr_burst_if.w_valid = u_mgmt_burst_if.w_valid;
u_mstr_burst_if.wdata = u_mgmt_burst_if.wdata;
u_mstr_burst_if.wstrb = u_mgmt_burst_if.wstrb;
u_mstr_burst_if.wlast = u_mgmt_burst_if.wlast;
u_mstr_burst_if.rsp_ready = u_mgmt_burst_if.rsp_ready;
u_mstr_rib_if.cmd_valid = u_mgmt_rib_if.cmd_valid;
u_mstr_rib_if.cmd_addr = u_mgmt_rib_if.cmd_addr;
u_mstr_rib_if.cmd_write = u_mgmt_rib_if.cmd_write;
u_mstr_rib_if.cmd_len = u_mgmt_rib_if.cmd_len;
u_mstr_rib_if.w_valid = u_mgmt_rib_if.w_valid;
u_mstr_rib_if.wdata = u_mgmt_rib_if.wdata;
u_mstr_rib_if.wstrb = u_mgmt_rib_if.wstrb;
u_mstr_rib_if.wlast = u_mgmt_rib_if.wlast;
u_mstr_rib_if.rsp_ready = u_mgmt_rib_if.rsp_ready;
end
MSTR_USER: begin
u_mstr_burst_if.cmd_valid = user_rib.cmd_valid;
u_mstr_burst_if.cmd_addr = user_rib.cmd_addr;
u_mstr_burst_if.cmd_write = user_rib.cmd_write;
u_mstr_burst_if.cmd_len = user_rib.cmd_len;
u_mstr_burst_if.w_valid = user_rib.w_valid;
u_mstr_burst_if.wdata = user_rib.wdata;
u_mstr_burst_if.wstrb = user_rib.wstrb;
u_mstr_burst_if.wlast = user_rib.wlast;
u_mstr_burst_if.rsp_ready = user_rib.rsp_ready;
u_mstr_rib_if.cmd_valid = user_rib.cmd_valid;
u_mstr_rib_if.cmd_addr = user_rib.cmd_addr;
u_mstr_rib_if.cmd_write = user_rib.cmd_write;
u_mstr_rib_if.cmd_len = user_rib.cmd_len;
u_mstr_rib_if.w_valid = user_rib.w_valid;
u_mstr_rib_if.wdata = user_rib.wdata;
u_mstr_rib_if.wstrb = user_rib.wstrb;
u_mstr_rib_if.wlast = user_rib.wlast;
u_mstr_rib_if.rsp_ready = user_rib.rsp_ready;
end
default: begin
u_mstr_burst_if.cmd_valid = dma_rib.cmd_valid;
u_mstr_burst_if.cmd_addr = dma_rib.cmd_addr;
u_mstr_burst_if.cmd_write = dma_rib.cmd_write;
u_mstr_burst_if.cmd_len = dma_rib.cmd_len;
u_mstr_burst_if.w_valid = dma_rib.w_valid;
u_mstr_burst_if.wdata = dma_rib.wdata;
u_mstr_burst_if.wstrb = dma_rib.wstrb;
u_mstr_burst_if.wlast = dma_rib.wlast;
u_mstr_burst_if.rsp_ready = dma_rib.rsp_ready;
u_mstr_rib_if.cmd_valid = dma_rib.cmd_valid;
u_mstr_rib_if.cmd_addr = dma_rib.cmd_addr;
u_mstr_rib_if.cmd_write = dma_rib.cmd_write;
u_mstr_rib_if.cmd_len = dma_rib.cmd_len;
u_mstr_rib_if.w_valid = dma_rib.w_valid;
u_mstr_rib_if.wdata = dma_rib.wdata;
u_mstr_rib_if.wstrb = dma_rib.wstrb;
u_mstr_rib_if.wlast = dma_rib.wlast;
u_mstr_rib_if.rsp_ready = dma_rib.rsp_ready;
end
endcase
end
end
// Responses are visible only to the granted master.
assign u_mgmt_burst_if.cmd_ready = s_mstr_lock_q && (s_mstr_id_q == MSTR_MGMT) ?
u_mstr_burst_if.cmd_ready : 1'b0;
assign u_mgmt_burst_if.w_ready = s_mstr_lock_q && (s_mstr_id_q == MSTR_MGMT) ?
u_mstr_burst_if.w_ready : 1'b0;
assign u_mgmt_burst_if.rsp_valid = s_mstr_lock_q && (s_mstr_id_q == MSTR_MGMT) ?
u_mstr_burst_if.rsp_valid : 1'b0;
assign u_mgmt_burst_if.rdata = u_mstr_burst_if.rdata;
assign u_mgmt_burst_if.resp_err = u_mstr_burst_if.resp_err;
assign u_mgmt_burst_if.resp_code = u_mstr_burst_if.resp_code;
assign u_mgmt_burst_if.rsp_beat = u_mstr_burst_if.rsp_beat;
assign u_mgmt_burst_if.rsp_last = u_mstr_burst_if.rsp_last;
assign u_mgmt_rib_if.cmd_ready = s_mstr_lock_q && (s_mstr_id_q == MSTR_MGMT) ?
u_mstr_rib_if.cmd_ready : 1'b0;
assign u_mgmt_rib_if.w_ready = s_mstr_lock_q && (s_mstr_id_q == MSTR_MGMT) ?
u_mstr_rib_if.w_ready : 1'b0;
assign u_mgmt_rib_if.rsp_valid = s_mstr_lock_q && (s_mstr_id_q == MSTR_MGMT) ?
u_mstr_rib_if.rsp_valid : 1'b0;
assign u_mgmt_rib_if.rdata = u_mstr_rib_if.rdata;
assign u_mgmt_rib_if.resp_err = u_mstr_rib_if.resp_err;
assign u_mgmt_rib_if.resp_code = u_mstr_rib_if.resp_code;
assign u_mgmt_rib_if.rsp_beat = u_mstr_rib_if.rsp_beat;
assign u_mgmt_rib_if.rsp_last = u_mstr_rib_if.rsp_last;
assign user_rib.cmd_ready = s_mstr_lock_q && (s_mstr_id_q == MSTR_USER) ?
u_mstr_burst_if.cmd_ready : 1'b0;
u_mstr_rib_if.cmd_ready : 1'b0;
assign user_rib.w_ready = s_mstr_lock_q && (s_mstr_id_q == MSTR_USER) ?
u_mstr_burst_if.w_ready : 1'b0;
u_mstr_rib_if.w_ready : 1'b0;
assign user_rib.rsp_valid = s_mstr_lock_q && (s_mstr_id_q == MSTR_USER) ?
u_mstr_burst_if.rsp_valid : 1'b0;
assign user_rib.rdata = u_mstr_burst_if.rdata;
assign user_rib.resp_err = u_mstr_burst_if.resp_err;
assign user_rib.resp_code = u_mstr_burst_if.resp_code;
assign user_rib.rsp_beat = u_mstr_burst_if.rsp_beat;
assign user_rib.rsp_last = u_mstr_burst_if.rsp_last;
u_mstr_rib_if.rsp_valid : 1'b0;
assign user_rib.rdata = u_mstr_rib_if.rdata;
assign user_rib.resp_err = u_mstr_rib_if.resp_err;
assign user_rib.resp_code = u_mstr_rib_if.resp_code;
assign user_rib.rsp_beat = u_mstr_rib_if.rsp_beat;
assign user_rib.rsp_last = u_mstr_rib_if.rsp_last;
assign dma_rib.cmd_ready = s_mstr_lock_q && (s_mstr_id_q == MSTR_DMA) ?
u_mstr_burst_if.cmd_ready : 1'b0;
u_mstr_rib_if.cmd_ready : 1'b0;
assign dma_rib.w_ready = s_mstr_lock_q && (s_mstr_id_q == MSTR_DMA) ?
u_mstr_burst_if.w_ready : 1'b0;
u_mstr_rib_if.w_ready : 1'b0;
assign dma_rib.rsp_valid = s_mstr_lock_q && (s_mstr_id_q == MSTR_DMA) ?
u_mstr_burst_if.rsp_valid : 1'b0;
assign dma_rib.rdata = u_mstr_burst_if.rdata;
assign dma_rib.resp_err = u_mstr_burst_if.resp_err;
assign dma_rib.resp_code = u_mstr_burst_if.resp_code;
assign dma_rib.rsp_beat = u_mstr_burst_if.rsp_beat;
assign dma_rib.rsp_last = u_mstr_burst_if.rsp_last;
u_mstr_rib_if.rsp_valid : 1'b0;
assign dma_rib.rdata = u_mstr_rib_if.rdata;
assign dma_rib.resp_err = u_mstr_rib_if.resp_err;
assign dma_rib.resp_code = u_mstr_rib_if.resp_code;
assign dma_rib.rsp_beat = u_mstr_rib_if.rsp_beat;
assign dma_rib.rsp_last = u_mstr_rib_if.rsp_last;
// verilog_format: off
assign s_last_addr = u_mstr_burst_if.cmd_addr +
(u_mstr_burst_if.cmd_len == `SOC_RIB_BURST_INCR4 ? 32'd12 : 32'd0);
assign s_last_addr = u_mstr_rib_if.cmd_addr +
(u_mstr_rib_if.cmd_len == `SOC_RIB_LEN_INCR4 ? 32'd12 : 32'd0);
assign s_length_legal =
(u_mstr_burst_if.cmd_len == `SOC_RIB_BURST_INCR1) ||
(u_mstr_burst_if.cmd_len == `SOC_RIB_BURST_INCR4);
(u_mstr_rib_if.cmd_len == `SOC_RIB_LEN_INCR1) ||
(u_mstr_rib_if.cmd_len == `SOC_RIB_LEN_INCR4);
assign s_burst_legal =
s_length_legal &&
((u_mstr_burst_if.cmd_len == `SOC_RIB_BURST_INCR1) ||
((u_mstr_burst_if.cmd_addr[3:0] == 4'b0000) &&
`SOC_ADDR_SUPPORTS_INCR4(u_mstr_burst_if.cmd_addr) &&
((u_mstr_rib_if.cmd_len == `SOC_RIB_LEN_INCR1) ||
((u_mstr_rib_if.cmd_addr[3:0] == 4'b0000) &&
`SOC_ADDR_SUPPORTS_INCR4(u_mstr_rib_if.cmd_addr) &&
`SOC_ADDR_SUPPORTS_INCR4(s_last_addr)));
assign s_user_access_allowed = u_mstr_burst_if.cmd_write ?
(`SOC_USER_ADDR_WRITABLE(u_mstr_burst_if.cmd_addr) &&
assign s_user_access_allowed = u_mstr_rib_if.cmd_write ?
(`SOC_USER_ADDR_WRITABLE(u_mstr_rib_if.cmd_addr) &&
`SOC_USER_ADDR_WRITABLE(s_last_addr)) :
(`SOC_USER_ADDR_READABLE(u_mstr_burst_if.cmd_addr) &&
(`SOC_USER_ADDR_READABLE(u_mstr_rib_if.cmd_addr) &&
`SOC_USER_ADDR_READABLE(s_last_addr));
// verilog_format: on
assign s_access_denied = (s_mstr_id_q == MSTR_USER) && ~s_user_access_allowed;
// verilog_format: off
assign s_rib_sel = u_mstr_burst_if.cmd_valid && ~s_cmd_accepted_q && ~s_access_denied &&
s_burst_legal && `SOC_ADDR_IS_RIB(u_mstr_burst_if.cmd_addr);
assign s_apb_sel = u_mstr_burst_if.cmd_valid && ~s_cmd_accepted_q && ~s_access_denied &&
(u_mstr_burst_if.cmd_len == `SOC_RIB_BURST_INCR1) &&
`SOC_ADDR_IS_APB(u_mstr_burst_if.cmd_addr);
assign s_ribp_sel = u_mstr_rib_if.cmd_valid && ~s_cmd_accepted_q && ~s_access_denied &&
s_burst_legal && `SOC_ADDR_IS_RIBP(u_mstr_rib_if.cmd_addr);
assign s_apb_sel = u_mstr_rib_if.cmd_valid && ~s_cmd_accepted_q && ~s_access_denied &&
(u_mstr_rib_if.cmd_len == `SOC_RIB_LEN_INCR1) &&
`SOC_ADDR_IS_APB(u_mstr_rib_if.cmd_addr);
`ifdef HAVE_SRAM_IF
assign s_ram_sel = u_mstr_burst_if.cmd_valid && ~s_cmd_accepted_q && ~s_access_denied &&
s_burst_legal && `SOC_ADDR_IS_RAM(u_mstr_burst_if.cmd_addr);
assign s_ram_sel = u_mstr_rib_if.cmd_valid && ~s_cmd_accepted_q && ~s_access_denied &&
s_burst_legal && `SOC_ADDR_IS_RAM(u_mstr_rib_if.cmd_addr);
`else
assign s_ram_sel = 1'b0;
`endif
assign s_fault_sel = u_mstr_burst_if.cmd_valid && ~s_cmd_accepted_q &&
~(s_rib_sel || s_apb_sel || s_ram_sel);
assign s_fault_sel = u_mstr_rib_if.cmd_valid && ~s_cmd_accepted_q &&
~(s_ribp_sel || s_apb_sel || s_ram_sel);
// verilog_format: on
always_comb begin
s_fault_code = `SOC_RIB_RESP_DECERR;
if (s_access_denied) begin
s_fault_code = `SOC_RIB_RESP_PROTERR;
end else if (`SOC_ADDR_IS_RESERVED(u_mstr_burst_if.cmd_addr)) begin
end else if (`SOC_ADDR_IS_RESERVED(u_mstr_rib_if.cmd_addr)) begin
s_fault_code = `SOC_RIB_RESP_RESERVED;
// verilog_format: off
end else if ((`SOC_ADDR_IS_RIB(u_mstr_burst_if.cmd_addr) ||
`SOC_ADDR_IS_APB(u_mstr_burst_if.cmd_addr) ||
`SOC_ADDR_IS_RAM(u_mstr_burst_if.cmd_addr)) &&
end else if ((`SOC_ADDR_IS_RIBP(u_mstr_rib_if.cmd_addr) ||
`SOC_ADDR_IS_APB(u_mstr_rib_if.cmd_addr) ||
`SOC_ADDR_IS_RAM(u_mstr_rib_if.cmd_addr)) &&
(~s_burst_legal ||
(`SOC_ADDR_IS_APB(u_mstr_burst_if.cmd_addr) &&
(u_mstr_burst_if.cmd_len != `SOC_RIB_BURST_INCR1)))) begin
(`SOC_ADDR_IS_APB(u_mstr_rib_if.cmd_addr) &&
(u_mstr_rib_if.cmd_len != `SOC_RIB_LEN_INCR1)))) begin
// verilog_format: on
s_fault_code = `SOC_RIB_RESP_BURSTERR;
end
end
// Command routing. Target selection is captured on command acceptance.
assign rib.cmd_valid = s_rib_sel;
assign rib.cmd_addr = u_mstr_burst_if.cmd_addr;
assign rib.cmd_write = u_mstr_burst_if.cmd_write;
assign rib.cmd_len = u_mstr_burst_if.cmd_len;
assign u_apb_burst_if.cmd_valid = s_apb_sel;
assign u_apb_burst_if.cmd_addr = u_mstr_burst_if.cmd_addr;
assign u_apb_burst_if.cmd_write = u_mstr_burst_if.cmd_write;
assign u_apb_burst_if.cmd_len = u_mstr_burst_if.cmd_len;
assign u_ram_burst_if.cmd_valid = s_ram_sel;
assign u_ram_burst_if.cmd_addr = u_mstr_burst_if.cmd_addr;
assign u_ram_burst_if.cmd_write = u_mstr_burst_if.cmd_write;
assign u_ram_burst_if.cmd_len = u_mstr_burst_if.cmd_len;
assign u_fault_burst_if.cmd_valid = s_fault_sel;
assign u_fault_burst_if.cmd_addr = u_mstr_burst_if.cmd_addr;
assign u_fault_burst_if.cmd_write = u_mstr_burst_if.cmd_write;
assign u_fault_burst_if.cmd_len = u_mstr_burst_if.cmd_len;
assign rib.cmd_valid = s_ribp_sel;
assign rib.cmd_addr = u_mstr_rib_if.cmd_addr;
assign rib.cmd_write = u_mstr_rib_if.cmd_write;
assign rib.cmd_len = u_mstr_rib_if.cmd_len;
assign u_apb_rib_if.cmd_valid = s_apb_sel;
assign u_apb_rib_if.cmd_addr = u_mstr_rib_if.cmd_addr;
assign u_apb_rib_if.cmd_write = u_mstr_rib_if.cmd_write;
assign u_apb_rib_if.cmd_len = u_mstr_rib_if.cmd_len;
assign u_ram_rib_if.cmd_valid = s_ram_sel;
assign u_ram_rib_if.cmd_addr = u_mstr_rib_if.cmd_addr;
assign u_ram_rib_if.cmd_write = u_mstr_rib_if.cmd_write;
assign u_ram_rib_if.cmd_len = u_mstr_rib_if.cmd_len;
assign u_fault_rib_if.cmd_valid = s_fault_sel;
assign u_fault_rib_if.cmd_addr = u_mstr_rib_if.cmd_addr;
assign u_fault_rib_if.cmd_write = u_mstr_rib_if.cmd_write;
assign u_fault_rib_if.cmd_len = u_mstr_rib_if.cmd_len;
always_comb begin
u_mstr_burst_if.cmd_ready = 1'b0;
if (s_rib_sel) begin
u_mstr_burst_if.cmd_ready = rib.cmd_ready;
u_mstr_rib_if.cmd_ready = 1'b0;
if (s_ribp_sel) begin
u_mstr_rib_if.cmd_ready = rib.cmd_ready;
end else if (s_apb_sel) begin
u_mstr_burst_if.cmd_ready = u_apb_burst_if.cmd_ready;
u_mstr_rib_if.cmd_ready = u_apb_rib_if.cmd_ready;
end else if (s_ram_sel) begin
u_mstr_burst_if.cmd_ready = u_ram_burst_if.cmd_ready;
u_mstr_rib_if.cmd_ready = u_ram_rib_if.cmd_ready;
end else if (s_fault_sel) begin
u_mstr_burst_if.cmd_ready = u_fault_burst_if.cmd_ready;
u_mstr_rib_if.cmd_ready = u_fault_rib_if.cmd_ready;
end
end
always_comb begin
s_target_d = s_target_q;
if (u_mstr_burst_if.cmd_valid && u_mstr_burst_if.cmd_ready) begin
if (s_rib_sel) begin
s_target_d = TARGET_RIB;
if (u_mstr_rib_if.cmd_valid && u_mstr_rib_if.cmd_ready) begin
if (s_ribp_sel) begin
s_target_d = TARGET_RIBP;
end else if (s_apb_sel) begin
s_target_d = TARGET_APB;
end else if (s_ram_sel) begin
@@ -419,101 +419,101 @@ module bus (
);
// Write-data and response routing uses the captured target.
assign rib.w_valid = s_mstr_lock_q && s_cmd_accepted_q && (s_target_q == TARGET_RIB) ?
u_mstr_burst_if.w_valid : 1'b0;
assign rib.wdata = u_mstr_burst_if.wdata;
assign rib.wstrb = u_mstr_burst_if.wstrb;
assign rib.wlast = u_mstr_burst_if.wlast;
assign rib.rsp_ready = s_mstr_lock_q && s_cmd_accepted_q && (s_target_q == TARGET_RIB) ?
u_mstr_burst_if.rsp_ready : 1'b0;
assign rib.w_valid = s_mstr_lock_q && s_cmd_accepted_q && (s_target_q == TARGET_RIBP) ?
u_mstr_rib_if.w_valid : 1'b0;
assign rib.wdata = u_mstr_rib_if.wdata;
assign rib.wstrb = u_mstr_rib_if.wstrb;
assign rib.wlast = u_mstr_rib_if.wlast;
assign rib.rsp_ready = s_mstr_lock_q && s_cmd_accepted_q && (s_target_q == TARGET_RIBP) ?
u_mstr_rib_if.rsp_ready : 1'b0;
assign u_apb_burst_if.w_valid = s_mstr_lock_q && s_cmd_accepted_q &&
assign u_apb_rib_if.w_valid = s_mstr_lock_q && s_cmd_accepted_q &&
(s_target_q == TARGET_APB) ?
u_mstr_burst_if.w_valid : 1'b0;
assign u_apb_burst_if.wdata = u_mstr_burst_if.wdata;
assign u_apb_burst_if.wstrb = u_mstr_burst_if.wstrb;
assign u_apb_burst_if.wlast = u_mstr_burst_if.wlast;
assign u_apb_burst_if.rsp_ready = s_mstr_lock_q && s_cmd_accepted_q &&
u_mstr_rib_if.w_valid : 1'b0;
assign u_apb_rib_if.wdata = u_mstr_rib_if.wdata;
assign u_apb_rib_if.wstrb = u_mstr_rib_if.wstrb;
assign u_apb_rib_if.wlast = u_mstr_rib_if.wlast;
assign u_apb_rib_if.rsp_ready = s_mstr_lock_q && s_cmd_accepted_q &&
(s_target_q == TARGET_APB) ?
u_mstr_burst_if.rsp_ready : 1'b0;
u_mstr_rib_if.rsp_ready : 1'b0;
assign u_ram_burst_if.w_valid = s_mstr_lock_q && s_cmd_accepted_q &&
assign u_ram_rib_if.w_valid = s_mstr_lock_q && s_cmd_accepted_q &&
(s_target_q == TARGET_RAM) ?
u_mstr_burst_if.w_valid : 1'b0;
assign u_ram_burst_if.wdata = u_mstr_burst_if.wdata;
assign u_ram_burst_if.wstrb = u_mstr_burst_if.wstrb;
assign u_ram_burst_if.wlast = u_mstr_burst_if.wlast;
assign u_ram_burst_if.rsp_ready = s_mstr_lock_q && s_cmd_accepted_q &&
u_mstr_rib_if.w_valid : 1'b0;
assign u_ram_rib_if.wdata = u_mstr_rib_if.wdata;
assign u_ram_rib_if.wstrb = u_mstr_rib_if.wstrb;
assign u_ram_rib_if.wlast = u_mstr_rib_if.wlast;
assign u_ram_rib_if.rsp_ready = s_mstr_lock_q && s_cmd_accepted_q &&
(s_target_q == TARGET_RAM) ?
u_mstr_burst_if.rsp_ready : 1'b0;
u_mstr_rib_if.rsp_ready : 1'b0;
assign u_fault_burst_if.w_valid = s_mstr_lock_q && s_cmd_accepted_q &&
assign u_fault_rib_if.w_valid = s_mstr_lock_q && s_cmd_accepted_q &&
(s_target_q == TARGET_FAULT) ?
u_mstr_burst_if.w_valid : 1'b0;
assign u_fault_burst_if.wdata = u_mstr_burst_if.wdata;
assign u_fault_burst_if.wstrb = u_mstr_burst_if.wstrb;
assign u_fault_burst_if.wlast = u_mstr_burst_if.wlast;
assign u_fault_burst_if.rsp_ready = s_mstr_lock_q && s_cmd_accepted_q &&
u_mstr_rib_if.w_valid : 1'b0;
assign u_fault_rib_if.wdata = u_mstr_rib_if.wdata;
assign u_fault_rib_if.wstrb = u_mstr_rib_if.wstrb;
assign u_fault_rib_if.wlast = u_mstr_rib_if.wlast;
assign u_fault_rib_if.rsp_ready = s_mstr_lock_q && s_cmd_accepted_q &&
(s_target_q == TARGET_FAULT) ?
u_mstr_burst_if.rsp_ready : 1'b0;
u_mstr_rib_if.rsp_ready : 1'b0;
always_comb begin
u_mstr_burst_if.w_ready = 1'b0;
u_mstr_burst_if.rsp_valid = 1'b0;
u_mstr_burst_if.rdata = '0;
u_mstr_burst_if.resp_err = 1'b0;
u_mstr_burst_if.resp_code = `SOC_RIB_RESP_OK;
u_mstr_burst_if.rsp_beat = '0;
u_mstr_burst_if.rsp_last = 1'b0;
u_mstr_rib_if.w_ready = 1'b0;
u_mstr_rib_if.rsp_valid = 1'b0;
u_mstr_rib_if.rdata = '0;
u_mstr_rib_if.resp_err = 1'b0;
u_mstr_rib_if.resp_code = `SOC_RIB_RESP_OK;
u_mstr_rib_if.rsp_beat = '0;
u_mstr_rib_if.rsp_last = 1'b0;
unique case (s_target_q)
TARGET_RIB: begin
u_mstr_burst_if.w_ready = s_cmd_accepted_q && rib.w_ready;
u_mstr_burst_if.rsp_valid = s_cmd_accepted_q && rib.rsp_valid;
u_mstr_burst_if.rdata = rib.rdata;
u_mstr_burst_if.resp_err = rib.resp_err;
u_mstr_burst_if.resp_code = rib.resp_code;
u_mstr_burst_if.rsp_beat = rib.rsp_beat;
u_mstr_burst_if.rsp_last = rib.rsp_last;
TARGET_RIBP: begin
u_mstr_rib_if.w_ready = s_cmd_accepted_q && rib.w_ready;
u_mstr_rib_if.rsp_valid = s_cmd_accepted_q && rib.rsp_valid;
u_mstr_rib_if.rdata = rib.rdata;
u_mstr_rib_if.resp_err = rib.resp_err;
u_mstr_rib_if.resp_code = rib.resp_code;
u_mstr_rib_if.rsp_beat = rib.rsp_beat;
u_mstr_rib_if.rsp_last = rib.rsp_last;
end
TARGET_APB: begin
u_mstr_burst_if.w_ready = s_cmd_accepted_q && u_apb_burst_if.w_ready;
u_mstr_burst_if.rsp_valid = s_cmd_accepted_q && u_apb_burst_if.rsp_valid;
u_mstr_burst_if.rdata = u_apb_burst_if.rdata;
u_mstr_burst_if.resp_err = u_apb_burst_if.resp_err;
u_mstr_burst_if.resp_code = u_apb_burst_if.resp_code;
u_mstr_burst_if.rsp_beat = u_apb_burst_if.rsp_beat;
u_mstr_burst_if.rsp_last = u_apb_burst_if.rsp_last;
u_mstr_rib_if.w_ready = s_cmd_accepted_q && u_apb_rib_if.w_ready;
u_mstr_rib_if.rsp_valid = s_cmd_accepted_q && u_apb_rib_if.rsp_valid;
u_mstr_rib_if.rdata = u_apb_rib_if.rdata;
u_mstr_rib_if.resp_err = u_apb_rib_if.resp_err;
u_mstr_rib_if.resp_code = u_apb_rib_if.resp_code;
u_mstr_rib_if.rsp_beat = u_apb_rib_if.rsp_beat;
u_mstr_rib_if.rsp_last = u_apb_rib_if.rsp_last;
end
TARGET_RAM: begin
u_mstr_burst_if.w_ready = s_cmd_accepted_q && u_ram_burst_if.w_ready;
u_mstr_burst_if.rsp_valid = s_cmd_accepted_q && u_ram_burst_if.rsp_valid;
u_mstr_burst_if.rdata = u_ram_burst_if.rdata;
u_mstr_burst_if.resp_err = u_ram_burst_if.resp_err;
u_mstr_burst_if.resp_code = u_ram_burst_if.resp_code;
u_mstr_burst_if.rsp_beat = u_ram_burst_if.rsp_beat;
u_mstr_burst_if.rsp_last = u_ram_burst_if.rsp_last;
u_mstr_rib_if.w_ready = s_cmd_accepted_q && u_ram_rib_if.w_ready;
u_mstr_rib_if.rsp_valid = s_cmd_accepted_q && u_ram_rib_if.rsp_valid;
u_mstr_rib_if.rdata = u_ram_rib_if.rdata;
u_mstr_rib_if.resp_err = u_ram_rib_if.resp_err;
u_mstr_rib_if.resp_code = u_ram_rib_if.resp_code;
u_mstr_rib_if.rsp_beat = u_ram_rib_if.rsp_beat;
u_mstr_rib_if.rsp_last = u_ram_rib_if.rsp_last;
end
default: begin
u_mstr_burst_if.w_ready = s_cmd_accepted_q && u_fault_burst_if.w_ready;
u_mstr_burst_if.rsp_valid = s_cmd_accepted_q && u_fault_burst_if.rsp_valid;
u_mstr_burst_if.rdata = u_fault_burst_if.rdata;
u_mstr_burst_if.resp_err = u_fault_burst_if.resp_err;
u_mstr_burst_if.resp_code = u_fault_burst_if.resp_code;
u_mstr_burst_if.rsp_beat = u_fault_burst_if.rsp_beat;
u_mstr_burst_if.rsp_last = u_fault_burst_if.rsp_last;
u_mstr_rib_if.w_ready = s_cmd_accepted_q && u_fault_rib_if.w_ready;
u_mstr_rib_if.rsp_valid = s_cmd_accepted_q && u_fault_rib_if.rsp_valid;
u_mstr_rib_if.rdata = u_fault_rib_if.rdata;
u_mstr_rib_if.resp_err = u_fault_rib_if.resp_err;
u_mstr_rib_if.resp_code = u_fault_rib_if.resp_code;
u_mstr_rib_if.rsp_beat = u_fault_rib_if.rsp_beat;
u_mstr_rib_if.rsp_last = u_fault_rib_if.rsp_last;
end
endcase
end
assign s_fault_cmd_hdshk = s_fault_sel && u_fault_burst_if.cmd_ready;
assign s_fault_cmd_hdshk = s_fault_sel && u_fault_rib_if.cmd_ready;
assign s_fault_w_hdshk = (s_target_q == TARGET_FAULT) &&
u_fault_burst_if.w_valid && u_fault_burst_if.w_ready;
u_fault_rib_if.w_valid && u_fault_rib_if.w_ready;
always_comb begin
s_fault_wstrb_d = s_fault_wstrb_q;
if (s_fault_cmd_hdshk) begin
s_fault_wstrb_d = '0;
end else if (s_fault_w_hdshk && (s_fault_wstrb_q == '0)) begin
s_fault_wstrb_d = u_fault_burst_if.wstrb;
s_fault_wstrb_d = u_fault_rib_if.wstrb;
end
end
dffr #(4) u_fault_wstrb_dffr (
@@ -526,7 +526,7 @@ module bus (
clk_i,
rst_n_i,
s_fault_cmd_hdshk,
u_mstr_burst_if.cmd_addr,
u_mstr_rib_if.cmd_addr,
s_fault_addr_q
);
dffer #(2) u_fault_master_dffer (
@@ -546,13 +546,13 @@ module bus (
dffer #(32) u_xfer_addr_dffer (
clk_i,
rst_n_i,
u_mstr_burst_if.cmd_valid && u_mstr_burst_if.cmd_ready,
u_mstr_burst_if.cmd_addr,
u_mstr_rib_if.cmd_valid && u_mstr_rib_if.cmd_ready,
u_mstr_rib_if.cmd_addr,
s_xfer_addr_q
);
assign fault_valid_o = s_cmd_accepted_q && (s_target_q == TARGET_FAULT) &&
u_fault_burst_if.rsp_valid && u_fault_burst_if.rsp_ready;
u_fault_rib_if.rsp_valid && u_fault_rib_if.rsp_ready;
assign fault_addr_o = s_fault_addr_q;
assign fault_wstrb_o = s_fault_wstrb_q;
assign fault_reserved_o = s_fault_code_q == `SOC_RIB_RESP_RESERVED;
@@ -561,16 +561,16 @@ module bus (
assign fault_code_o = s_fault_code_q;
assign s_xfer_stalled = s_mstr_lock_q &&
((u_mstr_burst_if.cmd_valid && ~u_mstr_burst_if.cmd_ready) ||
(u_mstr_burst_if.w_valid && ~u_mstr_burst_if.w_ready) ||
(~u_mstr_burst_if.cmd_valid && ~u_mstr_burst_if.w_valid &&
~u_mstr_burst_if.rsp_valid));
((u_mstr_rib_if.cmd_valid && ~u_mstr_rib_if.cmd_ready) ||
(u_mstr_rib_if.w_valid && ~u_mstr_rib_if.w_ready) ||
(~u_mstr_rib_if.cmd_valid && ~u_mstr_rib_if.w_valid &&
~u_mstr_rib_if.rsp_valid));
always_comb begin
s_perf_mgmt_wait_d = s_perf_mgmt_wait_q;
s_perf_user_wait_d = s_perf_user_wait_q;
s_perf_dma_wait_d = s_perf_dma_wait_q;
s_perf_rib_wait_d = s_perf_rib_wait_q;
s_perf_ribp_wait_d = s_perf_ribp_wait_q;
s_perf_apb_wait_d = s_perf_apb_wait_q;
s_perf_sdram_wait_d = s_perf_sdram_wait_q;
s_perf_psram_wait_d = s_perf_psram_wait_q;
@@ -579,7 +579,7 @@ module bus (
s_perf_mgmt_wait_d = '0;
s_perf_user_wait_d = '0;
s_perf_dma_wait_d = '0;
s_perf_rib_wait_d = '0;
s_perf_ribp_wait_d = '0;
s_perf_apb_wait_d = '0;
s_perf_sdram_wait_d = '0;
s_perf_psram_wait_d = '0;
@@ -590,7 +590,7 @@ module bus (
MSTR_USER: s_perf_user_wait_d = s_perf_user_wait_q + 1'b1;
default: s_perf_dma_wait_d = s_perf_dma_wait_q + 1'b1;
endcase
if (s_target_q == TARGET_RIB) s_perf_rib_wait_d = s_perf_rib_wait_q + 1'b1;
if (s_target_q == TARGET_RIBP) s_perf_ribp_wait_d = s_perf_ribp_wait_q + 1'b1;
if (s_target_q == TARGET_APB) s_perf_apb_wait_d = s_perf_apb_wait_q + 1'b1;
if (`SOC_ADDR_IS_SDRAM(s_xfer_addr_q)) begin
s_perf_sdram_wait_d = s_perf_sdram_wait_q + 1'b1;
@@ -622,11 +622,11 @@ module bus (
s_perf_dma_wait_d,
s_perf_dma_wait_q
);
dffr #(64) u_perf_rib_wait_dffr (
dffr #(64) u_perf_ribp_wait_dffr (
clk_i,
rst_n_i,
s_perf_rib_wait_d,
s_perf_rib_wait_q
s_perf_ribp_wait_d,
s_perf_ribp_wait_q
);
dffr #(64) u_perf_apb_wait_dffr (
clk_i,
@@ -656,7 +656,7 @@ module bus (
assign perf_mgmt_wait_o = s_perf_mgmt_wait_q;
assign perf_user_wait_o = s_perf_user_wait_q;
assign perf_dma_wait_o = s_perf_dma_wait_q;
assign perf_rib_wait_o = s_perf_rib_wait_q;
assign perf_ribp_wait_o = s_perf_ribp_wait_q;
assign perf_apb_wait_o = s_perf_apb_wait_q;
assign perf_sdram_wait_o = s_perf_sdram_wait_q;
assign perf_psram_wait_o = s_perf_psram_wait_q;
rtl/mini/top/core_wrapper.sv
+2 -2
View File
@@ -13,7 +13,7 @@ module core_wrapper (
input logic clk_i,
input logic rst_n_i,
input logic [31:0] irq_i,
soc_rib_if.master rib
soc_ribl_if.master ribl
// verilog_format: on
);
@@ -21,7 +21,7 @@ module core_wrapper (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.irq_i (irq_i),
.rib (rib)
.ribl (ribl)
);
endmodule
rtl/mini/top/ip_apb_wrapper.sv
+5 -5
View File
@@ -22,13 +22,13 @@ module ip_apb_wrapper (
input logic clk_aud_i,
input logic rst_aud_n_i,
input logic tmr_capch_i,
rib_if.slave rib,
ribp_if.slave ribp,
uart_if.dut uart,
pwm_if.dut pwm,
ps2_if.dut ps2,
input logic [`USER_IPSEL_WIDTH-1:0] ip_sel_i,
user_gpio_if.user_ip user_gpio,
output logic rib_resp_err_o,
output logic ribp_resp_err_o,
output logic [`SOC_IRQ_APB_WIDTH-1:0] irq_o
// verilog_format: on
);
@@ -63,11 +63,11 @@ module ip_apb_wrapper (
// Generated IRQ ownership and core-vector bit assignments are topology checked.
`include "soc_apb_irq_bindings.svh"
rib2apb u_rib2apb (
ribp2apb u_ribp2apb (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.rib (rib),
.resp_err_o(rib_resp_err_o),
.ribp (ribp),
.resp_err_o(ribp_resp_err_o),
`include "soc_apb_connections.svh"
);
rtl/mini/top/ip_rib_wrapper.sv → rtl/mini/top/ip_ribp_wrapper.sv
+56 -56
View File
@@ -12,13 +12,13 @@
`include "soc_irq_config.svh"
`include "soc_rib_defs.svh"
module ip_rib_wrapper (
module ip_ribp_wrapper (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
input logic clk_aud_i,
input logic rst_aud_n_i,
soc_rib_burst_if.slave burst_rib,
soc_rib_if.slave rib,
gpio_if.dut gpio,
user_gpio_if.padctrl user_gpio,
uart_if.dut uart,
@@ -28,7 +28,7 @@ module ip_rib_wrapper (
i2s_if.dut i2s,
onewire_if.dut onewire,
xpi_if.dut xpi,
soc_rib_burst_if.master dma_rib,
soc_rib_if.master dma_rib,
sysctrl_if.dut sysctrl,
pll_ctrl_if.sysctrl pll_ctrl,
sdram_if.dut sdram,
@@ -40,15 +40,15 @@ module ip_rib_wrapper (
input logic [31:0] fault_addr_i,
input logic [3:0] fault_wstrb_i,
input logic fault_reserved_i,
output logic [`SOC_IRQ_RIB_WIDTH-1:0] irq_o
output logic [`SOC_IRQ_RIBP_WIDTH-1:0] irq_o
// verilog_format: on
);
// verilog_format: off
// Generated RIB target declarations preserve scalar-interface compatibility.
`include "soc_rib_interfaces.svh"
// Generated RIBP target declarations preserve scalar-interface compatibility.
`include "soc_ribp_interfaces.svh"
rib_if rib ();
ribp_if ribp ();
// verilog_format: on
simp_clint_if u_clint_if ();
@@ -59,169 +59,169 @@ module ip_rib_wrapper (
logic s_dma_xfer_done;
logic s_tim0_irq, s_tim1_irq;
soc_rib_burst_to_legacy u_rib_burst_to_legacy (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.legacy_resp_err_i (1'b0),
.legacy_resp_code_i(`SOC_RIB_RESP_OK),
.burst (burst_rib),
.legacy (rib)
soc_rib2ribp u_rib2ribp (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.ribp_resp_err_i (1'b0),
.ribp_resp_code_i(`SOC_RIB_RESP_OK),
.rib (rib),
.ribp (ribp)
);
// Generated target routing operates on the legacy boundary behind the
// burst adapter. Register targets therefore remain INCR1-only.
// Generated target routing operates on the RIBP boundary behind the RIB
// adapter. Register targets therefore remain INCR1-only.
assign u_dma_hw_trg_if.i2s_tx_proc = ~s_dma_i2s_tx_stall;
assign u_dma_hw_trg_if.i2s_rx_proc = ~s_dma_i2s_rx_stall;
assign u_dma_hw_trg_if.qspi_tx_proc = ~s_dma_xpi_tx_stall;
assign u_dma_hw_trg_if.qspi_rx_proc = ~s_dma_xpi_rx_stall;
// Uses ClusterIP common rib_if and register.sv dffr through generated bindings.
`include "soc_rib_routes.svh"
// Uses ClusterIP common ribp_if and register.sv dffr through generated bindings.
`include "soc_ribp_routes.svh"
// verilog_format: off
// Generated IRQ ownership and core-vector bit assignments are topology checked.
`include "soc_rib_irq_bindings.svh"
`include "soc_ribp_irq_bindings.svh"
rib_gpio u_rib_gpio (
ribp_gpio u_rib_gpio (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.rib (u_gpio_rib_if),
.ribp(u_gpio_ribp_if),
.gpio (gpio),
.user_gpio(user_gpio)
);
// verilog_format: on
rib_uart u_rib_uart (
ribp_uart u_rib_uart (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.rib (u_uart_rib_if),
.ribp (u_uart_ribp_if),
.uart (uart)
);
rib_timer u_rib_timer0 (
ribp_timer u_rib_timer0 (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.rib (u_tim0_rib_if),
.ribp (u_tim0_ribp_if),
.irq_o (s_tim0_irq)
);
rib_timer u_rib_timer1 (
ribp_timer u_rib_timer1 (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.rib (u_tim1_rib_if),
.ribp (u_tim1_ribp_if),
.irq_o (s_tim1_irq)
);
rib_psram u_rib_psram (
ribp_psram u_rib_psram (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.rib (u_psram_rib_if),
.ribp (u_psram_ribp_if),
.psram (psram)
);
rib_spisd u_rib_spisd (
ribp_spisd u_rib_spisd (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.rib (u_spisd_rib_if),
.ribp (u_spisd_ribp_if),
.spi (spisd)
);
rib_i2c u_rib_i2c0 (
ribp_i2c u_rib_i2c0 (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.rib (u_i2c0_rib_if),
.ribp (u_i2c0_ribp_if),
.i2c (i2c0)
);
rib_i2s u_rib_i2s (
ribp_i2s u_rib_i2s (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.clk_aud_i (clk_aud_i),
.rst_aud_n_i (rst_aud_n_i),
.dma_tx_stall_o(s_dma_i2s_tx_stall),
.dma_rx_stall_o(s_dma_i2s_rx_stall),
.rib (u_i2s_rib_if),
.ribp (u_i2s_ribp_if),
.i2s (i2s)
);
rib_onewire u_rib_onewire (
ribp_onewire u_rib_onewire (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.rib (u_onewire_rib_if),
.ribp (u_onewire_ribp_if),
.onewire(onewire)
);
rib_xpi u_rib_xpi (
ribp_xpi u_rib_xpi (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.dma_xfer_done_i(s_dma_xfer_done),
.dma_tx_stall_o (s_dma_xpi_tx_stall),
.dma_rx_stall_o (s_dma_xpi_rx_stall),
.rib (u_xpi_rib_if),
.ribp (u_xpi_ribp_if),
.xpi (xpi)
);
rib_dma u_rib_dma (
ribp_dma u_rib_dma (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.dma_xfer_done_o(s_dma_xfer_done),
.hw_trg (u_dma_hw_trg_if),
.rib (u_dma_rib_if),
.rib_dma (dma_rib)
.ribp (u_dma_ribp_if),
.rib (dma_rib)
);
rib_sysctrl u_rib_sysctrl (
ribp_sysctrl u_rib_sysctrl (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.fault_valid_i (fault_valid_i),
.fault_addr_i (fault_addr_i),
.fault_wstrb_i (fault_wstrb_i),
.fault_reserved_i(fault_reserved_i),
.rib (u_sysctrl_rib_if),
.ribp (u_sysctrl_ribp_if),
.sysctrl (sysctrl),
.pll_ctrl (pll_ctrl)
);
rib_clint u_rib_clint (
ribp_clint u_rib_clint (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.rib (u_clint_rib_if),
.ribp (u_clint_ribp_if),
.clint (u_clint_if)
);
rib_sdram u_rib_sdram (
ribp_sdram u_rib_sdram (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.rib (u_sdram_rib_if),
.ribp (u_sdram_ribp_if),
.sdram (sdram)
);
rib_dvp u_rib_dvp (
ribp_dvp u_rib_dvp (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.rib (u_dvp_rib_if),
.ribp (u_dvp_ribp_if),
.dvp (dvp)
);
rib_sdio u_rib_sdio (
ribp_sdio u_rib_sdio (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.rib (u_sdio_rib_if),
.ribp (u_sdio_ribp_if),
.sdio (sdio)
);
rib_opipsram u_rib_opipsram (
ribp_opipsram u_rib_opipsram (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.rib (u_opipsram_rib_if),
.ribp (u_opipsram_ribp_if),
.psram (opipsram)
);
rib_i2c u_rib_i2c1 (
ribp_i2c u_rib_i2c1 (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.rib (u_i2c1_rib_if),
.ribp (u_i2c1_ribp_if),
.i2c (i2c1)
);
rtl/mini/top/mgmt_core_wrapper.sv
+8 -8
View File
@@ -15,7 +15,7 @@ module mgmt_core_wrapper (
input logic clk_i,
input logic rst_n_i,
input logic [31:0] irq_i,
soc_rib_if.master rib
soc_ribl_if.master ribl
// verilog_format: on
);
@@ -33,13 +33,13 @@ module mgmt_core_wrapper (
.clk (clk_i),
.resetn (rst_n_i),
.trap (),
.mem_valid (rib.valid),
.mem_valid (ribl.valid),
.mem_instr (),
.mem_addr (rib.addr),
.mem_wdata (rib.wdata),
.mem_wstrb (rib.wstrb),
.mem_rdata (rib.rdata),
.mem_ready (rib.ready),
.mem_addr (ribl.addr),
.mem_wdata (ribl.wdata),
.mem_wstrb (ribl.wstrb),
.mem_rdata (ribl.rdata),
.mem_ready (ribl.ready),
.mem_la_read (),
.mem_la_write(),
.mem_la_addr (),
@@ -62,7 +62,7 @@ module mgmt_core_wrapper (
logic s_pwrup_req;
// verilog_format: off
ahbl_if u_ahbl_if (clk_i, rst_n_i);
ahbl2soc_rib u_ahbl2soc_rib (u_ahbl_if, rib);
ahbl2soc_ribl u_ahbl2soc_ribl (u_ahbl_if, ribl);
// verilog_format: on
hazard3_cpu_1port #(
rtl/mini/top/rcu.sv
+56 -6
View File
@@ -55,17 +55,53 @@ module rcu (
logic s_pll_capable;
logic [2:0] s_pll_sel;
logic s_pll_apply;
logic s_select_ext_clk;
logic [2:0] s_pll_cfg_sel;
logic s_pll_cfg_valid;
logic s_pll_cfg_ready;
logic s_pll_cfg_req;
logic s_pll_cfg_sent_d, s_pll_cfg_sent_q;
logic s_select_ext_clk;
tc_clk_buf u_xtal_buf (
.clk_i(xtal_clk_i),
.clk_o(s_xtal_clk_buf)
);
// ext_clk_i and the PLL reference clock are unrelated. A pulse generated
// by the controller must cross this boundary through a handshake.
cdc_2phase #(
.DATA_WIDTH(3)
) u_pll_config_cdc (
.src_clk_i (s_ext_clk_buf),
.src_rst_n_i(s_ext_rst_n_sync),
.src_data_i (s_pll_sel),
.src_valid_i(s_pll_cfg_req),
.src_ready_o(s_pll_cfg_ready),
.dst_clk_i (s_xtal_clk_buf),
.dst_rst_n_i(s_ext_rst_n_sync),
.dst_data_o (s_pll_cfg_sel),
.dst_valid_o(s_pll_cfg_valid),
.dst_ready_i(1'b1)
);
assign s_pll_cfg_req = s_pll_apply && ~s_pll_cfg_sent_q;
always_comb begin
s_pll_cfg_sent_d = s_pll_cfg_sent_q;
if (!s_pll_apply) begin
s_pll_cfg_sent_d = 1'b0;
end else if (s_pll_cfg_req && s_pll_cfg_ready) begin
s_pll_cfg_sent_d = 1'b1;
end
end
dffr #(1) u_pll_cfg_sent_dffr (
s_ext_clk_buf,
s_ext_rst_n_sync,
s_pll_cfg_sent_d,
s_pll_cfg_sent_q
);
tc_pll u_tc_pll (
.fref_i (s_xtal_clk_buf),
.rst_n_i (s_ext_rst_n_sync),
.cfg_sel_i (s_pll_sel),
.cfg_apply_i (s_pll_apply),
.cfg_sel_i (s_pll_cfg_sel),
.cfg_apply_i (s_pll_cfg_valid),
.pll_capable_o(s_pll_capable),
.pll_lock_o (s_pll_lock),
.pll_clk_o (s_pll_clk)
@@ -199,6 +235,7 @@ module pll_rcu_controller #(
logic s_active_valid_d, s_active_valid_q;
logic s_safe_clk_d, s_safe_clk_q;
logic s_lock_d, s_lock_q;
logic s_lock_seen_low_d, s_lock_seen_low_q;
logic [1:0] s_error_d, s_error_q;
logic s_rsp_valid_d, s_rsp_valid_q;
@@ -254,11 +291,13 @@ module pll_rcu_controller #(
s_active_valid_d = s_active_valid_q;
s_safe_clk_d = s_safe_clk_q;
s_lock_d = s_lock_q;
s_lock_seen_low_d = s_lock_seen_low_q;
s_error_d = s_error_q;
s_rsp_valid_d = s_rsp_valid_q;
unique case (s_state_q)
PLL_IDLE: begin
s_lock_seen_low_d = 1'b0;
if (s_req_valid) begin
s_pll_sel_d = s_req_sel;
s_select_ext_clk_d = 1'b1;
@@ -267,6 +306,7 @@ module pll_rcu_controller #(
end
end
PLL_SAFE: begin
s_lock_seen_low_d = 1'b0;
s_select_ext_clk_d = 1'b1;
s_safe_clk_d = 1'b1;
s_lock_d = 1'b0;
@@ -279,11 +319,15 @@ module pll_rcu_controller #(
end
end
PLL_APPLY: begin
s_lock_count_d = '0;
s_state_d = PLL_WAIT_LOCK;
s_lock_count_d = '0;
s_lock_seen_low_d = 1'b0;
s_state_d = PLL_WAIT_LOCK;
end
PLL_WAIT_LOCK: begin
if (pll_lock_i) begin
if (!pll_lock_i) begin
s_lock_seen_low_d = 1'b1;
end
if (s_lock_seen_low_q && pll_lock_i) begin
s_active_sel_d = s_pll_sel_q;
s_active_valid_d = 1'b1;
s_safe_clk_d = 1'b0;
@@ -371,6 +415,12 @@ module pll_rcu_controller #(
s_lock_d,
s_lock_q
);
dffr #(1) u_lock_seen_low_dffr (
ext_clk_i,
ext_rst_n_i,
s_lock_seen_low_d,
s_lock_seen_low_q
);
dffr #(2) u_error_dffr (
ext_clk_i,
ext_rst_n_i,
rtl/mini/top/retrosoc.sv
+20 -20
View File
@@ -31,7 +31,7 @@ module retrosoc (
);
// verilog_format: off
// Generated fabric links reuse the common rib_if contract.
// Generated fabric links reuse the common ribp_if contract.
`include "soc_fabric_interfaces.svh"
user_gpio_if u_user_gpio_if ();
// ip interface
@@ -53,7 +53,7 @@ module retrosoc (
logic s_tmr_capch;
logic [`SOC_IRQ_VECTOR_WIDTH-1:0] s_irq;
logic [ `SOC_IRQ_RIB_WIDTH-1:0] s_rib_irq;
logic [ `SOC_IRQ_RIBP_WIDTH-1:0] s_ribp_irq;
logic [ `SOC_IRQ_APB_WIDTH-1:0] s_apb_irq;
logic s_bus_fault_valid;
logic [ 31:0] s_bus_fault_addr;
@@ -68,7 +68,7 @@ module retrosoc (
logic [ 63:0] s_perf_mgmt_wait;
logic [ 63:0] s_perf_user_wait;
logic [ 63:0] s_perf_dma_wait;
logic [ 63:0] s_perf_rib_wait;
logic [ 63:0] s_perf_ribp_wait;
logic [ 63:0] s_perf_apb_wait;
logic [ 63:0] s_perf_sdram_wait;
logic [ 63:0] s_perf_psram_wait;
@@ -83,7 +83,7 @@ module retrosoc (
assign u_sysctrl_if.perf_mgmt_wait_i = s_perf_mgmt_wait;
assign u_sysctrl_if.perf_user_wait_i = s_perf_user_wait;
assign u_sysctrl_if.perf_dma_wait_i = s_perf_dma_wait;
assign u_sysctrl_if.perf_rib_wait_i = s_perf_rib_wait;
assign u_sysctrl_if.perf_ribp_wait_i = s_perf_ribp_wait;
assign u_sysctrl_if.perf_apb_wait_i = s_perf_apb_wait;
assign u_sysctrl_if.perf_sdram_wait_i = s_perf_sdram_wait;
assign u_sysctrl_if.perf_psram_wait_i = s_perf_psram_wait;
@@ -139,19 +139,19 @@ core_wrapper u_core_wrapper (
.perf_mgmt_wait_o (s_perf_mgmt_wait),
.perf_user_wait_o (s_perf_user_wait),
.perf_dma_wait_o (s_perf_dma_wait),
.perf_rib_wait_o (s_perf_rib_wait),
.perf_ribp_wait_o (s_perf_ribp_wait),
.perf_apb_wait_o (s_perf_apb_wait),
.perf_sdram_wait_o(s_perf_sdram_wait),
.perf_psram_wait_o(s_perf_psram_wait),
.perf_flash_wait_o(s_perf_flash_wait)
);
ip_rib_wrapper u_ip_rib_wrapper (
ip_ribp_wrapper u_ip_ribp_wrapper (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.clk_aud_i (clk_aud_i),
.rst_aud_n_i (rst_aud_n_i),
`include "soc_ip_rib_wrapper_fabric.svh"
`include "soc_ip_ribp_wrapper_fabric.svh"
.gpio (u_gpio_if),
.user_gpio (u_user_gpio_if),
.uart (uart0),
@@ -172,23 +172,23 @@ core_wrapper u_core_wrapper (
.fault_addr_i (s_bus_fault_addr),
.fault_wstrb_i (s_bus_fault_wstrb),
.fault_reserved_i(s_bus_fault_reserved),
.irq_o (s_rib_irq)
.irq_o (s_ribp_irq)
);
ip_apb_wrapper u_ip_apb_wrapper (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.clk_aud_i (clk_aud_i),
.rst_aud_n_i (rst_aud_n_i),
.tmr_capch_i (s_tmr_capch),
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.clk_aud_i (clk_aud_i),
.rst_aud_n_i (rst_aud_n_i),
.tmr_capch_i (s_tmr_capch),
`include "soc_ip_apb_wrapper_fabric.svh"
.uart (u_uart1_if),
.pwm (u_pwm_if),
.ps2 (u_ps2_if),
.ip_sel_i (u_sysctrl_if.ip_sel_o),
.user_gpio (u_user_gpio_if),
.rib_resp_err_o(s_apb_resp_err),
.irq_o (s_apb_irq)
.uart (u_uart1_if),
.pwm (u_pwm_if),
.ps2 (u_ps2_if),
.ip_sel_i (u_sysctrl_if.ip_sel_o),
.user_gpio (u_user_gpio_if),
.ribp_resp_err_o(s_apb_resp_err),
.irq_o (s_apb_irq)
);
endmodule
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