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https://github.com/retroSoC/retroSoC.git
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feat: init sta files
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10 files changed
+172
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@@ -1,7 +1,7 @@
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SOC ?= MINI
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SIMU ?= VCS
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SYNTH ?= NONE
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TIMI ?= NONE
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STA ?= NONE
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# HW
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PDK ?= IHP130
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@@ -46,7 +46,7 @@ $(info CORE [PICORV32, HAZARD3, MDD]: $(CORE))
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$(info IP [NONE, MDD]: $(IP))
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$(info SIMU [VCS, VERILATOR, IVERILOG]: $(SIMU))
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$(info SYNTH [NONE, YOSYS, DC]: $(SYNTH))
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$(info TIMI [NONE, OPENSTA, ISTA]: $(TIMI))
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$(info STA [NONE, OPENSTA, ISTA]: $(STA))
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$(info PDK [ICS55, IHP130, SKY130, GF180]: $(PDK))
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$(info HAVE_PLL [YES, NO]: $(HAVE_PLL))
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$(info HAVE_SRAM_IF [YES, NO]: $(HAVE_SRAM_IF))
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@@ -104,4 +104,9 @@ ifeq ($(SYNTH), YOSYS)
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else ifeq ($(SYNTH), DC)
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include syn/dc.mk
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endif
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endif
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ifeq ($(STA), OPENSTA)
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include sta/opensta/opensta.mk
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endif
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@@ -1,17 +0,0 @@
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# report_timing
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read_liberty ../S110/S011HD1P_X256Y4D32_BW_TT_1.2_25.lib
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read_liberty ../S110/scc011ums_hd_lvt_tt_v1p2_25c_basic.lib
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read_liberty ../S110/SP013D3WP_V1p7_typ.lib
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read_liberty ../S110/S013PLLFN_v1.5.1_typ.lib
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read_verilog ../yosys/out/retrosoc_asic_yosys.v
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link_design retrosoc_asic
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#
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read_sdc retrosoc_pll.sdc
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report_checks -path_delay min_max -path_group {CLK_src_xtal CLK_src_ext CLK_xtal_buf CLK_ext_buf CLK_pll CLK_pll_buf CLK_sys_mux_pll CLK_sys_mux_ext CLK_sys_clk_buf CLK_flash_clk_o CLK_cust_qspi_spi_clk_o CLK_cust_psram_sclk_o CLK_cust_spfs_clk_o} -sort_by_slack -slack_max 0.0 -group_path_count 50000 -endpoint_path_count 50000 > retrosoc_sta.log
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# set_propagated_clock clk
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# read_spef gcd_sky130hd.spef
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# set_power_activity -input -activity .1
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# set_power_activity -input_port reset -activity 0
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# report_power
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@@ -1,17 +0,0 @@
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# read lib
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read_liberty /nfs/share/home/zhuangchunan/proj/Flow_CX55/lib_data/ccslib/ics55_LLSC_H7CH_ss_rcworst_1p08_125_nldm.lib
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read_liberty /nfs/share/home/zhuangchunan/proj/Flow_CX55/lib_data/ccslib/ics55_LLSC_H7CL_ss_rcworst_1p08_125_nldm.lib
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read_liberty /nfs/share/home/zhuangchunan/proj/Flow_CX55/lib_data/ccslib/ics55_LLSC_H7CR_ss_rcworst_1p08_125_nldm.lib
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read_liberty /nfs/share/home/zhuangchunan/proj/Flow_CX55/lib_data/ccslib/ICSIOA_N55_3P3_ss_1p08_2p97_125c.lib
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read_verilog /nfs/share/home/zhaoxueyan/dataset_gj_test26/retrosoc_asic-cx55/retrosoc_asic_yosys.v
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link_design retrosoc_asic
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# read sdc
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read_sdc retrosoc_gen2.sdc
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report_checks -path_delay min_max -path_group {CLK_src_xtal CLK_src_ext CLK_xtal_buf CLK_ext_buf CLK_pll CLK_pll_buf CLK_sys_mux_pll CLK_sys_mux_ext CLK_sys_clk_buf CLK_flash_clk_o CLK_cust_qspi_spi_clk_o CLK_cust_psram_sclk_o CLK_cust_spfs_clk_o} -sort_by_slack -slack_max 0.0 -group_path_count 50000 -endpoint_path_count 50000 > retrosoc_sta.log
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# set_propagated_clock clk
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# read_spef gcd_sky130hd.spef
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# set_power_activity -input -activity .1
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# set_power_activity -input_port reset -activity 0
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# report_power
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@@ -1,42 +1,29 @@
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set sdc_version 2.1
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# mini gen2 plus
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# set_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm
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set_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm
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###############################################################################
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#
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# Units
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# capacitive_load_unit : 1 pF
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# current_unit : 0.001 A
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# resistance_unit : 1 kOhm
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# time_unit : 1 ns
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# voltage_unit : 1 V
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###############################################################################
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set_operating_conditions -analysis_type on_chip_variation -library [get_libs {ETSCA_N55_H7BH_DSS_PRCMAX_V1P0_T125.db:ETSCA_N55_H7BH_DSS_PRCMAX_V1P0_T125}]
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# unit: MHz
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set clk_xtal_freq 24.0
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set clk_ext_freq 72.0
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set clk_aud_freq 18.432
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set clk_xtal_period [expr 1000.0 / $clk_xtal_freq]
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set clk_ext_period [expr 1000.0 / $clk_ext_freq]
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set clk_aud_period [expr 1000.0 / $clk_aud_freq]
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set clk_period_factor .2
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# set_operating_conditions -analysis_type on_chip_variation -library [get_libs {ETSCA_N55_H7BH_DSS_PRCMAX_V1P0_T125.db:ETSCA_N55_H7BH_DSS_PRCMAX_V1P0_T125}]
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###############################################################################
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# Clock Related Information
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###############################################################################
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create_clock -name CLK_u_xtal_io_pad_u_P65_1233_PWE_XC -period 41.666668 -waveform { 0 20.833334 } [get_pins {u_xtal_io_pad.u_P65_1233_PWE/XC}]
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set_clock_uncertainty -setup 0.2 [get_clocks {CLK_u_xtal_io_pad_u_P65_1233_PWE_XC}]
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set_clock_uncertainty -hold 0.1 [get_clocks {CLK_u_xtal_io_pad_u_P65_1233_PWE_XC}]
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create_clock -name CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C -period 10 -waveform { 0 5 } [get_pins {u_extclk_i_pad.u_P65_1233_PBMUX/C}]
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set_clock_uncertainty -setup 0.2 [get_clocks {CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C}]
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set_clock_uncertainty -hold 0.1 [get_clocks {CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C}]
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create_clock -name CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y -period 41.666668 -waveform { 0 20.833334 } [get_pins {u_rcu.u_pll_clk_buf.u_BUFX0P7H7L/Y}]
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set_clock_uncertainty -setup 0.2 [get_clocks {CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y}]
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set_clock_uncertainty -hold 0.1 [get_clocks {CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y}]
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create_clock -name u_audclk_i_pad.u_P65_1233_PBMUX_C -period 81.380 -waveform { 0 40.690 } [get_pins {u_audclk_i_pad.u_P65_1233_PBMUX/C}]
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set_clock_uncertainty -setup 0.2 [get_clocks {u_audclk_i_pad.u_P65_1233_PBMUX_C}]
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set_clock_uncertainty -hold 0.1 [get_clocks {u_audclk_i_pad.u_P65_1233_PBMUX_C}]
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set_timing_derate -cell_delay -net_delay -late 1
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set_timing_derate -net_delay -clock -early 0.95
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set_timing_derate -net_delay -data -early 1
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set_timing_derate -net_delay -clock -early 0.95
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set_timing_derate -net_delay -data -early 1
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set_timing_derate -cell_delay -clock -early 0.95
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set_timing_derate -cell_delay -data -early 1
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create_clock -name clk_ext -period $clk_ext_period [get_pins \u_extclk_i_pad.u_sg13g2_IOPadInOut4mA/p2c]
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create_clock -name clk_aud -period $clk_aud_period [get_pins \u_audclk_i_pad.u_sg13g2_IOPadInOut4mA/p2c]
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###############################################################################
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# Derived Clock related information
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###############################################################################
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# create_generated_clock -name CLK_sys_clk_buf -source [get_pins {u_rcu.u_ext_clk_buf.u_BUFX0P7H7L/Y}] -divide_by 1 -add -master_clock [get_clocks {CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C}] [get_pins {u_rcu.u_sys_clk_buf.u_BUFX0P7H7L/Y}]
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# create_generated_clock -name CLK_sys_clk_buf -source [get_pins {u_rcu.u_ext_clk_buf.u_BUFX0P7H7L/Y}] -divide_by 1 -add -master_clock [get_clocks {clk_ext}] [get_pins {u_rcu.u_sys_clk_buf.u_BUFX0P7H7L/Y}]
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# set_clock_uncertainty -setup 0.2 [get_clocks {CLK_sys_clk_buf}]
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# set_clock_uncertainty -hold 0.1 [get_clocks {CLK_sys_clk_buf}]
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# create_generated_clock -name CLK_cust_qspi_spi_clk_o -source [get_pins {u_rcu.u_sys_clk_buf.u_BUFX0P7H7L/Y}] -divide_by 2 [get_ports {cust_qspi_spi_clk_o_pad}]
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@@ -48,14 +35,14 @@ set_timing_derate -cell_delay -data -early 1
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# create_generated_clock -name CLK_cust_psram_sclk_o -source [get_pins {u_rcu.u_sys_clk_buf.u_BUFX0P7H7L/Y}] -divide_by 2 [get_ports {cust_psram_sclk_o_pad}]
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# set_clock_uncertainty -setup 0.2 [get_clocks {CLK_cust_psram_sclk_o}]
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# set_clock_uncertainty -hold 0.1 [get_clocks {CLK_cust_psram_sclk_o}]
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# set_clock_groups -asynchronous -name CLK_u_xtal_io_pad_u_P65_1233_PWE_XC_1 -group [get_clocks {CLK_u_xtal_io_pad_u_P65_1233_PWE_XC}] -group [get_clocks {CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C CLK_sys_clk_buf CLK_cust_qspi_spi_clk_o CLK_cust_psram_sclk_o CLK_cust_spfs_clk_o}] -group [get_clocks {CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y}]
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# set_clock_groups -asynchronous -name CLK_u_xtal_io_pad_u_P65_1233_PWE_XC_1 -group [get_clocks {CLK_u_xtal_io_pad_u_P65_1233_PWE_XC}] -group [get_clocks {clk_ext CLK_sys_clk_buf CLK_cust_qspi_spi_clk_o CLK_cust_psram_sclk_o CLK_cust_spfs_clk_o}] -group [get_clocks {CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y}]
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###############################################################################
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# Point to Point exceptions
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###############################################################################
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# group_path -name CLK_u_xtal_io_pad_u_P65_1233_PWE_XC_in2reg -from [get_ports {xi_i_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_rx_i_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_miso_i_pad}] -to [get_clocks {CLK_u_xtal_io_pad_u_P65_1233_PWE_XC}]
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# group_path -name CLK_u_xtal_io_pad_u_P65_1233_PWE_XC_reg2out -from [get_clocks {CLK_u_xtal_io_pad_u_P65_1233_PWE_XC}] -to [get_ports {xo_o_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad sys_clkdiv4_o_pad uart_tx_o_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_tx_o_pad cust_uart_rx_i_pad cust_pwm_pwm_0_o_pad cust_pwm_pwm_1_o_pad cust_pwm_pwm_2_o_pad cust_pwm_pwm_3_o_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_spi_clk_o_pad cust_qspi_spi_csn_0_o_pad cust_qspi_spi_csn_1_o_pad cust_qspi_spi_csn_2_o_pad cust_qspi_spi_csn_3_o_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sclk_o_pad cust_psram_ce_o_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_clk_o_pad cust_spfs_cs_o_pad cust_spfs_mosi_o_pad cust_spfs_miso_i_pad}]
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# group_path -name CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C_in2reg -from [get_ports {xi_i_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_rx_i_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_miso_i_pad}] -to [get_clocks {CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C}]
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# group_path -name CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C_reg2out -from [get_clocks {CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C}] -to [get_ports {xo_o_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad sys_clkdiv4_o_pad uart_tx_o_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_tx_o_pad cust_uart_rx_i_pad cust_pwm_pwm_0_o_pad cust_pwm_pwm_1_o_pad cust_pwm_pwm_2_o_pad cust_pwm_pwm_3_o_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_spi_clk_o_pad cust_qspi_spi_csn_0_o_pad cust_qspi_spi_csn_1_o_pad cust_qspi_spi_csn_2_o_pad cust_qspi_spi_csn_3_o_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sclk_o_pad cust_psram_ce_o_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_clk_o_pad cust_spfs_cs_o_pad cust_spfs_mosi_o_pad cust_spfs_miso_i_pad}]
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# group_path -name CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C_in2reg -from [get_ports {xi_i_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_rx_i_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_miso_i_pad}] -to [get_clocks {clk_ext}]
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# group_path -name CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C_reg2out -from [get_clocks {clk_ext}] -to [get_ports {xo_o_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad sys_clkdiv4_o_pad uart_tx_o_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_tx_o_pad cust_uart_rx_i_pad cust_pwm_pwm_0_o_pad cust_pwm_pwm_1_o_pad cust_pwm_pwm_2_o_pad cust_pwm_pwm_3_o_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_spi_clk_o_pad cust_qspi_spi_csn_0_o_pad cust_qspi_spi_csn_1_o_pad cust_qspi_spi_csn_2_o_pad cust_qspi_spi_csn_3_o_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sclk_o_pad cust_psram_ce_o_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_clk_o_pad cust_spfs_cs_o_pad cust_spfs_mosi_o_pad cust_spfs_miso_i_pad}]
|
||||
# group_path -name CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y_in2reg -from [get_ports {xi_i_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_rx_i_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_miso_i_pad}] -to [get_clocks {CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y}]
|
||||
# group_path -name CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y_reg2out -from [get_clocks {CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y}] -to [get_ports {xo_o_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad sys_clkdiv4_o_pad uart_tx_o_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_tx_o_pad cust_uart_rx_i_pad cust_pwm_pwm_0_o_pad cust_pwm_pwm_1_o_pad cust_pwm_pwm_2_o_pad cust_pwm_pwm_3_o_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_spi_clk_o_pad cust_qspi_spi_csn_0_o_pad cust_qspi_spi_csn_1_o_pad cust_qspi_spi_csn_2_o_pad cust_qspi_spi_csn_3_o_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sclk_o_pad cust_psram_ce_o_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_clk_o_pad cust_spfs_cs_o_pad cust_spfs_mosi_o_pad cust_spfs_miso_i_pad}]
|
||||
# group_path -name CLK_sys_clk_buf_in2reg -from [get_ports {xi_i_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_rx_i_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_miso_i_pad}] -to [get_clocks {CLK_sys_clk_buf}]
|
||||
@@ -68,88 +55,138 @@ set_timing_derate -cell_delay -data -early 1
|
||||
# group_path -name CLK_cust_spfs_clk_o_reg2out -from [get_clocks {CLK_cust_spfs_clk_o}] -to [get_ports {xo_o_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad sys_clkdiv4_o_pad uart_tx_o_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_tx_o_pad cust_uart_rx_i_pad cust_pwm_pwm_0_o_pad cust_pwm_pwm_1_o_pad cust_pwm_pwm_2_o_pad cust_pwm_pwm_3_o_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_spi_clk_o_pad cust_qspi_spi_csn_0_o_pad cust_qspi_spi_csn_1_o_pad cust_qspi_spi_csn_2_o_pad cust_qspi_spi_csn_3_o_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sclk_o_pad cust_psram_ce_o_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_clk_o_pad cust_spfs_cs_o_pad cust_spfs_mosi_o_pad cust_spfs_miso_i_pad}]
|
||||
# group_path -name all_in2out -from [get_ports {xi_i_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_rx_i_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_miso_i_pad}] -to [get_ports {xo_o_pad extclk_i_pad pll_cfg_0_i_pad pll_cfg_1_i_pad pll_cfg_2_i_pad clk_bypass_i_pad ext_rst_n_i_pad sys_clkdiv4_o_pad uart_tx_o_pad uart_rx_i_pad gpio_0_io_pad gpio_1_io_pad gpio_2_io_pad gpio_3_io_pad gpio_4_io_pad gpio_5_io_pad gpio_6_io_pad gpio_7_io_pad gpio_8_io_pad gpio_9_io_pad gpio_10_io_pad gpio_11_io_pad gpio_12_io_pad gpio_13_io_pad gpio_14_io_pad gpio_15_io_pad irq_pin_i_pad cust_uart_tx_o_pad cust_uart_rx_i_pad cust_pwm_pwm_0_o_pad cust_pwm_pwm_1_o_pad cust_pwm_pwm_2_o_pad cust_pwm_pwm_3_o_pad cust_ps2_ps2_clk_i_pad cust_ps2_ps2_dat_i_pad cust_i2c_scl_io_pad cust_i2c_sda_io_pad cust_qspi_spi_clk_o_pad cust_qspi_spi_csn_0_o_pad cust_qspi_spi_csn_1_o_pad cust_qspi_spi_csn_2_o_pad cust_qspi_spi_csn_3_o_pad cust_qspi_dat_0_io_pad cust_qspi_dat_1_io_pad cust_qspi_dat_2_io_pad cust_qspi_dat_3_io_pad cust_psram_sclk_o_pad cust_psram_ce_o_pad cust_psram_sio0_io_pad cust_psram_sio1_io_pad cust_psram_sio2_io_pad cust_psram_sio3_io_pad cust_spfs_clk_o_pad cust_spfs_cs_o_pad cust_spfs_mosi_o_pad cust_spfs_miso_i_pad}]
|
||||
# set_case_analysis 1 [get_pins {u_rcu.u_sys_mux.u_MUX2X0P5H7L/S0}]
|
||||
# set_load -pin_load 8 [get_ports {xo_o_pad}]
|
||||
# set_load -pin_load 8 [get_ports {extclk_i_pad}]
|
||||
# set_load -pin_load 8 [get_ports {pll_cfg_0_i_pad}]
|
||||
# set_load -pin_load 8 [get_ports {pll_cfg_1_i_pad}]
|
||||
# set_load -pin_load 8 [get_ports {pll_cfg_2_i_pad}]
|
||||
# set_load -pin_load 8 [get_ports {clk_bypass_i_pad}]
|
||||
# set_load -pin_load 8 [get_ports {ext_rst_n_i_pad}]
|
||||
# set_load -pin_load 8 [get_ports {sys_clkdiv4_o_pad}]
|
||||
# set_load -pin_load 8 [get_ports {uart_tx_o_pad}]
|
||||
# set_load -pin_load 8 [get_ports {uart_rx_i_pad}]
|
||||
# set_load -pin_load 8 [get_ports {gpio_0_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {gpio_1_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {gpio_2_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {gpio_3_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {gpio_4_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {gpio_5_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {gpio_6_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {gpio_7_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {gpio_8_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {gpio_9_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {gpio_10_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {gpio_11_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {gpio_12_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {gpio_13_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {gpio_14_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {gpio_15_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {irq_pin_i_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_uart_tx_o_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_uart_rx_i_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_pwm_pwm_0_o_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_pwm_pwm_1_o_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_pwm_pwm_2_o_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_pwm_pwm_3_o_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_ps2_ps2_clk_i_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_ps2_ps2_dat_i_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_i2c_scl_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_i2c_sda_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_qspi_spi_clk_o_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_qspi_spi_csn_0_o_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_qspi_spi_csn_1_o_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_qspi_spi_csn_2_o_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_qspi_spi_csn_3_o_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_qspi_dat_0_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_qspi_dat_1_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_qspi_dat_2_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_qspi_dat_3_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_psram_sclk_o_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_psram_ce_o_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_psram_sio0_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_psram_sio1_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_psram_sio2_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_psram_sio3_io_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_spfs_clk_o_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_spfs_cs_o_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_spfs_mosi_o_pad}]
|
||||
# set_load -pin_load 8 [get_ports {cust_spfs_miso_i_pad}]
|
||||
|
||||
set_input_transition .1 [all_inputs]
|
||||
set_clock_uncertainty -setup 0.2 [get_clocks clk_ext]
|
||||
set_clock_uncertainty -hold 0.1 [get_clocks clk_ext]
|
||||
set_clock_uncertainty -setup 0.2 [get_clocks clk_aud]
|
||||
set_clock_uncertainty -hold 0.1 [get_clocks clk_aud]
|
||||
|
||||
set_timing_derate -cell_delay -net_delay -late 1
|
||||
set_timing_derate -net_delay -clock -early 0.95
|
||||
set_timing_derate -net_delay -data -early 1
|
||||
set_timing_derate -net_delay -clock -early 0.95
|
||||
set_timing_derate -net_delay -data -early 1
|
||||
set_timing_derate -cell_delay -clock -early 0.95
|
||||
set_timing_derate -cell_delay -data -early 1
|
||||
# Clock Group
|
||||
###############################################################################
|
||||
set_clock_groups -name cgp_async -asynchronous -group [get_clocks clk_ext] -group [get_clocks clk_aud]
|
||||
###############################################################################
|
||||
# Input/Output Delay
|
||||
###############################################################################
|
||||
|
||||
###############################################################################
|
||||
# Pin drive/load
|
||||
###############################################################################
|
||||
# set_load -pin_load 8 [get_ports extclk_i_pad]
|
||||
# set_load -pin_load 8 [get_ports audclk_i_pad]
|
||||
# set_load -pin_load 8 [get_ports ext_rst_n_i_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_0_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_1_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_2_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_3_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_4_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_5_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_6_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_7_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_8_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_9_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_10_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_11_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_12_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_13_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_14_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_15_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_16_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_17_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_18_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_19_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_20_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_21_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_22_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_23_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_24_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_25_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_26_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_27_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_28_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_29_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_30_io_pad]
|
||||
# set_load -pin_load 8 [get_ports gpio_31_io_pad]
|
||||
# set_load -pin_load 8 [get_ports uart0_tx_o_pad]
|
||||
# set_load -pin_load 8 [get_ports uart0_rx_i_pad]
|
||||
# set_load -pin_load 8 [get_ports xpi_sck_o_pad]
|
||||
# set_load -pin_load 8 [get_ports xpi_nss0_o_pad]
|
||||
# set_load -pin_load 8 [get_ports xpi_nss1_o_pad]
|
||||
# set_load -pin_load 8 [get_ports xpi_nss2_o_pad]
|
||||
# set_load -pin_load 8 [get_ports xpi_nss3_o_pad]
|
||||
# set_load -pin_load 8 [get_ports xpi_dat0_io_pad]
|
||||
# set_load -pin_load 8 [get_ports xpi_dat1_io_pad]
|
||||
# set_load -pin_load 8 [get_ports xpi_dat2_io_pad]
|
||||
# set_load -pin_load 8 [get_ports xpi_dat3_io_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_clk_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_cke_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_cs_n_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_ras_n_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_cas_n_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_we_n_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_ba0_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_ba1_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_addr0_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_addr1_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_addr2_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_addr3_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_addr4_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_addr5_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_addr6_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_addr7_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_addr8_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_addr9_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_addr10_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_addr11_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_addr12_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_dqm0_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_dqm1_o_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_dq0_io_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_dq1_io_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_dq2_io_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_dq3_io_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_dq4_io_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_dq5_io_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_dq6_io_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_dq7_io_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_dq8_io_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_dq9_io_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_dq10_io_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_dq11_io_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_dq12_io_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_dq13_io_pad]
|
||||
# set_load -pin_load 8 [get_ports sdram_dq14_io_pad]
|
||||
###############################################################################
|
||||
# False Path
|
||||
###############################################################################
|
||||
set_false_path -from [get_cells \u_rcu.u_ext_rst_sync*]
|
||||
set_false_path -from [get_cells s_sys_rst_n_reg]
|
||||
set_false_path -from [get_cells \u_rcu.u_aud_rst_sync*]
|
||||
set_false_path -from [get_cells s_aud_rst_n_reg]
|
||||
|
||||
###############################################################################
|
||||
|
||||
# set_wire_load_mode top
|
||||
# set_max_fanout 32 [current_design]
|
||||
# set_max_transition 1.7 [get_clocks {CLK_sys_clk_buf}] -clock_path -rise
|
||||
# set_max_transition 1.7 [get_clocks {CLK_sys_clk_buf}] -clock_path -fall
|
||||
# set_max_transition 3.4 [get_clocks {CLK_sys_clk_buf}] -data_path -rise
|
||||
# set_max_transition 3.4 [get_clocks {CLK_sys_clk_buf}] -data_path -fall
|
||||
# set_max_transition 3.4 [get_clocks {CLK_cust_qspi_spi_clk_o}] -clock_path -rise
|
||||
# set_max_transition 3.4 [get_clocks {CLK_cust_qspi_spi_clk_o}] -clock_path -fall
|
||||
# set_max_transition 6.8 [get_clocks {CLK_cust_qspi_spi_clk_o}] -data_path -rise
|
||||
# set_max_transition 6.8 [get_clocks {CLK_cust_qspi_spi_clk_o}] -data_path -fall
|
||||
# set_max_transition 7.083333 [get_clocks {CLK_u_xtal_io_pad_u_P65_1233_PWE_XC}] -clock_path -rise
|
||||
# set_max_transition 7.083333 [get_clocks {CLK_u_xtal_io_pad_u_P65_1233_PWE_XC}] -clock_path -fall
|
||||
# set_max_transition 14.166667 [get_clocks {CLK_u_xtal_io_pad_u_P65_1233_PWE_XC}] -data_path -rise
|
||||
# set_max_transition 14.166667 [get_clocks {CLK_u_xtal_io_pad_u_P65_1233_PWE_XC}] -data_path -fall
|
||||
# set_max_transition 3.4 [get_clocks {CLK_cust_psram_sclk_o}] -clock_path -rise
|
||||
# set_max_transition 3.4 [get_clocks {CLK_cust_psram_sclk_o}] -clock_path -fall
|
||||
# set_max_transition 6.8 [get_clocks {CLK_cust_psram_sclk_o}] -data_path -rise
|
||||
# set_max_transition 6.8 [get_clocks {CLK_cust_psram_sclk_o}] -data_path -fall
|
||||
# set_max_transition 1.7 [get_clocks {CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C}] -clock_path -rise
|
||||
# set_max_transition 1.7 [get_clocks {CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C}] -clock_path -fall
|
||||
# set_max_transition 3.4 [get_clocks {CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C}] -data_path -rise
|
||||
# set_max_transition 3.4 [get_clocks {CLK_u_extclk_i_pad_u_P65_1233_PBMUX_C}] -data_path -fall
|
||||
# set_max_transition 3.4 [get_clocks {CLK_cust_spfs_clk_o}] -clock_path -rise
|
||||
# set_max_transition 3.4 [get_clocks {CLK_cust_spfs_clk_o}] -clock_path -fall
|
||||
# set_max_transition 6.8 [get_clocks {CLK_cust_spfs_clk_o}] -data_path -rise
|
||||
# set_max_transition 6.8 [get_clocks {CLK_cust_spfs_clk_o}] -data_path -fall
|
||||
# set_max_transition 1.7 [get_clocks {clk_ext}] -clock_path -rise
|
||||
# set_max_transition 1.7 [get_clocks {clk_ext}] -clock_path -fall
|
||||
# set_max_transition 3.4 [get_clocks {clk_ext}] -data_path -rise
|
||||
# set_max_transition 3.4 [get_clocks {clk_ext}] -data_path -fall
|
||||
# set_max_transition 7.083333 [get_clocks {CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y}] -clock_path -rise
|
||||
# set_max_transition 7.083333 [get_clocks {CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y}] -clock_path -fall
|
||||
# set_max_transition 14.166667 [get_clocks {CLK_u_rcu_u_pll_clk_buf_u_BUFX0P7H7L_Y}] -data_path -rise
|
||||
@@ -0,0 +1,5 @@
|
||||
|
||||
sta:
|
||||
sta $(RTL_PATH)/../../sta/opensta/opensta.tcl -threads max
|
||||
|
||||
.PHONY: sta
|
||||
@@ -0,0 +1,14 @@
|
||||
# report_timing
|
||||
read_liberty pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib
|
||||
read_liberty pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
read_verilog syn/yosys/.synth_build/out/retrosoc_asic_yosys.v
|
||||
link_design retrosoc_asic
|
||||
read_sdc sta/opensta/gen2.sdc
|
||||
|
||||
report_checks -path_delay min_max -path_group {clk_ext clk_aud } -sort_by_slack -slack_max 0.0 -group_path_count 1000 -endpoint_path_count 1000 > sta/opensta/retrosoc_sta.log
|
||||
|
||||
# set_propagated_clock clk
|
||||
# read_spef gcd_sky130hd.spef
|
||||
# set_power_activity -input -activity .1
|
||||
# set_power_activity -input_port reset -activity 0
|
||||
# report_power
|
||||
File renamed without changes.
File renamed without changes.
File renamed without changes.
@@ -22,28 +22,7 @@ set root_dir [file dirname [file dirname [file dirname [file dirname [info scrip
|
||||
|
||||
puts "0. Executing init_tech: load technology from Github PDK"
|
||||
|
||||
if {$pdk == "S110"} {
|
||||
set pdk_dir "$root_dir/pdk/s110"
|
||||
set pdk_cells_lib ${pdk_dir}
|
||||
set pdk_sram_lib ${pdk_dir}
|
||||
set pdk_io_lib ${pdk_dir}
|
||||
set pdk_pll_lib ${pdk_dir}
|
||||
set tech_cells [list "$pdk_cells_lib/scc011ums_hd_lvt_tt_v1p2_25c_basic.lib"]
|
||||
set tech_macros [glob -nocomplain -directory $pdk_sram_lib *_TT_1.2_25.lib]
|
||||
lappend tech_macros "$pdk_io_lib/SP013D3WP_V1p7_typ.lib"
|
||||
lappend tech_macros "$pdk_pll_lib/S013PLLFN_v1.5.1_typ.lib"
|
||||
# for hilomap
|
||||
set tech_cell_tiehi {LVT_PULLHD1 Z}
|
||||
set tech_cell_tielo {LVT_PULLHD0 Z}
|
||||
set dff_dont_use_cells [list "LVT_CLKLAHAQHDV1" "LVT_CLKLAHAQHDV2" "LVT_CLKLAHAQHDV4" "LVT_CLKLAHAQHDV8" "LVT_CLKLAHQHDV1" "LVT_CLKLAHQHDV2" "LVT_CLKLAHQHDV4" "LVT_CLKLAHQHDV8" "LVT_DGRSNHDV1" "LVT_DGRSNHDV2" "LVT_DGRSNHDV4" "LVT_DRSNHDV1" "LVT_DRSNHDV2" "LVT_DRSNHDV4" "LVT_DXHDV1" "LVT_DXHDV2" "LVT_DXHDV4" "LVT_EDGRNHDV1" "LVT_EDGRNHDV2" "LVT_EDGRNHDV4" "LVT_EDGRNQHDV1" "LVT_EDGRNQHDV2" "LVT_EDGRNQHDV4" "LVT_EDHDV1" "LVT_EDHDV2" "LVT_EDHDV4" "LVT_EDQHDV1" "LVT_EDQHDV2" "LVT_EDQHDV4" "LVT_EDRNHDV1" "LVT_EDRNHDV2" "LVT_EDRNHDV4" "LVT_EDRNQHDV1" "LVT_EDRNQHDV2" "LVT_EDRNQHDV4" "LVT_LAHHDV1" "LVT_LAHHDV2" "LVT_LAHHDV4" "LVT_LAHRNHDV1" "LVT_LAHRNHDV2" "LVT_LAHRNHDV4" "LVT_LAHRSNHDV1" "LVT_LAHRSNHDV1" "LVT_LAHRSNHDV2" "LVT_LAHRSNHDV2" "LVT_LAHRSNHDV4" "LVT_LAHRSNHDV4" "LVT_LAHSNHDV1" "LVT_LAHSNHDV2" "LVT_LAHSNHDV4" "LVT_LALHDV1" "LVT_LALHDV2" "LVT_LALHDV4" "LVT_LALRNHDV1" "LVT_LALRNHDV2" "LVT_LALRNHDV4" "LVT_LALRSNHDV1" "LVT_LALRSNHDV1" "LVT_LALRSNHDV2" "LVT_LALRSNHDV2" "LVT_LALRSNHDV4" "LVT_LALRSNHDV4" "LVT_LALSNHDV1" "LVT_LALSNHDV2" "LVT_LALSNHDV4" "LVT_NDRSNHDV1" "LVT_NDRSNHDV1" "LVT_NDRSNHDV2" "LVT_NDRSNHDV2" "LVT_NDRSNHDV4" "LVT_NDRSNHDV4" "LVT_SDGRNHDV1" "LVT_SDGRNHDV2" "LVT_SDGRNHDV4" "LVT_SDGRNQHDV1" "LVT_SDGRNQHDV2" "LVT_SDGRNQHDV4" "LVT_SDGRSNHDV1" "LVT_SDGRSNHDV1" "LVT_SDGRSNHDV2" "LVT_SDGRSNHDV2" "LVT_SDGRSNHDV4" "LVT_SDGRSNHDV4" "LVT_SDGSNHDV1" "LVT_SDGSNHDV2" "LVT_SDGSNHDV4" "LVT_SDHDV1" "LVT_SDHDV2" "LVT_SDHDV4" "LVT_SDQHDV1" "LVT_SDQHDV2" "LVT_SDQHDV4" "LVT_SDRNHDV1" "LVT_SDRNHDV2" "LVT_SDRNHDV4" "LVT_SDRNQHDV1" "LVT_SDRNQHDV2" "LVT_SDRNQHDV4" "LVT_SDRSNHDV1" "LVT_SDRSNHDV1" "LVT_SDRSNHDV2" "LVT_SDRSNHDV2" "LVT_SDRSNHDV4" "LVT_SDRSNHDV4" "LVT_SDSNHDV1" "LVT_SDSNHDV2" "LVT_SDSNHDV4" "LVT_SDXHDV1" "LVT_SDXHDV1" "LVT_SDXHDV2" "LVT_SDXHDV2" "LVT_SDXHDV4" "LVT_SDXHDV4" "LVT_SEDGRNHDV1" "LVT_SEDGRNHDV2" "LVT_SEDGRNHDV4" "LVT_SEDGRNQHDV1" "LVT_SEDGRNQHDV2" "LVT_SEDGRNQHDV4" "LVT_SEDHDV1" "LVT_SEDHDV2" "LVT_SEDHDV4" "LVT_SEDQHDV1" "LVT_SEDQHDV2" "LVT_SEDQHDV4" "LVT_SEDRNHDV1" "LVT_SEDRNHDV2" "LVT_SEDRNHDV4" "LVT_SEDRNQHDV1" "LVT_SEDRNQHDV2" "LVT_SEDRNQHDV4" "LVT_SNDHDV1" "LVT_SNDHDV2" "LVT_SNDHDV4" "LVT_SNDRNHDV1" "LVT_SNDRNHDV2" "LVT_SNDRNHDV4" "LVT_SNDRSNHDV1" "LVT_SNDRSNHDV1" "LVT_SNDRSNHDV1" "LVT_SNDRSNHDV2" "LVT_SNDRSNHDV2" "LVT_SNDRSNHDV2" "LVT_SNDRSNHDV4" "LVT_SNDRSNHDV4" "LVT_SNDRSNHDV4" "LVT_SNDSNHDV1" "LVT_SNDSNHDV2" "LVT_SNDSNHDV4"]
|
||||
set comb_dont_use_cells [list "LVT_AO222HDV0" "LVT_AO222HDV1" "LVT_AO222HDV2" "LVT_AO222HDV4" "LVT_AO33HDV0" "LVT_AO33HDV1" "LVT_AO33HDV2" "LVT_AO33HDV4" "LVT_AOI222HDV0" "LVT_AOI222HDV1" "LVT_AOI222HDV2" "LVT_AOI222HDV4" "LVT_AOI33HDV0" "LVT_AOI33HDV1" "LVT_AOI33HDV2" "LVT_AOI33HDV4" "LVT_CKMUX2HDV0" "LVT_CKMUX2HDV1" "LVT_CKMUX2HDV2" "LVT_CKMUX2HDV4" "LVT_CLKAND2HDV0" "LVT_CLKAND2HDV1" "LVT_CLKAND2HDV2" "LVT_CLKAND2HDV4" "LVT_CLKAND2HDV8" "LVT_CLKBUFHDV0" "LVT_CLKBUFHDV1" "LVT_CLKBUFHDV12" "LVT_CLKBUFHDV16" "LVT_CLKBUFHDV2" "LVT_CLKBUFHDV20" "LVT_CLKBUFHDV24" "LVT_CLKBUFHDV3" "LVT_CLKBUFHDV4" "LVT_CLKBUFHDV6" "LVT_CLKBUFHDV8" "LVT_CLKLAHAQHDV1" "LVT_CLKLAHAQHDV2" "LVT_CLKLAHAQHDV4" "LVT_CLKLAHAQHDV8" "LVT_CLKLAHQHDV1" "LVT_CLKLAHQHDV2" "LVT_CLKLAHQHDV4" "LVT_CLKLAHQHDV8" "LVT_CLKLANAQHDV1" "LVT_CLKLANAQHDV2" "LVT_CLKLANAQHDV4" "LVT_CLKLANAQHDV8" "LVT_CLKLANQHDV1" "LVT_CLKLANQHDV12" "LVT_CLKLANQHDV16" "LVT_CLKLANQHDV2" "LVT_CLKLANQHDV20" "LVT_CLKLANQHDV24" "LVT_CLKLANQHDV3" "LVT_CLKLANQHDV4" "LVT_CLKLANQHDV6" "LVT_CLKLANQHDV8" "LVT_CLKNAND2HDV0" "LVT_CLKNAND2HDV1" "LVT_CLKNAND2HDV2" "LVT_CLKNAND2HDV3" "LVT_CLKNAND2HDV4" "LVT_CLKNAND2HDV8" "LVT_CLKNHDV0" "LVT_CLKNHDV1" "LVT_CLKNHDV12" "LVT_CLKNHDV16" "LVT_CLKNHDV2" "LVT_CLKNHDV20" "LVT_CLKNHDV24" "LVT_CLKNHDV3" "LVT_CLKNHDV4" "LVT_CLKNHDV6" "LVT_CLKNHDV8" "LVT_CLKXOR2HDV0" "LVT_CLKXOR2HDV1" "LVT_CLKXOR2HDV2" "LVT_CLKXOR2HDV4" "LVT_DEL1HDV1" "LVT_DEL1HDV4" "LVT_DEL2HDV1" "LVT_DEL2HDV4" "LVT_DEL3HDV1" "LVT_DEL3HDV4" "LVT_DEL4HDV1" "LVT_DEL4HDV4" "LVT_FDCAPHD16" "LVT_FDCAPHD32" "LVT_FDCAPHD4" "LVT_FDCAPHD64" "LVT_FDCAPHD8" "LVT_F_DIODEHD2" "LVT_F_DIODEHD4" "LVT_F_DIODEHD8" "LVT_I2NOR4HDV0" "LVT_I2NOR4HDV1" "LVT_I2NOR4HDV2" "LVT_I2NOR4HDV4" "LVT_IAO22HDV0" "LVT_IAO22HDV1" "LVT_IAO22HDV2" "LVT_IAO22HDV4" "LVT_INOR4HDV0" "LVT_INOR4HDV1" "LVT_INOR4HDV2" "LVT_INOR4HDV4" "LVT_MAOI222HDV0" "LVT_MAOI222HDV1" "LVT_MAOI222HDV2" "LVT_MAOI222HDV4" "LVT_MUX4HDV1" "LVT_NOR4HDV0" "LVT_NOR4HDV1" "LVT_NOR4HDV2" "LVT_NOR4HDV3" "LVT_NOR4HDV4" "LVT_NOR4HDV8" "LVT_OA222HDV0" "LVT_OA222HDV1" "LVT_OA222HDV2" "LVT_OA222HDV4" "LVT_OA33HDV0" "LVT_OA33HDV1" "LVT_OA33HDV2" "LVT_OA33HDV4" "LVT_OAI222HDV0" "LVT_OAI222HDV1" "LVT_OAI222HDV2" "LVT_OAI222HDV4" "LVT_OAI33HDV0" "LVT_OAI33HDV1" "LVT_OAI33HDV2" "LVT_OAI33HDV4" "LVT_PULLHD0" "LVT_PULLHD1" "LVT_TBUFHDV0" "LVT_TBUFHDV1" "LVT_TBUFHDV12" "LVT_TBUFHDV16" "LVT_TBUFHDV2" "LVT_TBUFHDV20" "LVT_TBUFHDV24" "LVT_TBUFHDV3" "LVT_TBUFHDV4" "LVT_TBUFHDV6" "LVT_TBUFHDV8" "LVT_XNOR4HDV0" "LVT_XNOR4HDV1" "LVT_XNOR4HDV2" "LVT_XNOR4HDV4"]
|
||||
# set the dff dont_use
|
||||
set dff_cells_dont_use_list [lmap cell $dff_dont_use_cells {concat "-dont_use" $cell}]
|
||||
set dff_cells_dont_use_args [concat {*}$dff_cells_dont_use_list]
|
||||
# set the comb dont_use
|
||||
set comb_cells_dont_use_list [lmap cell $comb_dont_use_cells {concat "-dont_use" $cell}]
|
||||
set comb_cells_dont_use_args [concat {*}$comb_cells_dont_use_list]
|
||||
} elseif {$pdk == "IHP130"} {
|
||||
if {$pdk == "IHP130"} {
|
||||
set pdk_dir "$root_dir/pdk/IHP-Open-PDK"
|
||||
set pdk_cells_lib ${pdk_dir}/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib
|
||||
set pdk_sram_lib ${pdk_dir}/ihp-sg13g2/libs.ref/sg13g2_sram/lib
|
||||
|
||||
Reference in new issue
Block a user