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feat: add I2S support with formal verification and testbench

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- Updated filelist to include I2S related files.
- Enhanced formal file generation script to support I2S target.
- Introduced I2S formal design and properties for verification.
- Modified formal makefile to include I2S targets and source files.
- Added I2S related source files to software build.
- Updated style audit to include I2S files.
- Implemented I2S helper functions in C tests.
- Created I2S testbench for RTL simulation.
- Added regression test for I2S controller functionality.
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maksyuki committed 2026-08-17 15:53:39 +08:00
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commit 270343a891
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docs/axi4-stream.md
+3 -2
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@@ -20,10 +20,11 @@ IDs, destinations, and user sidebands are currently zero.
## Configuration and PIO Fallback
I2S register offset `0x20` is `STREAM_CTRL`: bit 0 selects AXI4-Stream as the
I2S register offset `0x00C` is `STREAM_CTRL`: bit 0 selects AXI4-Stream as the
TX FIFO producer and bit 1 selects AXI4-Stream as the RX FIFO consumer. A clear
bit preserves the existing `TXDATA` or `RXDATA` PIO behavior. Software must not
change a stream-select bit while that direction is active.
change a stream-select bit while that direction is active. `TXDATA` is `0x01C`
and `RXDATA` is `0x020`.
DVP register offset `0x0C` is `STREAM_CTRL`: bit 0 selects AXI4-Stream as the
RX FIFO consumer. When clear, reads of `RXDATA` retain the existing pop