refactor: refactor APB4 and AXI4 references in RTL and test files

- Updated RTL style audit to reflect new APB4 naming conventions.
- Changed performance log parsing to accommodate new APB4 wait signals.
- Modified AXI4 interconnect and rib bus testbenches to use updated performance wait signals.
- Adjusted IRQ topology testbench to use new APB4 peripheral and system IRQ widths.
- Updated sysctrl testbench to reflect changes in APB4 performance wait signals.
- Refined memory map tests to check for new APB4 definitions.
- Enhanced performance log tests to validate new APB4 wait signal parsing.
- Revised SOC topology tests to ensure correct APB4 peripheral and system bindings.
- Updated user extensions tests to align with new APB4 interface naming.

app/apps/benchmark/main.c

@@ -115,7 +115,7 @@ static void rs_benchmark_report(const char *region, const char *operation, uint3
     rs_benchmark_put_hex(checksum);
     rs_benchmark_put_counter(" cycles=", cycles);
     rs_benchmark_put_counter(" mgmt_wait=", snapshot->mgmt_wait);
-    rs_benchmark_put_counter(" apb4_wait=", snapshot->apb4_wait);
+    rs_benchmark_put_counter(" apb4_periph_wait=", snapshot->apb4_periph_wait);
     rs_benchmark_put_counter(" sdram_wait=", snapshot->sdram_wait);
     rs_benchmark_put_counter(" psram_wait=", snapshot->psram_wait);
     rs_benchmark_put_counter(" flash_wait=", snapshot->flash_wait);

crt/include/retrosoc/core/soc.h

@@ -98,11 +98,11 @@
 // sdram
 #define reg_sdram_clkdiv                RS_SOC_REG32(RS_SOC_APB4_SDRAM_BASE, UINT32_C(0x00))
 #define reg_sdram_cfg                   RS_SOC_REG32(RS_SOC_APB4_SDRAM_BASE, UINT32_C(0x04))
-#define reg_user_ip_reg0                RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x00))
-#define reg_user_ip_reg1                RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x04))
-#define reg_user_ip_reg2                RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x08))
-#define reg_user_ip_reg3                RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x0C))
-#define reg_user_ip_reg4                RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x10))
-#define reg_user_ip_reg5                RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x14))
-#define reg_user_ip_reg6                RS_SOC_REG32(RS_SOC_APB_USER_IP_BASE, UINT32_C(0x18))
+#define reg_user_ip_reg0                RS_SOC_REG32(RS_SOC_APB4_USER_IP_BASE, UINT32_C(0x00))
+#define reg_user_ip_reg1                RS_SOC_REG32(RS_SOC_APB4_USER_IP_BASE, UINT32_C(0x04))
+#define reg_user_ip_reg2                RS_SOC_REG32(RS_SOC_APB4_USER_IP_BASE, UINT32_C(0x08))
+#define reg_user_ip_reg3                RS_SOC_REG32(RS_SOC_APB4_USER_IP_BASE, UINT32_C(0x0C))
+#define reg_user_ip_reg4                RS_SOC_REG32(RS_SOC_APB4_USER_IP_BASE, UINT32_C(0x10))
+#define reg_user_ip_reg5                RS_SOC_REG32(RS_SOC_APB4_USER_IP_BASE, UINT32_C(0x14))
+#define reg_user_ip_reg6                RS_SOC_REG32(RS_SOC_APB4_USER_IP_BASE, UINT32_C(0x18))
 #endif

crt/include/retrosoc/hal/perf.h

@@ -9,8 +9,8 @@ typedef struct {
     uint64_t mgmt_wait;
     uint64_t user_wait;
     uint64_t dma_wait;
-    uint64_t apb4_wait;
-    uint64_t apb_wait;
+    uint64_t apb4_periph_wait;
+    uint64_t apb4_system_wait;
     uint64_t sdram_wait;
     uint64_t psram_wait;
     uint64_t flash_wait;

crt/include/retrosoc/hal/sysctrl.h

@@ -10,8 +10,8 @@ typedef enum {
     RS_SYSCTRL_PERF_MGMT_WAIT = 0,
     RS_SYSCTRL_PERF_USER_WAIT = 1,
     RS_SYSCTRL_PERF_DMA_WAIT = 2,
-    RS_SYSCTRL_PERF_APB4_WAIT = 3,
-    RS_SYSCTRL_PERF_APB_WAIT = 4,
+    RS_SYSCTRL_PERF_APB4_PERIPH_WAIT = 3,
+    RS_SYSCTRL_PERF_APB4_SYSTEM_WAIT = 4,
     RS_SYSCTRL_PERF_SDRAM_WAIT = 5,
     RS_SYSCTRL_PERF_PSRAM_WAIT = 6,
     RS_SYSCTRL_PERF_FLASH_WAIT = 7,

crt/src/core/archinfo.c

@@ -27,7 +27,7 @@ static rs_status_t rs_archinfo_status(archinfo_status_t status) {
 }
 
 rs_status_t rs_archinfo_read(rs_archinfo_t *info) {
-    return rs_archinfo_status(archinfo_read((uintptr_t)RS_SOC_APB_ARCHINFO_BASE, info));
+    return rs_archinfo_status(archinfo_read((uintptr_t)RS_SOC_APB4_ARCHINFO_BASE, info));
 }
 
 rs_status_t rs_archinfo_validate_build(const rs_archinfo_t *info) {
@@ -44,7 +44,7 @@ rs_status_t rs_archinfo_validate_build(const rs_archinfo_t *info) {
 
 rs_status_t rs_archinfo_read_device_id(uint32_t device_id[4]) {
     return rs_archinfo_status(
-        archinfo_read_device_id((uintptr_t)RS_SOC_APB_ARCHINFO_BASE, device_id));
+        archinfo_read_device_id((uintptr_t)RS_SOC_APB4_ARCHINFO_BASE, device_id));
 }
 
 void ip_archinfo_test(int argc, char **argv) {

crt/src/hal/crc.c

@@ -30,36 +30,37 @@ rs_status_t rs_crc_get_profile(rs_crc_profile_t profile, rs_crc_config_t *config
 }
 
 rs_status_t rs_crc_init(const rs_crc_config_t *config) {
-    return rs_crc_status(crc_init((uintptr_t)RS_SOC_APB_CRC_BASE, config));
+    return rs_crc_status(crc_init((uintptr_t)RS_SOC_APB4_CRC_BASE, config));
 }
 
 rs_status_t rs_crc_start(void) {
-    return rs_crc_status(crc_start((uintptr_t)RS_SOC_APB_CRC_BASE));
+    return rs_crc_status(crc_start((uintptr_t)RS_SOC_APB4_CRC_BASE));
 }
 
 rs_status_t rs_crc_update(const void *data, size_t length) {
-    return rs_crc_status(crc_update((uintptr_t)RS_SOC_APB_CRC_BASE, data, length));
+    return rs_crc_status(crc_update((uintptr_t)RS_SOC_APB4_CRC_BASE, data, length));
 }
 
 rs_status_t rs_crc_finish(uint32_t *result) {
-    return rs_crc_status(crc_finish((uintptr_t)RS_SOC_APB_CRC_BASE, result));
+    return rs_crc_status(crc_finish((uintptr_t)RS_SOC_APB4_CRC_BASE, result));
 }
 
 rs_status_t rs_crc_abort(void) {
-    return rs_crc_status(crc_abort((uintptr_t)RS_SOC_APB_CRC_BASE));
+    return rs_crc_status(crc_abort((uintptr_t)RS_SOC_APB4_CRC_BASE));
 }
 
 rs_status_t rs_crc_compute(const rs_crc_config_t *config, const void *data, size_t length,
                            uint32_t *result) {
-    return rs_crc_status(crc_compute((uintptr_t)RS_SOC_APB_CRC_BASE, config, data, length, result));
+    return rs_crc_status(
+        crc_compute((uintptr_t)RS_SOC_APB4_CRC_BASE, config, data, length, result));
 }
 
 rs_status_t rs_crc_get_status(rs_crc_snapshot_t *snapshot) {
-    return rs_crc_status(crc_get_status((uintptr_t)RS_SOC_APB_CRC_BASE, snapshot));
+    return rs_crc_status(crc_get_status((uintptr_t)RS_SOC_APB4_CRC_BASE, snapshot));
 }
 
 rs_status_t rs_crc_clear_errors(uint32_t mask) {
-    return rs_crc_status(crc_clear_errors((uintptr_t)RS_SOC_APB_CRC_BASE, mask));
+    return rs_crc_status(crc_clear_errors((uintptr_t)RS_SOC_APB4_CRC_BASE, mask));
 }
 
 void rs_crc_shell_test(int argc, char **argv) {

crt/src/hal/perf.c

@@ -24,8 +24,10 @@ rs_status_t rs_perf_snapshot(rs_perf_snapshot_t *snapshot) {
         (rs_sysctrl_read_perf_counter(RS_SYSCTRL_PERF_MGMT_WAIT, &snapshot->mgmt_wait) != RS_OK) ||
         (rs_sysctrl_read_perf_counter(RS_SYSCTRL_PERF_USER_WAIT, &snapshot->user_wait) != RS_OK) ||
         (rs_sysctrl_read_perf_counter(RS_SYSCTRL_PERF_DMA_WAIT, &snapshot->dma_wait) != RS_OK) ||
-        (rs_sysctrl_read_perf_counter(RS_SYSCTRL_PERF_APB4_WAIT, &snapshot->apb4_wait) != RS_OK) ||
-        (rs_sysctrl_read_perf_counter(RS_SYSCTRL_PERF_APB_WAIT, &snapshot->apb_wait) != RS_OK) ||
+        (rs_sysctrl_read_perf_counter(RS_SYSCTRL_PERF_APB4_PERIPH_WAIT,
+                                      &snapshot->apb4_periph_wait) != RS_OK) ||
+        (rs_sysctrl_read_perf_counter(RS_SYSCTRL_PERF_APB4_SYSTEM_WAIT,
+                                      &snapshot->apb4_system_wait) != RS_OK) ||
         (rs_sysctrl_read_perf_counter(RS_SYSCTRL_PERF_SDRAM_WAIT, &snapshot->sdram_wait) !=
          RS_OK) ||
         (rs_sysctrl_read_perf_counter(RS_SYSCTRL_PERF_PSRAM_WAIT, &snapshot->psram_wait) !=

crt/src/hal/ps2.c

@@ -31,53 +31,53 @@ static rs_status_t rs_ps2_status(ps2_status_t status) {
 }
 
 rs_status_t rs_ps2_configure(const rs_ps2_config_t *config, rs_timeout_t timeout) {
-    return rs_ps2_status(ps2_configure(RS_SOC_APB_PS2_BASE, config, timeout));
+    return rs_ps2_status(ps2_configure(RS_SOC_APB4_PS2_BASE, config, timeout));
 }
 
 rs_status_t rs_ps2_init(uint32_t source_clock_hz) {
-    return rs_ps2_status(ps2_init(RS_SOC_APB_PS2_BASE, source_clock_hz));
+    return rs_ps2_status(ps2_init(RS_SOC_APB4_PS2_BASE, source_clock_hz));
 }
 
 rs_status_t rs_ps2_write(const uint8_t *data, size_t length, rs_timeout_t timeout) {
-    return rs_ps2_status(ps2_write(RS_SOC_APB_PS2_BASE, data, length, timeout));
+    return rs_ps2_status(ps2_write(RS_SOC_APB4_PS2_BASE, data, length, timeout));
 }
 
 rs_status_t rs_ps2_read(rs_ps2_rx_byte_t *data, size_t length, rs_timeout_t timeout) {
-    return rs_ps2_status(ps2_read(RS_SOC_APB_PS2_BASE, data, length, timeout));
+    return rs_ps2_status(ps2_read(RS_SOC_APB4_PS2_BASE, data, length, timeout));
 }
 
 rs_status_t rs_ps2_command(uint8_t command, const uint8_t *parameters, size_t parameter_count,
                            rs_timeout_t timeout) {
     return rs_ps2_status(
-        ps2_command(RS_SOC_APB_PS2_BASE, command, parameters, parameter_count, timeout));
+        ps2_command(RS_SOC_APB4_PS2_BASE, command, parameters, parameter_count, timeout));
 }
 
 rs_status_t rs_ps2_identify(rs_ps2_device_info_t *info, rs_timeout_t timeout) {
-    return rs_ps2_status(ps2_identify(RS_SOC_APB_PS2_BASE, info, timeout));
+    return rs_ps2_status(ps2_identify(RS_SOC_APB4_PS2_BASE, info, timeout));
 }
 
 rs_status_t rs_ps2_flush(bool flush_rx, bool flush_tx) {
-    return rs_ps2_status(ps2_flush(RS_SOC_APB_PS2_BASE, flush_rx, flush_tx));
+    return rs_ps2_status(ps2_flush(RS_SOC_APB4_PS2_BASE, flush_rx, flush_tx));
 }
 
 rs_status_t rs_ps2_abort(void) {
-    return rs_ps2_status(ps2_abort(RS_SOC_APB_PS2_BASE));
+    return rs_ps2_status(ps2_abort(RS_SOC_APB4_PS2_BASE));
 }
 
 rs_status_t rs_ps2_get_status(rs_ps2_controller_status_t *status) {
-    return rs_ps2_status(ps2_get_status(RS_SOC_APB_PS2_BASE, status));
+    return rs_ps2_status(ps2_get_status(RS_SOC_APB4_PS2_BASE, status));
 }
 
 rs_status_t rs_ps2_irq_enable(uint32_t mask) {
-    return rs_ps2_status(ps2_irq_enable(RS_SOC_APB_PS2_BASE, mask));
+    return rs_ps2_status(ps2_irq_enable(RS_SOC_APB4_PS2_BASE, mask));
 }
 
 rs_status_t rs_ps2_irq_ack(uint32_t mask) {
-    return rs_ps2_status(ps2_irq_ack(RS_SOC_APB_PS2_BASE, mask));
+    return rs_ps2_status(ps2_irq_ack(RS_SOC_APB4_PS2_BASE, mask));
 }
 
 rs_status_t rs_ps2_irq_test(uint32_t mask) {
-    return rs_ps2_status(ps2_irq_test(RS_SOC_APB_PS2_BASE, mask));
+    return rs_ps2_status(ps2_irq_test(RS_SOC_APB4_PS2_BASE, mask));
 }
 
 void rs_ps2_keyboard_decoder_init(rs_ps2_keyboard_decoder_t *decoder) {
@@ -90,15 +90,15 @@ bool rs_ps2_keyboard_decode_byte(rs_ps2_keyboard_decoder_t *decoder, uint8_t byt
 }
 
 rs_status_t rs_ps2_keyboard_init(rs_ps2_device_info_t *info, rs_timeout_t timeout) {
-    return rs_ps2_status(ps2_keyboard_init(RS_SOC_APB_PS2_BASE, info, timeout));
+    return rs_ps2_status(ps2_keyboard_init(RS_SOC_APB4_PS2_BASE, info, timeout));
 }
 
 rs_status_t rs_ps2_keyboard_set_leds(uint8_t led_mask, rs_timeout_t timeout) {
-    return rs_ps2_status(ps2_keyboard_set_leds(RS_SOC_APB_PS2_BASE, led_mask, timeout));
+    return rs_ps2_status(ps2_keyboard_set_leds(RS_SOC_APB4_PS2_BASE, led_mask, timeout));
 }
 
 rs_status_t rs_ps2_keyboard_set_typematic(uint8_t value, rs_timeout_t timeout) {
-    return rs_ps2_status(ps2_keyboard_set_typematic(RS_SOC_APB_PS2_BASE, value, timeout));
+    return rs_ps2_status(ps2_keyboard_set_typematic(RS_SOC_APB4_PS2_BASE, value, timeout));
 }
 
 void rs_ps2_mouse_decoder_init(rs_ps2_mouse_decoder_t *decoder, uint8_t device_id) {
@@ -111,23 +111,23 @@ bool rs_ps2_mouse_decode_byte(rs_ps2_mouse_decoder_t *decoder, uint8_t byte,
 }
 
 rs_status_t rs_ps2_mouse_init(rs_ps2_device_info_t *info, rs_timeout_t timeout) {
-    return rs_ps2_status(ps2_mouse_init(RS_SOC_APB_PS2_BASE, info, timeout));
+    return rs_ps2_status(ps2_mouse_init(RS_SOC_APB4_PS2_BASE, info, timeout));
 }
 
 rs_status_t rs_ps2_mouse_set_mode(rs_ps2_mouse_mode_t mode, rs_timeout_t timeout) {
-    return rs_ps2_status(ps2_mouse_set_mode(RS_SOC_APB_PS2_BASE, mode, timeout));
+    return rs_ps2_status(ps2_mouse_set_mode(RS_SOC_APB4_PS2_BASE, mode, timeout));
 }
 
 rs_status_t rs_ps2_mouse_set_sample_rate(uint8_t rate, rs_timeout_t timeout) {
-    return rs_ps2_status(ps2_mouse_set_sample_rate(RS_SOC_APB_PS2_BASE, rate, timeout));
+    return rs_ps2_status(ps2_mouse_set_sample_rate(RS_SOC_APB4_PS2_BASE, rate, timeout));
 }
 
 rs_status_t rs_ps2_mouse_set_resolution(uint8_t resolution, rs_timeout_t timeout) {
-    return rs_ps2_status(ps2_mouse_set_resolution(RS_SOC_APB_PS2_BASE, resolution, timeout));
+    return rs_ps2_status(ps2_mouse_set_resolution(RS_SOC_APB4_PS2_BASE, resolution, timeout));
 }
 
 rs_status_t rs_ps2_mouse_enable_reporting(bool enable, rs_timeout_t timeout) {
-    return rs_ps2_status(ps2_mouse_enable_reporting(RS_SOC_APB_PS2_BASE, enable, timeout));
+    return rs_ps2_status(ps2_mouse_enable_reporting(RS_SOC_APB4_PS2_BASE, enable, timeout));
 }
 
 void rs_ps2_shell_test(int argc, char **argv) {

crt/src/hal/pwm.c

@@ -34,107 +34,107 @@ static rs_status_t rs_pwm_status(pwm_status_t status) {
 }
 
 rs_status_t rs_pwm_probe(void) {
-    return rs_pwm_status(pwm_probe((uintptr_t)RS_SOC_APB_PWM_BASE));
+    return rs_pwm_status(pwm_probe((uintptr_t)RS_SOC_APB4_PWM_BASE));
 }
 
 rs_status_t rs_pwm_timer_configure(uint8_t timer, const rs_pwm_timer_config_t *config) {
-    return rs_pwm_status(pwm_timer_configure((uintptr_t)RS_SOC_APB_PWM_BASE, timer, config));
+    return rs_pwm_status(pwm_timer_configure((uintptr_t)RS_SOC_APB4_PWM_BASE, timer, config));
 }
 
 rs_status_t rs_pwm_channel_configure(uint8_t channel, const rs_pwm_channel_config_t *config) {
-    return rs_pwm_status(pwm_channel_configure((uintptr_t)RS_SOC_APB_PWM_BASE, channel, config));
+    return rs_pwm_status(pwm_channel_configure((uintptr_t)RS_SOC_APB4_PWM_BASE, channel, config));
 }
 
 rs_status_t rs_pwm_operator_configure(uint8_t operator_id, const rs_pwm_operator_config_t *config) {
     return rs_pwm_status(
-        pwm_operator_configure((uintptr_t)RS_SOC_APB_PWM_BASE, operator_id, config));
+        pwm_operator_configure((uintptr_t)RS_SOC_APB4_PWM_BASE, operator_id, config));
 }
 
 rs_status_t rs_pwm_fault_configure(const rs_pwm_fault_config_t *config) {
-    return rs_pwm_status(pwm_fault_configure((uintptr_t)RS_SOC_APB_PWM_BASE, config));
+    return rs_pwm_status(pwm_fault_configure((uintptr_t)RS_SOC_APB4_PWM_BASE, config));
 }
 
 rs_status_t rs_pwm_capture_configure(const rs_pwm_capture_config_t *config) {
-    return rs_pwm_status(pwm_capture_configure((uintptr_t)RS_SOC_APB_PWM_BASE, config));
+    return rs_pwm_status(pwm_capture_configure((uintptr_t)RS_SOC_APB4_PWM_BASE, config));
 }
 
 rs_status_t rs_pwm_enable(bool debug_freeze) {
-    return rs_pwm_status(pwm_enable((uintptr_t)RS_SOC_APB_PWM_BASE, debug_freeze));
+    return rs_pwm_status(pwm_enable((uintptr_t)RS_SOC_APB4_PWM_BASE, debug_freeze));
 }
 
 rs_status_t rs_pwm_disable(void) {
-    return rs_pwm_status(pwm_disable((uintptr_t)RS_SOC_APB_PWM_BASE));
+    return rs_pwm_status(pwm_disable((uintptr_t)RS_SOC_APB4_PWM_BASE));
 }
 
 rs_status_t rs_pwm_apply_update(rs_timeout_t timeout) {
-    return rs_pwm_status(pwm_apply_update((uintptr_t)RS_SOC_APB_PWM_BASE, timeout));
+    return rs_pwm_status(pwm_apply_update((uintptr_t)RS_SOC_APB4_PWM_BASE, timeout));
 }
 
 rs_status_t rs_pwm_software_sync(void) {
-    return rs_pwm_status(pwm_software_sync((uintptr_t)RS_SOC_APB_PWM_BASE));
+    return rs_pwm_status(pwm_software_sync((uintptr_t)RS_SOC_APB4_PWM_BASE));
 }
 
 rs_status_t rs_pwm_set_duty(uint8_t channel, uint32_t duty, rs_timeout_t timeout) {
-    return rs_pwm_status(pwm_set_duty((uintptr_t)RS_SOC_APB_PWM_BASE, channel, duty, timeout));
+    return rs_pwm_status(pwm_set_duty((uintptr_t)RS_SOC_APB4_PWM_BASE, channel, duty, timeout));
 }
 
 rs_status_t rs_pwm_fade_configure(uint8_t channel, const rs_pwm_fade_segment_t *segment) {
-    return rs_pwm_status(pwm_fade_configure((uintptr_t)RS_SOC_APB_PWM_BASE, channel, segment));
+    return rs_pwm_status(pwm_fade_configure((uintptr_t)RS_SOC_APB4_PWM_BASE, channel, segment));
 }
 
 rs_status_t rs_pwm_fade_start(uint8_t channel) {
-    return rs_pwm_status(pwm_fade_start((uintptr_t)RS_SOC_APB_PWM_BASE, channel));
+    return rs_pwm_status(pwm_fade_start((uintptr_t)RS_SOC_APB4_PWM_BASE, channel));
 }
 
 rs_status_t rs_pwm_fade_pause(uint8_t channel) {
-    return rs_pwm_status(pwm_fade_pause((uintptr_t)RS_SOC_APB_PWM_BASE, channel));
+    return rs_pwm_status(pwm_fade_pause((uintptr_t)RS_SOC_APB4_PWM_BASE, channel));
 }
 
 rs_status_t rs_pwm_fade_resume(uint8_t channel) {
-    return rs_pwm_status(pwm_fade_resume((uintptr_t)RS_SOC_APB_PWM_BASE, channel));
+    return rs_pwm_status(pwm_fade_resume((uintptr_t)RS_SOC_APB4_PWM_BASE, channel));
 }
 
 rs_status_t rs_pwm_fade_stop(uint8_t channel) {
-    return rs_pwm_status(pwm_fade_stop((uintptr_t)RS_SOC_APB_PWM_BASE, channel));
+    return rs_pwm_status(pwm_fade_stop((uintptr_t)RS_SOC_APB4_PWM_BASE, channel));
 }
 
 rs_status_t rs_pwm_gamma_program(uint8_t channel, const rs_pwm_fade_segment_t *segments,
                                  uint8_t count) {
     return rs_pwm_status(
-        pwm_gamma_program((uintptr_t)RS_SOC_APB_PWM_BASE, channel, segments, count));
+        pwm_gamma_program((uintptr_t)RS_SOC_APB4_PWM_BASE, channel, segments, count));
 }
 
 rs_status_t rs_pwm_gamma_start(uint8_t channel, uint8_t count) {
-    return rs_pwm_status(pwm_gamma_start((uintptr_t)RS_SOC_APB_PWM_BASE, channel, count));
+    return rs_pwm_status(pwm_gamma_start((uintptr_t)RS_SOC_APB4_PWM_BASE, channel, count));
 }
 
 rs_status_t rs_pwm_fault_clear(void) {
-    return rs_pwm_status(pwm_fault_clear((uintptr_t)RS_SOC_APB_PWM_BASE));
+    return rs_pwm_status(pwm_fault_clear((uintptr_t)RS_SOC_APB4_PWM_BASE));
 }
 
 rs_status_t rs_pwm_fault_test(void) {
-    return rs_pwm_status(pwm_fault_test((uintptr_t)RS_SOC_APB_PWM_BASE));
+    return rs_pwm_status(pwm_fault_test((uintptr_t)RS_SOC_APB4_PWM_BASE));
 }
 
 rs_status_t rs_pwm_capture_read(uint8_t channel, uint32_t *timestamp, rs_timeout_t timeout) {
     return rs_pwm_status(
-        pwm_capture_read((uintptr_t)RS_SOC_APB_PWM_BASE, channel, timestamp, timeout));
+        pwm_capture_read((uintptr_t)RS_SOC_APB4_PWM_BASE, channel, timestamp, timeout));
 }
 
 rs_status_t rs_pwm_interrupt_enable(uint32_t mask) {
-    return rs_pwm_status(pwm_interrupt_enable((uintptr_t)RS_SOC_APB_PWM_BASE, mask));
+    return rs_pwm_status(pwm_interrupt_enable((uintptr_t)RS_SOC_APB4_PWM_BASE, mask));
 }
 
 rs_status_t rs_pwm_interrupt_clear(uint32_t mask) {
-    return rs_pwm_status(pwm_interrupt_clear((uintptr_t)RS_SOC_APB_PWM_BASE, mask));
+    return rs_pwm_status(pwm_interrupt_clear((uintptr_t)RS_SOC_APB4_PWM_BASE, mask));
 }
 
 rs_status_t rs_pwm_interrupt_test(uint32_t mask) {
-    return rs_pwm_status(pwm_interrupt_test((uintptr_t)RS_SOC_APB_PWM_BASE, mask));
+    return rs_pwm_status(pwm_interrupt_test((uintptr_t)RS_SOC_APB4_PWM_BASE, mask));
 }
 
 rs_status_t rs_pwm_get_status(rs_pwm_snapshot_t *snapshot) {
-    return rs_pwm_status(pwm_get_status((uintptr_t)RS_SOC_APB_PWM_BASE, snapshot));
+    return rs_pwm_status(pwm_get_status((uintptr_t)RS_SOC_APB4_PWM_BASE, snapshot));
 }
 
 void rs_pwm_shell_test(int argc, char **argv) {

crt/src/hal/rng.c

@@ -32,35 +32,35 @@ static rs_status_t rs_rng_status(rng_status_t status) {
 }
 
 rs_status_t rs_rng_init(const rs_rng_config_t *config) {
-    return rs_rng_status(rng_init((uintptr_t)RS_SOC_APB_RNG_BASE, config));
+    return rs_rng_status(rng_init((uintptr_t)RS_SOC_APB4_RNG_BASE, config));
 }
 
 rs_status_t rs_rng_get_status(rs_rng_snapshot_t *snapshot) {
-    return rs_rng_status(rng_get_status((uintptr_t)RS_SOC_APB_RNG_BASE, snapshot));
+    return rs_rng_status(rng_get_status((uintptr_t)RS_SOC_APB4_RNG_BASE, snapshot));
 }
 
 rs_status_t rs_rng_read_entropy(uint32_t *word, rs_timeout_t timeout) {
-    return rs_rng_status(rng_read_entropy((uintptr_t)RS_SOC_APB_RNG_BASE, word, timeout));
+    return rs_rng_status(rng_read_entropy((uintptr_t)RS_SOC_APB4_RNG_BASE, word, timeout));
 }
 
 rs_status_t rs_rng_read_diagnostic(uint32_t *word, rs_timeout_t timeout) {
-    return rs_rng_status(rng_read_diagnostic((uintptr_t)RS_SOC_APB_RNG_BASE, word, timeout));
+    return rs_rng_status(rng_read_diagnostic((uintptr_t)RS_SOC_APB4_RNG_BASE, word, timeout));
 }
 
 rs_status_t rs_rng_recover(void) {
-    return rs_rng_status(rng_recover((uintptr_t)RS_SOC_APB_RNG_BASE));
+    return rs_rng_status(rng_recover((uintptr_t)RS_SOC_APB4_RNG_BASE));
 }
 
 rs_status_t rs_rng_interrupt_enable(uint32_t mask) {
-    return rs_rng_status(rng_interrupt_enable((uintptr_t)RS_SOC_APB_RNG_BASE, mask));
+    return rs_rng_status(rng_interrupt_enable((uintptr_t)RS_SOC_APB4_RNG_BASE, mask));
 }
 
 rs_status_t rs_rng_interrupt_clear(uint32_t mask) {
-    return rs_rng_status(rng_interrupt_clear((uintptr_t)RS_SOC_APB_RNG_BASE, mask));
+    return rs_rng_status(rng_interrupt_clear((uintptr_t)RS_SOC_APB4_RNG_BASE, mask));
 }
 
 rs_status_t rs_rng_interrupt_test(uint32_t mask) {
-    return rs_rng_status(rng_interrupt_test((uintptr_t)RS_SOC_APB_RNG_BASE, mask));
+    return rs_rng_status(rng_interrupt_test((uintptr_t)RS_SOC_APB4_RNG_BASE, mask));
 }
 
 void rs_rng_shell_test(int argc, char **argv) {

crt/src/hal/rtc.c

@@ -28,37 +28,38 @@ static rs_status_t rs_rtc_status(rtc_status_t status) {
 }
 
 rs_status_t rs_rtc_probe(void) {
-    return rs_rtc_status(rtc_probe((uintptr_t)RS_SOC_APB_RTC_BASE));
+    return rs_rtc_status(rtc_probe((uintptr_t)RS_SOC_APB4_RTC_BASE));
 }
 
 rs_status_t rs_rtc_configure(const rs_rtc_config_t *config, rs_timeout_t timeout) {
-    return rs_rtc_status(rtc_configure((uintptr_t)RS_SOC_APB_RTC_BASE, config, timeout));
+    return rs_rtc_status(rtc_configure((uintptr_t)RS_SOC_APB4_RTC_BASE, config, timeout));
 }
 
 rs_status_t rs_rtc_set_time(const rs_rtc_time_t *time, rs_timeout_t timeout) {
-    return rs_rtc_status(rtc_set_time((uintptr_t)RS_SOC_APB_RTC_BASE, time, timeout));
+    return rs_rtc_status(rtc_set_time((uintptr_t)RS_SOC_APB4_RTC_BASE, time, timeout));
 }
 
 rs_status_t rs_rtc_get_time(rs_rtc_time_t *time, rs_timeout_t timeout) {
-    return rs_rtc_status(rtc_get_time((uintptr_t)RS_SOC_APB_RTC_BASE, time, timeout));
+    return rs_rtc_status(rtc_get_time((uintptr_t)RS_SOC_APB4_RTC_BASE, time, timeout));
 }
 
 rs_status_t rs_rtc_configure_alarm(uint32_t channel, const rs_rtc_alarm_t *alarm,
                                    rs_timeout_t timeout) {
     return rs_rtc_status(
-        rtc_configure_alarm((uintptr_t)RS_SOC_APB_RTC_BASE, channel, alarm, timeout));
+        rtc_configure_alarm((uintptr_t)RS_SOC_APB4_RTC_BASE, channel, alarm, timeout));
 }
 
 rs_status_t rs_rtc_configure_periodic(const rs_rtc_periodic_t *periodic, rs_timeout_t timeout) {
-    return rs_rtc_status(rtc_configure_periodic((uintptr_t)RS_SOC_APB_RTC_BASE, periodic, timeout));
+    return rs_rtc_status(
+        rtc_configure_periodic((uintptr_t)RS_SOC_APB4_RTC_BASE, periodic, timeout));
 }
 
 uint32_t rs_rtc_get_events(void) {
-    return rtc_get_events((uintptr_t)RS_SOC_APB_RTC_BASE);
+    return rtc_get_events((uintptr_t)RS_SOC_APB4_RTC_BASE);
 }
 
 rs_status_t rs_rtc_clear_events(uint32_t mask, rs_timeout_t timeout) {
-    return rs_rtc_status(rtc_clear_events((uintptr_t)RS_SOC_APB_RTC_BASE, mask, timeout));
+    return rs_rtc_status(rtc_clear_events((uintptr_t)RS_SOC_APB4_RTC_BASE, mask, timeout));
 }
 
 void rs_rtc_shell_test(int argc, char **argv) {

crt/src/hal/sysctrl.c

@@ -3,63 +3,63 @@
 #include <retrosoc/core/soc.h>
 #include <retrosoc/hal/sysctrl.h>
 
-#define RS_SYSCTRL_CORESEL_OFFSET            RS_SOC_SYSCTRL_CORESEL_OFFSET
-#define RS_SYSCTRL_IPSEL_OFFSET              RS_SOC_SYSCTRL_IPSEL_OFFSET
-#define RS_SYSCTRL_PLL_CFG_OFFSET            RS_SOC_SYSCTRL_PLL_CFG_OFFSET
-#define RS_SYSCTRL_PLL_CMD_OFFSET            RS_SOC_SYSCTRL_PLL_CMD_OFFSET
-#define RS_SYSCTRL_FAULT_STATUS_OFFSET       RS_SOC_SYSCTRL_FAULT_STATUS_OFFSET
-#define RS_SYSCTRL_FAULT_ADDR_OFFSET         RS_SOC_SYSCTRL_FAULT_ADDR_OFFSET
-#define RS_SYSCTRL_FAULT_COUNT_OFFSET        RS_SOC_SYSCTRL_FAULT_COUNT_OFFSET
-#define RS_SYSCTRL_PLL_STATUS_OFFSET         RS_SOC_SYSCTRL_PLL_STATUS_OFFSET
-#define RS_SYSCTRL_USER_CORE_RESET_OFFSET    RS_SOC_SYSCTRL_USER_CORE_RESET_OFFSET
-#define RS_SYSCTRL_USER_CORE_STATUS_OFFSET   RS_SOC_SYSCTRL_USER_CORE_STATUS_OFFSET
-#define RS_SYSCTRL_FAULT_MASTER_OFFSET       RS_SOC_SYSCTRL_FAULT_MASTER_OFFSET
-#define RS_SYSCTRL_FAULT_DETAIL_OFFSET       RS_SOC_SYSCTRL_FAULT_DETAIL_OFFSET
-#define RS_SYSCTRL_PERF_CTRL_OFFSET          RS_SOC_SYSCTRL_PERF_CTRL_OFFSET
-#define RS_SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET  RS_SOC_SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET
-#define RS_SYSCTRL_PERF_MGMT_WAIT_HI_OFFSET  RS_SOC_SYSCTRL_PERF_MGMT_WAIT_HI_OFFSET
-#define RS_SYSCTRL_PERF_USER_WAIT_LO_OFFSET  RS_SOC_SYSCTRL_PERF_USER_WAIT_LO_OFFSET
-#define RS_SYSCTRL_PERF_USER_WAIT_HI_OFFSET  RS_SOC_SYSCTRL_PERF_USER_WAIT_HI_OFFSET
-#define RS_SYSCTRL_PERF_DMA_WAIT_LO_OFFSET   RS_SOC_SYSCTRL_PERF_DMA_WAIT_LO_OFFSET
-#define RS_SYSCTRL_PERF_DMA_WAIT_HI_OFFSET   RS_SOC_SYSCTRL_PERF_DMA_WAIT_HI_OFFSET
-#define RS_SYSCTRL_PERF_APB4_WAIT_LO_OFFSET  RS_SOC_SYSCTRL_PERF_APB4_WAIT_LO_OFFSET
-#define RS_SYSCTRL_PERF_APB4_WAIT_HI_OFFSET  RS_SOC_SYSCTRL_PERF_APB4_WAIT_HI_OFFSET
-#define RS_SYSCTRL_PERF_APB_WAIT_LO_OFFSET   RS_SOC_SYSCTRL_PERF_APB_WAIT_LO_OFFSET
-#define RS_SYSCTRL_PERF_APB_WAIT_HI_OFFSET   RS_SOC_SYSCTRL_PERF_APB_WAIT_HI_OFFSET
-#define RS_SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET RS_SOC_SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET
-#define RS_SYSCTRL_PERF_SDRAM_WAIT_HI_OFFSET RS_SOC_SYSCTRL_PERF_SDRAM_WAIT_HI_OFFSET
-#define RS_SYSCTRL_PERF_PSRAM_WAIT_LO_OFFSET RS_SOC_SYSCTRL_PERF_PSRAM_WAIT_LO_OFFSET
-#define RS_SYSCTRL_PERF_PSRAM_WAIT_HI_OFFSET RS_SOC_SYSCTRL_PERF_PSRAM_WAIT_HI_OFFSET
-#define RS_SYSCTRL_PERF_FLASH_WAIT_LO_OFFSET RS_SOC_SYSCTRL_PERF_FLASH_WAIT_LO_OFFSET
-#define RS_SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET RS_SOC_SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET
-#define RS_SYSCTRL_TEST_STATUS_OFFSET        RS_SOC_SYSCTRL_TEST_STATUS_OFFSET
-#define RS_SYSCTRL_RTC_WAKE_STATUS_OFFSET    RS_SOC_SYSCTRL_RTC_WAKE_STATUS_OFFSET
+#define RS_SYSCTRL_CORESEL_OFFSET                  RS_SOC_SYSCTRL_CORESEL_OFFSET
+#define RS_SYSCTRL_IPSEL_OFFSET                    RS_SOC_SYSCTRL_IPSEL_OFFSET
+#define RS_SYSCTRL_PLL_CFG_OFFSET                  RS_SOC_SYSCTRL_PLL_CFG_OFFSET
+#define RS_SYSCTRL_PLL_CMD_OFFSET                  RS_SOC_SYSCTRL_PLL_CMD_OFFSET
+#define RS_SYSCTRL_FAULT_STATUS_OFFSET             RS_SOC_SYSCTRL_FAULT_STATUS_OFFSET
+#define RS_SYSCTRL_FAULT_ADDR_OFFSET               RS_SOC_SYSCTRL_FAULT_ADDR_OFFSET
+#define RS_SYSCTRL_FAULT_COUNT_OFFSET              RS_SOC_SYSCTRL_FAULT_COUNT_OFFSET
+#define RS_SYSCTRL_PLL_STATUS_OFFSET               RS_SOC_SYSCTRL_PLL_STATUS_OFFSET
+#define RS_SYSCTRL_USER_CORE_RESET_OFFSET          RS_SOC_SYSCTRL_USER_CORE_RESET_OFFSET
+#define RS_SYSCTRL_USER_CORE_STATUS_OFFSET         RS_SOC_SYSCTRL_USER_CORE_STATUS_OFFSET
+#define RS_SYSCTRL_FAULT_MASTER_OFFSET             RS_SOC_SYSCTRL_FAULT_MASTER_OFFSET
+#define RS_SYSCTRL_FAULT_DETAIL_OFFSET             RS_SOC_SYSCTRL_FAULT_DETAIL_OFFSET
+#define RS_SYSCTRL_PERF_CTRL_OFFSET                RS_SOC_SYSCTRL_PERF_CTRL_OFFSET
+#define RS_SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET        RS_SOC_SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET
+#define RS_SYSCTRL_PERF_MGMT_WAIT_HI_OFFSET        RS_SOC_SYSCTRL_PERF_MGMT_WAIT_HI_OFFSET
+#define RS_SYSCTRL_PERF_USER_WAIT_LO_OFFSET        RS_SOC_SYSCTRL_PERF_USER_WAIT_LO_OFFSET
+#define RS_SYSCTRL_PERF_USER_WAIT_HI_OFFSET        RS_SOC_SYSCTRL_PERF_USER_WAIT_HI_OFFSET
+#define RS_SYSCTRL_PERF_DMA_WAIT_LO_OFFSET         RS_SOC_SYSCTRL_PERF_DMA_WAIT_LO_OFFSET
+#define RS_SYSCTRL_PERF_DMA_WAIT_HI_OFFSET         RS_SOC_SYSCTRL_PERF_DMA_WAIT_HI_OFFSET
+#define RS_SYSCTRL_PERF_APB4_PERIPH_WAIT_LO_OFFSET RS_SOC_SYSCTRL_PERF_APB4_PERIPH_WAIT_LO_OFFSET
+#define RS_SYSCTRL_PERF_APB4_PERIPH_WAIT_HI_OFFSET RS_SOC_SYSCTRL_PERF_APB4_PERIPH_WAIT_HI_OFFSET
+#define RS_SYSCTRL_PERF_APB4_SYSTEM_WAIT_LO_OFFSET RS_SOC_SYSCTRL_PERF_APB4_SYSTEM_WAIT_LO_OFFSET
+#define RS_SYSCTRL_PERF_APB4_SYSTEM_WAIT_HI_OFFSET RS_SOC_SYSCTRL_PERF_APB4_SYSTEM_WAIT_HI_OFFSET
+#define RS_SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET       RS_SOC_SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET
+#define RS_SYSCTRL_PERF_SDRAM_WAIT_HI_OFFSET       RS_SOC_SYSCTRL_PERF_SDRAM_WAIT_HI_OFFSET
+#define RS_SYSCTRL_PERF_PSRAM_WAIT_LO_OFFSET       RS_SOC_SYSCTRL_PERF_PSRAM_WAIT_LO_OFFSET
+#define RS_SYSCTRL_PERF_PSRAM_WAIT_HI_OFFSET       RS_SOC_SYSCTRL_PERF_PSRAM_WAIT_HI_OFFSET
+#define RS_SYSCTRL_PERF_FLASH_WAIT_LO_OFFSET       RS_SOC_SYSCTRL_PERF_FLASH_WAIT_LO_OFFSET
+#define RS_SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET       RS_SOC_SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET
+#define RS_SYSCTRL_TEST_STATUS_OFFSET              RS_SOC_SYSCTRL_TEST_STATUS_OFFSET
+#define RS_SYSCTRL_RTC_WAKE_STATUS_OFFSET          RS_SOC_SYSCTRL_RTC_WAKE_STATUS_OFFSET
 
-#define RS_SYSCTRL_PLL_CMD_APPLY             UINT32_C(0x00000001)
-#define RS_SYSCTRL_PLL_CMD_CLEAR_ERROR       UINT32_C(0x00000002)
-#define RS_SYSCTRL_FAULT_PENDING             UINT32_C(0x00000001)
-#define RS_SYSCTRL_PERF_ENABLE               UINT32_C(0x00000001)
-#define RS_SYSCTRL_PERF_CLEAR                UINT32_C(0x00000002)
-#define RS_SYSCTRL_PERF_SNAPSHOT             UINT32_C(0x00000004)
-#define RS_SYSCTRL_PERF_CONTROL_MASK         UINT32_C(0x00000007)
-#define RS_SYSCTRL_TEST_STATUS_VALID         UINT32_C(0x80000000)
-#define RS_SYSCTRL_TEST_STATUS_PASS          UINT32_C(0x00000001)
-#define RS_SYSCTRL_TEST_STATUS_CODE_SHIFT    8U
-#define RS_SYSCTRL_USER_CORE_SEL_MASK        UINT32_C(0x0000001F)
-#define RS_SYSCTRL_USER_CORE_BUS_ENABLED     UINT32_C(0x00000100)
-#define RS_SYSCTRL_USER_CORE_BUS_IDLE        UINT32_C(0x00000200)
-#define RS_SYSCTRL_USER_CORE_DRAINING        UINT32_C(0x00000400)
-#define RS_SYSCTRL_USER_CORE_CONFIG_ERROR    UINT32_C(0x00000800)
-#define RS_SYSCTRL_PLL_SELECTION_MASK        UINT32_C(0x00000007)
-#define RS_SYSCTRL_PLL_ACTIVE_VALID          UINT32_C(0x00000008)
-#define RS_SYSCTRL_PLL_BUSY                  UINT32_C(0x00000010)
-#define RS_SYSCTRL_PLL_ERROR                 UINT32_C(0x00000020)
-#define RS_SYSCTRL_PLL_ERROR_SHIFT           6U
-#define RS_SYSCTRL_PLL_SAFE_CLOCK            UINT32_C(0x00000100)
-#define RS_SYSCTRL_PLL_LOCKED                UINT32_C(0x00000200)
-#define RS_SYSCTRL_PLL_CAPABLE               UINT32_C(0x00000400)
-#define RS_SYSCTRL_RTC_WAKE_LIVE             UINT32_C(0x00000001)
-#define RS_SYSCTRL_RTC_WAKE_SEEN             UINT32_C(0x00000002)
+#define RS_SYSCTRL_PLL_CMD_APPLY                   UINT32_C(0x00000001)
+#define RS_SYSCTRL_PLL_CMD_CLEAR_ERROR             UINT32_C(0x00000002)
+#define RS_SYSCTRL_FAULT_PENDING                   UINT32_C(0x00000001)
+#define RS_SYSCTRL_PERF_ENABLE                     UINT32_C(0x00000001)
+#define RS_SYSCTRL_PERF_CLEAR                      UINT32_C(0x00000002)
+#define RS_SYSCTRL_PERF_SNAPSHOT                   UINT32_C(0x00000004)
+#define RS_SYSCTRL_PERF_CONTROL_MASK               UINT32_C(0x00000007)
+#define RS_SYSCTRL_TEST_STATUS_VALID               UINT32_C(0x80000000)
+#define RS_SYSCTRL_TEST_STATUS_PASS                UINT32_C(0x00000001)
+#define RS_SYSCTRL_TEST_STATUS_CODE_SHIFT          8U
+#define RS_SYSCTRL_USER_CORE_SEL_MASK              UINT32_C(0x0000001F)
+#define RS_SYSCTRL_USER_CORE_BUS_ENABLED           UINT32_C(0x00000100)
+#define RS_SYSCTRL_USER_CORE_BUS_IDLE              UINT32_C(0x00000200)
+#define RS_SYSCTRL_USER_CORE_DRAINING              UINT32_C(0x00000400)
+#define RS_SYSCTRL_USER_CORE_CONFIG_ERROR          UINT32_C(0x00000800)
+#define RS_SYSCTRL_PLL_SELECTION_MASK              UINT32_C(0x00000007)
+#define RS_SYSCTRL_PLL_ACTIVE_VALID                UINT32_C(0x00000008)
+#define RS_SYSCTRL_PLL_BUSY                        UINT32_C(0x00000010)
+#define RS_SYSCTRL_PLL_ERROR                       UINT32_C(0x00000020)
+#define RS_SYSCTRL_PLL_ERROR_SHIFT                 6U
+#define RS_SYSCTRL_PLL_SAFE_CLOCK                  UINT32_C(0x00000100)
+#define RS_SYSCTRL_PLL_LOCKED                      UINT32_C(0x00000200)
+#define RS_SYSCTRL_PLL_CAPABLE                     UINT32_C(0x00000400)
+#define RS_SYSCTRL_RTC_WAKE_LIVE                   UINT32_C(0x00000001)
+#define RS_SYSCTRL_RTC_WAKE_SEEN                   UINT32_C(0x00000002)
 
 static volatile uint32_t *rs_sysctrl_register(uint32_t offset) {
     return (volatile uint32_t *)(RS_SOC_APB4_SYSCTRL_BASE + (uintptr_t)offset);
@@ -84,13 +84,13 @@ static rs_status_t rs_sysctrl_perf_offsets(rs_sysctrl_perf_counter_t counter, ui
         *low_offset = RS_SYSCTRL_PERF_DMA_WAIT_LO_OFFSET;
         *high_offset = RS_SYSCTRL_PERF_DMA_WAIT_HI_OFFSET;
         break;
-    case RS_SYSCTRL_PERF_APB4_WAIT:
-        *low_offset = RS_SYSCTRL_PERF_APB4_WAIT_LO_OFFSET;
-        *high_offset = RS_SYSCTRL_PERF_APB4_WAIT_HI_OFFSET;
+    case RS_SYSCTRL_PERF_APB4_PERIPH_WAIT:
+        *low_offset = RS_SYSCTRL_PERF_APB4_PERIPH_WAIT_LO_OFFSET;
+        *high_offset = RS_SYSCTRL_PERF_APB4_PERIPH_WAIT_HI_OFFSET;
         break;
-    case RS_SYSCTRL_PERF_APB_WAIT:
-        *low_offset = RS_SYSCTRL_PERF_APB_WAIT_LO_OFFSET;
-        *high_offset = RS_SYSCTRL_PERF_APB_WAIT_HI_OFFSET;
+    case RS_SYSCTRL_PERF_APB4_SYSTEM_WAIT:
+        *low_offset = RS_SYSCTRL_PERF_APB4_SYSTEM_WAIT_LO_OFFSET;
+        *high_offset = RS_SYSCTRL_PERF_APB4_SYSTEM_WAIT_HI_OFFSET;
         break;
     case RS_SYSCTRL_PERF_SDRAM_WAIT:
         *low_offset = RS_SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET;

crt/src/hal/watchdog.c

@@ -24,20 +24,20 @@ void ip_wdg_test(int argc, char **argv) {
     (void)argv;
 
     printf("[APB IP] wdg V2 test\n");
-    status = wdg_configure((uintptr_t)RS_SOC_APB_WDG_BASE, &config);
+    status = wdg_configure((uintptr_t)RS_SOC_APB4_WDG_BASE, &config);
     if (status != WDG_STATUS_OK) {
         printf("watchdog configure failed: %d\n", (int)status);
         return;
     }
-    status = wdg_interrupt_test((uintptr_t)RS_SOC_APB_WDG_BASE, WDG_INTR_WARNING_MASK);
+    status = wdg_interrupt_test((uintptr_t)RS_SOC_APB4_WDG_BASE, WDG_INTR_WARNING_MASK);
     if (status == WDG_STATUS_OK) {
-        status = wdg_snapshot((uintptr_t)RS_SOC_APB_WDG_BASE, &snapshot, RS_WDG_COMMAND_TIMEOUT);
+        status = wdg_snapshot((uintptr_t)RS_SOC_APB4_WDG_BASE, &snapshot, RS_WDG_COMMAND_TIMEOUT);
     }
     if ((status != WDG_STATUS_OK) || ((snapshot.interrupt_state & WDG_INTR_WARNING_MASK) == 0U)) {
         printf("watchdog interrupt self-test failed: %d\n", (int)status);
         return;
     }
-    status = wdg_interrupt_clear((uintptr_t)RS_SOC_APB_WDG_BASE, WDG_INTR_WARNING_MASK);
+    status = wdg_interrupt_clear((uintptr_t)RS_SOC_APB4_WDG_BASE, WDG_INTR_WARNING_MASK);
     if (status != WDG_STATUS_OK) {
         printf("watchdog interrupt clear failed: %d\n", (int)status);
         return;

crt/src/service/booter.c

@@ -129,19 +129,19 @@ void rs_app_info(void) {
     printf("                       1 x I2C1          @%p\n",
            (void *)(uintptr_t)RS_SOC_APB4_I2C1_BASE);
     printf("                       1 x ARCHINFO      @%p\n",
-           (void *)(uintptr_t)RS_SOC_APB_ARCHINFO_BASE);
+           (void *)(uintptr_t)RS_SOC_APB4_ARCHINFO_BASE);
     printf("                       1 x RNG           @%p\n",
-           (void *)(uintptr_t)RS_SOC_APB_RNG_BASE);
+           (void *)(uintptr_t)RS_SOC_APB4_RNG_BASE);
     printf("                       1 x PWM V2(4CH)   @%p\n",
-           (void *)(uintptr_t)RS_SOC_APB_PWM_BASE);
+           (void *)(uintptr_t)RS_SOC_APB4_PWM_BASE);
     printf("                       1 x PS2           @%p\n",
-           (void *)(uintptr_t)RS_SOC_APB_PS2_BASE);
+           (void *)(uintptr_t)RS_SOC_APB4_PS2_BASE);
     printf("                       1 x RTC           @%p\n",
-           (void *)(uintptr_t)RS_SOC_APB_RTC_BASE);
+           (void *)(uintptr_t)RS_SOC_APB4_RTC_BASE);
     printf("                       1 x WDG V2        @%p\n",
-           (void *)(uintptr_t)RS_SOC_APB_WDG_BASE);
+           (void *)(uintptr_t)RS_SOC_APB4_WDG_BASE);
     printf("                       1 x CRC           @%p\n",
-           (void *)(uintptr_t)RS_SOC_APB_CRC_BASE);
+           (void *)(uintptr_t)RS_SOC_APB4_CRC_BASE);
     printf("                       1 x USER_IP(4KiB) @%p\n", (void *)&reg_user_ip_reg0);
     printf("\n");
     printf("#############################################################\n");

docs/ip/ps2.md

@@ -1,7 +1,7 @@
 # PS/2 SoC Integration
 
 The Mini SoC integrates the managed PS/2 host controller at
-`RS_SOC_APB_PS2_BASE`. The standalone IP owns the transport RTL, register ABI,
+`RS_SOC_APB4_PS2_BASE`. The standalone IP owns the transport RTL, register ABI,
 device model, freestanding controller/keyboard/mouse software, formal proof,
 and release documentation under `rtl/managed/clusterip/ps2`.
 

docs/mini-soc-block-diagram.dot

@@ -138,11 +138,11 @@ digraph mini_soc_block_diagram {
         fillcolor="#FFF3C9",
         label="On-chip SRAM\noptional pipelined AXI42RAM path"
       ];
-      apb4_adapter [
+      apb4_periph [
         fillcolor="#E5E7EB",
         label="AXI42APB\nAPB4 configuration plane"
       ];
-      apb_adapter [
+      apb4_system [
         fillcolor="#E5E7EB",
         label="AXI42APB\ndirect APB bridge"
       ];
@@ -154,7 +154,7 @@ digraph mini_soc_block_diagram {
         fillcolor="#F9E1E7",
         label="CLINT\nstandard 64 KiB register map\nmtime, mtimecmp and MSIP"
       ];
-      apb4_targets [
+      apb4_periph_targets [
         fillcolor="#F9E1E7",
         label="APB4 configuration targets\nXPI, SDRAM, PSRAM, SPI-SD, DVP and I2S\nSDRAM config is a dedicated top-level port"
       ];
@@ -186,7 +186,7 @@ digraph mini_soc_block_diagram {
         fillcolor="#F9E1E7",
         label="WS2812 TX\n24-bit MSB-first serializer\n16-word FIFO, IRQ17, DMA-fed"
       ];
-      apb_targets [
+      apb4_system_targets [
         fillcolor="#E6F4EA",
         label="APB target wrapper\nUser IP target"
       ];
@@ -232,8 +232,8 @@ digraph mini_soc_block_diagram {
   { rank=same; jtag_dtm; debug_module; mgmt_core; }
   { rank=same; user_core; dma; }
   { rank=same; fault; fabric; sram; }
-  { rank=same; apb4_adapter; apb_adapter; }
-  { rank=same; sysctrl; clint; apb4_targets; memory_targets; stream_io; uart0; i2c_controllers; gpio_controller; timers; ws2812; archinfo; rng; ps2; rtc; wdg; crc; pwm; apb_targets; }
+  { rank=same; apb4_periph; apb4_system; }
+  { rank=same; sysctrl; clint; apb4_periph_targets; memory_targets; stream_io; uart0; i2c_controllers; gpio_controller; timers; ws2812; archinfo; rng; ps2; rtc; wdg; crc; pwm; apb4_system_targets; }
   { rank=same; gpio_bridge; irq; }
 
   ext_clock -> rcu [label="clock / reset"];
@@ -255,26 +255,26 @@ digraph mini_soc_block_diagram {
   fabric -> fault [label="invalid / denied", dir=both];
   fabric -> sram [label="AXI4"];
   fabric -> memory_targets [label="AXI4 data"];
-  fabric -> apb4_adapter [label="AXI4 config"];
-  fabric -> apb_adapter [label="AXI4"];
-  apb4_adapter -> sysctrl [label="APB4"];
-  apb4_adapter -> clint [label="APB4"];
-  apb4_adapter -> apb4_targets [label="APB4"];
-  apb4_adapter -> uart0 [label="APB4"];
-  apb4_adapter -> i2c_controllers [label="APB4"];
-  apb4_adapter -> gpio_controller [label="APB4\nuser/admin"];
-  apb4_adapter -> timers [label="APB4"];
-  apb4_adapter -> ws2812 [label="APB4"];
-  apb_adapter -> archinfo [label="APB"];
-  apb_adapter -> rng [label="APB"];
-  apb_adapter -> ps2 [label="APB"];
-  apb_adapter -> rtc [label="APB"];
-  apb_adapter -> wdg [label="APB"];
-  apb_adapter -> crc [label="APB"];
-  apb_adapter -> pwm [label="APB"];
-  apb_adapter -> apb_targets [label="APB"];
+  fabric -> apb4_periph [label="AXI4 config"];
+  fabric -> apb4_system [label="AXI4"];
+  apb4_periph -> sysctrl [label="APB4"];
+  apb4_periph -> clint [label="APB4"];
+  apb4_periph -> apb4_periph_targets [label="APB4"];
+  apb4_periph -> uart0 [label="APB4"];
+  apb4_periph -> i2c_controllers [label="APB4"];
+  apb4_periph -> gpio_controller [label="APB4\nuser/admin"];
+  apb4_periph -> timers [label="APB4"];
+  apb4_periph -> ws2812 [label="APB4"];
+  apb4_system -> archinfo [label="APB4"];
+  apb4_system -> rng [label="APB4"];
+  apb4_system -> ps2 [label="APB4"];
+  apb4_system -> rtc [label="APB4"];
+  apb4_system -> wdg [label="APB4"];
+  apb4_system -> crc [label="APB4"];
+  apb4_system -> pwm [label="APB4"];
+  apb4_system -> apb4_system_targets [label="APB4"];
 
-  apb4_targets -> gpio_controller [label="alternate functions"];
+  apb4_periph_targets -> gpio_controller [label="alternate functions"];
   gpio_controller -> gpio_bridge [label="pad control"];
   gpio_controller -> irq [label="IRQ18"];
   timers -> irq [label="IRQ3 / IRQ4"];
@@ -299,9 +299,9 @@ digraph mini_soc_block_diagram {
   rcu -> wdg [label="independent 18.432 MHz clock", style=dashed];
   wdg -> irq [label="early warning IRQ14"];
   wdg -> rcu [label="system reset request", color="#B91C1C", penwidth=2];
-  apb_targets -> gpio_controller [label="user_gpio"];
-  apb4_targets -> memory_targets [label="APB4 configuration", style=dashed];
-  apb4_targets -> stream_io [label="APB4 configuration", style=dashed];
+  apb4_system_targets -> gpio_controller [label="user_gpio"];
+  apb4_periph_targets -> memory_targets [label="APB4 configuration", style=dashed];
+  apb4_periph_targets -> stream_io [label="APB4 configuration", style=dashed];
   memory_targets -> ext_io [dir=both, label="device interfaces"];
   stream_io -> ext_io [dir=both, label="I2S / DVP signals"];
   uart0 -> ext_io [dir=both, label="UART pads"];

docs/mini-soc-block-diagram.svg

@@ -11,8 +11,8 @@
 <text text-anchor="middle" x="132" y="-948.08" font-family="Arial" font-size="18.00">retroSoC Mini SoC Architecture</text>
 <g id="clust1" class="cluster">
 <title>cluster_rtl_ownership</title>
-<path fill="transparent" stroke="#cbd5e1" stroke-dasharray="5,2" d="M3179,-832.48C3179,-832.48 3834,-832.48 3834,-832.48 3840,-832.48 3846,-838.48 3846,-844.48 3846,-844.48 3846,-918.48 3846,-918.48 3846,-924.48 3840,-930.48 3834,-930.48 3834,-930.48 3179,-930.48 3179,-930.48 3173,-930.48 3167,-924.48 3167,-918.48 3167,-918.48 3167,-844.48 3167,-844.48 3167,-838.48 3173,-832.48 3179,-832.48"/>
-<text text-anchor="middle" x="3256.5" y="-918.48" font-family="Arial" font-size="10.00" fill="#334155">RTL ownership and validation profiles</text>
+<path fill="transparent" stroke="#cbd5e1" stroke-dasharray="5,2" d="M3194,-832.48C3194,-832.48 3849,-832.48 3849,-832.48 3855,-832.48 3861,-838.48 3861,-844.48 3861,-844.48 3861,-918.48 3861,-918.48 3861,-924.48 3855,-930.48 3849,-930.48 3849,-930.48 3194,-930.48 3194,-930.48 3188,-930.48 3182,-924.48 3182,-918.48 3182,-918.48 3182,-844.48 3182,-844.48 3182,-838.48 3188,-832.48 3194,-832.48"/>
+<text text-anchor="middle" x="3271.5" y="-918.48" font-family="Arial" font-size="10.00" fill="#334155">RTL ownership and validation profiles</text>
 </g>
 <g id="clust2" class="cluster">
 <title>cluster_asic</title>
@@ -57,66 +57,66 @@
 <!-- ext_jtag -->
 <g id="node3" class="node">
 <title>ext_jtag</title>
-<path fill="#f3f4f6" stroke="#4b5563" stroke-width="1.1" d="M2389.5,-880.48C2389.5,-880.48 2258.5,-880.48 2258.5,-880.48 2252.5,-880.48 2246.5,-874.48 2246.5,-868.48 2246.5,-868.48 2246.5,-856.48 2246.5,-856.48 2246.5,-850.48 2252.5,-844.48 2258.5,-844.48 2258.5,-844.48 2389.5,-844.48 2389.5,-844.48 2395.5,-844.48 2401.5,-850.48 2401.5,-856.48 2401.5,-856.48 2401.5,-868.48 2401.5,-868.48 2401.5,-874.48 2395.5,-880.48 2389.5,-880.48"/>
-<text text-anchor="middle" x="2324" y="-865.48" font-family="Arial" font-size="10.00" fill="#111827">Management JTAG</text>
-<text text-anchor="middle" x="2324" y="-854.48" font-family="Arial" font-size="10.00" fill="#111827">TCK, TMS, TDI, TRST_n, TDO</text>
+<path fill="#f3f4f6" stroke="#4b5563" stroke-width="1.1" d="M2419.5,-880.48C2419.5,-880.48 2288.5,-880.48 2288.5,-880.48 2282.5,-880.48 2276.5,-874.48 2276.5,-868.48 2276.5,-868.48 2276.5,-856.48 2276.5,-856.48 2276.5,-850.48 2282.5,-844.48 2288.5,-844.48 2288.5,-844.48 2419.5,-844.48 2419.5,-844.48 2425.5,-844.48 2431.5,-850.48 2431.5,-856.48 2431.5,-856.48 2431.5,-868.48 2431.5,-868.48 2431.5,-874.48 2425.5,-880.48 2419.5,-880.48"/>
+<text text-anchor="middle" x="2354" y="-865.48" font-family="Arial" font-size="10.00" fill="#111827">Management JTAG</text>
+<text text-anchor="middle" x="2354" y="-854.48" font-family="Arial" font-size="10.00" fill="#111827">TCK, TMS, TDI, TRST_n, TDO</text>
 </g>
 <!-- jtag_dtm -->
 <g id="node10" class="node">
 <title>jtag_dtm</title>
-<path fill="#e5e7eb" stroke="#4b5563" stroke-width="1.1" d="M2399,-698.98C2399,-698.98 2249,-698.98 2249,-698.98 2243,-698.98 2237,-692.98 2237,-686.98 2237,-686.98 2237,-674.98 2237,-674.98 2237,-668.98 2243,-662.98 2249,-662.98 2249,-662.98 2399,-662.98 2399,-662.98 2405,-662.98 2411,-668.98 2411,-674.98 2411,-674.98 2411,-686.98 2411,-686.98 2411,-692.98 2405,-698.98 2399,-698.98"/>
-<text text-anchor="middle" x="2324" y="-683.98" font-family="Arial" font-size="10.00" fill="#111827">Hazard3 JTAG DTM</text>
-<text text-anchor="middle" x="2324" y="-672.98" font-family="Arial" font-size="10.00" fill="#111827">10 MHz asynchronous TCK domain</text>
+<path fill="#e5e7eb" stroke="#4b5563" stroke-width="1.1" d="M2429,-698.98C2429,-698.98 2279,-698.98 2279,-698.98 2273,-698.98 2267,-692.98 2267,-686.98 2267,-686.98 2267,-674.98 2267,-674.98 2267,-668.98 2273,-662.98 2279,-662.98 2279,-662.98 2429,-662.98 2429,-662.98 2435,-662.98 2441,-668.98 2441,-674.98 2441,-674.98 2441,-686.98 2441,-686.98 2441,-692.98 2435,-698.98 2429,-698.98"/>
+<text text-anchor="middle" x="2354" y="-683.98" font-family="Arial" font-size="10.00" fill="#111827">Hazard3 JTAG DTM</text>
+<text text-anchor="middle" x="2354" y="-672.98" font-family="Arial" font-size="10.00" fill="#111827">10 MHz asynchronous TCK domain</text>
 </g>
 <!-- ext_jtag&#45;&gt;jtag_dtm -->
 <g id="edge2" class="edge">
 <title>ext_jtag&#45;&gt;jtag_dtm</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2324,-844.27C2324,-812.24 2324,-743.39 2324,-706.51"/>
-<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2326.45,-706.14 2324,-699.14 2321.55,-706.14 2326.45,-706.14"/>
-<text text-anchor="middle" x="2344" y="-815.08" font-family="Arial" font-size="8.00" fill="#374151">JTAG pads</text>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2354,-844.27C2354,-812.24 2354,-743.39 2354,-706.51"/>
+<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2356.45,-706.14 2354,-699.14 2351.55,-706.14 2356.45,-706.14"/>
+<text text-anchor="middle" x="2374" y="-815.08" font-family="Arial" font-size="8.00" fill="#374151">JTAG pads</text>
 </g>
 <!-- rtl_owned -->
 <g id="node4" class="node">
 <title>rtl_owned</title>
-<path fill="#dcecf8" stroke="#4b5563" stroke-width="1.1" d="M3822,-880.48C3822,-880.48 3710,-880.48 3710,-880.48 3704,-880.48 3698,-874.48 3698,-868.48 3698,-868.48 3698,-856.48 3698,-856.48 3698,-850.48 3704,-844.48 3710,-844.48 3710,-844.48 3822,-844.48 3822,-844.48 3828,-844.48 3834,-850.48 3834,-856.48 3834,-856.48 3834,-868.48 3834,-868.48 3834,-874.48 3828,-880.48 3822,-880.48"/>
-<text text-anchor="middle" x="3766" y="-865.48" font-family="Arial" font-size="10.00" fill="#111827">Self&#45;owned RTL</text>
-<text text-anchor="middle" x="3766" y="-854.48" font-family="Arial" font-size="10.00" fill="#111827">Verible format + strict style</text>
+<path fill="#dcecf8" stroke="#4b5563" stroke-width="1.1" d="M3837,-880.48C3837,-880.48 3725,-880.48 3725,-880.48 3719,-880.48 3713,-874.48 3713,-868.48 3713,-868.48 3713,-856.48 3713,-856.48 3713,-850.48 3719,-844.48 3725,-844.48 3725,-844.48 3837,-844.48 3837,-844.48 3843,-844.48 3849,-850.48 3849,-856.48 3849,-856.48 3849,-868.48 3849,-868.48 3849,-874.48 3843,-880.48 3837,-880.48"/>
+<text text-anchor="middle" x="3781" y="-865.48" font-family="Arial" font-size="10.00" fill="#111827">Self&#45;owned RTL</text>
+<text text-anchor="middle" x="3781" y="-854.48" font-family="Arial" font-size="10.00" fill="#111827">Verible format + strict style</text>
 </g>
 <!-- rtl_verif -->
 <g id="node5" class="node">
 <title>rtl_verif</title>
-<path fill="#fce7f3" stroke="#4b5563" stroke-width="1.1" d="M3658.5,-880.48C3658.5,-880.48 3571.5,-880.48 3571.5,-880.48 3565.5,-880.48 3559.5,-874.48 3559.5,-868.48 3559.5,-868.48 3559.5,-856.48 3559.5,-856.48 3559.5,-850.48 3565.5,-844.48 3571.5,-844.48 3571.5,-844.48 3658.5,-844.48 3658.5,-844.48 3664.5,-844.48 3670.5,-850.48 3670.5,-856.48 3670.5,-856.48 3670.5,-868.48 3670.5,-868.48 3670.5,-874.48 3664.5,-880.48 3658.5,-880.48"/>
-<text text-anchor="middle" x="3615" y="-865.48" font-family="Arial" font-size="10.00" fill="#111827">Formal and DV RTL</text>
-<text text-anchor="middle" x="3615" y="-854.48" font-family="Arial" font-size="10.00" fill="#111827">verification lint profile</text>
+<path fill="#fce7f3" stroke="#4b5563" stroke-width="1.1" d="M3673.5,-880.48C3673.5,-880.48 3586.5,-880.48 3586.5,-880.48 3580.5,-880.48 3574.5,-874.48 3574.5,-868.48 3574.5,-868.48 3574.5,-856.48 3574.5,-856.48 3574.5,-850.48 3580.5,-844.48 3586.5,-844.48 3586.5,-844.48 3673.5,-844.48 3673.5,-844.48 3679.5,-844.48 3685.5,-850.48 3685.5,-856.48 3685.5,-856.48 3685.5,-868.48 3685.5,-868.48 3685.5,-874.48 3679.5,-880.48 3673.5,-880.48"/>
+<text text-anchor="middle" x="3630" y="-865.48" font-family="Arial" font-size="10.00" fill="#111827">Formal and DV RTL</text>
+<text text-anchor="middle" x="3630" y="-854.48" font-family="Arial" font-size="10.00" fill="#111827">verification lint profile</text>
 </g>
 <!-- rtl_tech -->
 <g id="node6" class="node">
 <title>rtl_tech</title>
-<path fill="#fff3c9" stroke="#4b5563" stroke-width="1.1" d="M3520.5,-880.48C3520.5,-880.48 3393.5,-880.48 3393.5,-880.48 3387.5,-880.48 3381.5,-874.48 3381.5,-868.48 3381.5,-868.48 3381.5,-856.48 3381.5,-856.48 3381.5,-850.48 3387.5,-844.48 3393.5,-844.48 3393.5,-844.48 3520.5,-844.48 3520.5,-844.48 3526.5,-844.48 3532.5,-850.48 3532.5,-856.48 3532.5,-856.48 3532.5,-868.48 3532.5,-868.48 3532.5,-874.48 3526.5,-880.48 3520.5,-880.48"/>
-<text text-anchor="middle" x="3457" y="-865.48" font-family="Arial" font-size="10.00" fill="#111827">PDK and technology wrappers</text>
-<text text-anchor="middle" x="3457" y="-854.48" font-family="Arial" font-size="10.00" fill="#111827">compile/elaboration profile</text>
+<path fill="#fff3c9" stroke="#4b5563" stroke-width="1.1" d="M3535.5,-880.48C3535.5,-880.48 3408.5,-880.48 3408.5,-880.48 3402.5,-880.48 3396.5,-874.48 3396.5,-868.48 3396.5,-868.48 3396.5,-856.48 3396.5,-856.48 3396.5,-850.48 3402.5,-844.48 3408.5,-844.48 3408.5,-844.48 3535.5,-844.48 3535.5,-844.48 3541.5,-844.48 3547.5,-850.48 3547.5,-856.48 3547.5,-856.48 3547.5,-868.48 3547.5,-868.48 3547.5,-874.48 3541.5,-880.48 3535.5,-880.48"/>
+<text text-anchor="middle" x="3472" y="-865.48" font-family="Arial" font-size="10.00" fill="#111827">PDK and technology wrappers</text>
+<text text-anchor="middle" x="3472" y="-854.48" font-family="Arial" font-size="10.00" fill="#111827">compile/elaboration profile</text>
 </g>
 <!-- rtl_generated -->
 <g id="node7" class="node">
 <title>rtl_generated</title>
-<path fill="#e5e7eb" stroke="#4b5563" stroke-width="1.1" d="M3342.5,-880.48C3342.5,-880.48 3191.5,-880.48 3191.5,-880.48 3185.5,-880.48 3179.5,-874.48 3179.5,-868.48 3179.5,-868.48 3179.5,-856.48 3179.5,-856.48 3179.5,-850.48 3185.5,-844.48 3191.5,-844.48 3191.5,-844.48 3342.5,-844.48 3342.5,-844.48 3348.5,-844.48 3354.5,-850.48 3354.5,-856.48 3354.5,-856.48 3354.5,-868.48 3354.5,-868.48 3354.5,-874.48 3348.5,-880.48 3342.5,-880.48"/>
-<text text-anchor="middle" x="3267" y="-865.48" font-family="Arial" font-size="10.00" fill="#111827">Generated and managed RTL</text>
-<text text-anchor="middle" x="3267" y="-854.48" font-family="Arial" font-size="10.00" fill="#111827">locked source and regeneration flow</text>
+<path fill="#e5e7eb" stroke="#4b5563" stroke-width="1.1" d="M3357.5,-880.48C3357.5,-880.48 3206.5,-880.48 3206.5,-880.48 3200.5,-880.48 3194.5,-874.48 3194.5,-868.48 3194.5,-868.48 3194.5,-856.48 3194.5,-856.48 3194.5,-850.48 3200.5,-844.48 3206.5,-844.48 3206.5,-844.48 3357.5,-844.48 3357.5,-844.48 3363.5,-844.48 3369.5,-850.48 3369.5,-856.48 3369.5,-856.48 3369.5,-868.48 3369.5,-868.48 3369.5,-874.48 3363.5,-880.48 3357.5,-880.48"/>
+<text text-anchor="middle" x="3282" y="-865.48" font-family="Arial" font-size="10.00" fill="#111827">Generated and managed RTL</text>
+<text text-anchor="middle" x="3282" y="-854.48" font-family="Arial" font-size="10.00" fill="#111827">locked source and regeneration flow</text>
 </g>
 <!-- fabric -->
 <g id="node15" class="node">
 <title>fabric</title>
-<path fill="#dcecf8" stroke="#4b5563" stroke-width="1.1" d="M2940.75,-470.69C2940.75,-470.69 2857.37,-499.78 2857.37,-499.78 2851.7,-501.75 2840.04,-503.73 2834.04,-503.73 2834.04,-503.73 2645.96,-503.73 2645.96,-503.73 2639.96,-503.73 2628.3,-501.75 2622.63,-499.78 2622.63,-499.78 2539.25,-470.69 2539.25,-470.69 2533.59,-468.72 2533.59,-464.77 2539.25,-462.79 2539.25,-462.79 2622.63,-433.71 2622.63,-433.71 2628.3,-431.73 2639.96,-429.76 2645.96,-429.76 2645.96,-429.76 2834.04,-429.76 2834.04,-429.76 2840.04,-429.76 2851.7,-431.73 2857.37,-433.71 2857.37,-433.71 2940.75,-462.79 2940.75,-462.79 2946.41,-464.77 2946.41,-468.72 2940.75,-470.69"/>
-<text text-anchor="middle" x="2740" y="-475.24" font-family="Arial" font-size="10.00" fill="#111827">AXI4 fabric</text>
-<text text-anchor="middle" x="2740" y="-464.24" font-family="Arial" font-size="10.00" fill="#111827">3 masters / 9 targets, per&#45;target round robin</text>
-<text text-anchor="middle" x="2740" y="-453.24" font-family="Arial" font-size="10.00" fill="#111827">FIXED/INCR/WRAP1&#45;16, access policy, fault reporting</text>
+<path fill="#dcecf8" stroke="#4b5563" stroke-width="1.1" d="M2970.75,-470.69C2970.75,-470.69 2887.37,-499.78 2887.37,-499.78 2881.7,-501.75 2870.04,-503.73 2864.04,-503.73 2864.04,-503.73 2675.96,-503.73 2675.96,-503.73 2669.96,-503.73 2658.3,-501.75 2652.63,-499.78 2652.63,-499.78 2569.25,-470.69 2569.25,-470.69 2563.59,-468.72 2563.59,-464.77 2569.25,-462.79 2569.25,-462.79 2652.63,-433.71 2652.63,-433.71 2658.3,-431.73 2669.96,-429.76 2675.96,-429.76 2675.96,-429.76 2864.04,-429.76 2864.04,-429.76 2870.04,-429.76 2881.7,-431.73 2887.37,-433.71 2887.37,-433.71 2970.75,-462.79 2970.75,-462.79 2976.41,-464.77 2976.41,-468.72 2970.75,-470.69"/>
+<text text-anchor="middle" x="2770" y="-475.24" font-family="Arial" font-size="10.00" fill="#111827">AXI4 fabric</text>
+<text text-anchor="middle" x="2770" y="-464.24" font-family="Arial" font-size="10.00" fill="#111827">3 masters / 9 targets, per&#45;target round robin</text>
+<text text-anchor="middle" x="2770" y="-453.24" font-family="Arial" font-size="10.00" fill="#111827">FIXED/INCR/WRAP1&#45;16, access policy, fault reporting</text>
 </g>
 <!-- rcu&#45;&gt;fabric -->
 <g id="edge3" class="edge">
 <title>rcu&#45;&gt;fabric</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M362.03,-560.47C368.2,-559.24 372,-558.48 372,-558.48 372,-558.48 1976.81,-496.99 2544.18,-475.25"/>
-<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2544.31,-477.69 2551.21,-474.98 2544.13,-472.8 2544.31,-477.69"/>
-<text text-anchor="middle" x="1240" y="-529.08" font-family="Arial" font-size="8.00" fill="#374151">system clock / reset</text>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M362.03,-560.47C368.2,-559.24 372,-558.48 372,-558.48 372,-558.48 2001.46,-496.82 2573.98,-475.16"/>
+<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2574.18,-477.6 2581.08,-474.89 2573.99,-472.71 2574.18,-477.6"/>
+<text text-anchor="middle" x="1251" y="-529.08" font-family="Arial" font-size="8.00" fill="#374151">system clock / reset</text>
 </g>
 <!-- clint -->
 <g id="node21" class="node">
@@ -166,53 +166,53 @@
 <!-- mgmt_core -->
 <g id="node9" class="node">
 <title>mgmt_core</title>
-<path fill="#ddf2e3" stroke="#4b5563" stroke-width="1.1" d="M2984,-703.48C2984,-703.48 2830,-703.48 2830,-703.48 2824,-703.48 2818,-697.48 2818,-691.48 2818,-691.48 2818,-670.48 2818,-670.48 2818,-664.48 2824,-658.48 2830,-658.48 2830,-658.48 2984,-658.48 2984,-658.48 2990,-658.48 2996,-664.48 2996,-670.48 2996,-670.48 2996,-691.48 2996,-691.48 2996,-697.48 2990,-703.48 2984,-703.48"/>
-<text text-anchor="middle" x="2907" y="-689.48" font-family="Arial" font-size="10.00" fill="#111827">Management core</text>
-<text text-anchor="middle" x="2907" y="-678.48" font-family="Arial" font-size="10.00" fill="#111827">Fixed Hazard3, branch predictor</text>
-<text text-anchor="middle" x="2907" y="-667.48" font-family="Arial" font-size="10.00" fill="#111827">JTAG Debug Module always present</text>
+<path fill="#ddf2e3" stroke="#4b5563" stroke-width="1.1" d="M3014,-703.48C3014,-703.48 2860,-703.48 2860,-703.48 2854,-703.48 2848,-697.48 2848,-691.48 2848,-691.48 2848,-670.48 2848,-670.48 2848,-664.48 2854,-658.48 2860,-658.48 2860,-658.48 3014,-658.48 3014,-658.48 3020,-658.48 3026,-664.48 3026,-670.48 3026,-670.48 3026,-691.48 3026,-691.48 3026,-697.48 3020,-703.48 3014,-703.48"/>
+<text text-anchor="middle" x="2937" y="-689.48" font-family="Arial" font-size="10.00" fill="#111827">Management core</text>
+<text text-anchor="middle" x="2937" y="-678.48" font-family="Arial" font-size="10.00" fill="#111827">Fixed Hazard3, branch predictor</text>
+<text text-anchor="middle" x="2937" y="-667.48" font-family="Arial" font-size="10.00" fill="#111827">JTAG Debug Module always present</text>
 </g>
 <!-- mgmt_adapter -->
 <g id="node12" class="node">
 <title>mgmt_adapter</title>
-<path fill="#e5e7eb" stroke="#4b5563" stroke-width="1.1" d="M2945.5,-598.98C2945.5,-598.98 2868.5,-598.98 2868.5,-598.98 2862.5,-598.98 2856.5,-592.98 2856.5,-586.98 2856.5,-586.98 2856.5,-574.98 2856.5,-574.98 2856.5,-568.98 2862.5,-562.98 2868.5,-562.98 2868.5,-562.98 2945.5,-562.98 2945.5,-562.98 2951.5,-562.98 2957.5,-568.98 2957.5,-574.98 2957.5,-574.98 2957.5,-586.98 2957.5,-586.98 2957.5,-592.98 2951.5,-598.98 2945.5,-598.98"/>
-<text text-anchor="middle" x="2907" y="-583.98" font-family="Arial" font-size="10.00" fill="#111827">AHB&#45;Lite2AXI4</text>
-<text text-anchor="middle" x="2907" y="-572.98" font-family="Arial" font-size="10.00" fill="#111827">single&#45;beat adapter</text>
+<path fill="#e5e7eb" stroke="#4b5563" stroke-width="1.1" d="M2975.5,-598.98C2975.5,-598.98 2898.5,-598.98 2898.5,-598.98 2892.5,-598.98 2886.5,-592.98 2886.5,-586.98 2886.5,-586.98 2886.5,-574.98 2886.5,-574.98 2886.5,-568.98 2892.5,-562.98 2898.5,-562.98 2898.5,-562.98 2975.5,-562.98 2975.5,-562.98 2981.5,-562.98 2987.5,-568.98 2987.5,-574.98 2987.5,-574.98 2987.5,-586.98 2987.5,-586.98 2987.5,-592.98 2981.5,-598.98 2975.5,-598.98"/>
+<text text-anchor="middle" x="2937" y="-583.98" font-family="Arial" font-size="10.00" fill="#111827">AHB&#45;Lite2AXI4</text>
+<text text-anchor="middle" x="2937" y="-572.98" font-family="Arial" font-size="10.00" fill="#111827">single&#45;beat adapter</text>
 </g>
 <!-- mgmt_core&#45;&gt;mgmt_adapter -->
 <g id="edge9" class="edge">
 <title>mgmt_core&#45;&gt;mgmt_adapter</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2907,-658.24C2907,-642.92 2907,-622.4 2907,-606.51"/>
-<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2909.45,-606.12 2907,-599.12 2904.55,-606.12 2909.45,-606.12"/>
-<text text-anchor="middle" x="2923.5" y="-629.08" font-family="Arial" font-size="8.00" fill="#374151">AHB&#45;Lite</text>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2937,-658.24C2937,-642.92 2937,-622.4 2937,-606.51"/>
+<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2939.45,-606.12 2937,-599.12 2934.55,-606.12 2939.45,-606.12"/>
+<text text-anchor="middle" x="2953.5" y="-629.08" font-family="Arial" font-size="8.00" fill="#374151">AHB&#45;Lite</text>
 </g>
 <!-- debug_module -->
 <g id="node11" class="node">
 <title>debug_module</title>
-<path fill="#fce7f3" stroke="#4b5563" stroke-width="1.1" d="M2660.5,-703.48C2660.5,-703.48 2539.5,-703.48 2539.5,-703.48 2533.5,-703.48 2527.5,-697.48 2527.5,-691.48 2527.5,-691.48 2527.5,-670.48 2527.5,-670.48 2527.5,-664.48 2533.5,-658.48 2539.5,-658.48 2539.5,-658.48 2660.5,-658.48 2660.5,-658.48 2666.5,-658.48 2672.5,-664.48 2672.5,-670.48 2672.5,-670.48 2672.5,-691.48 2672.5,-691.48 2672.5,-697.48 2666.5,-703.48 2660.5,-703.48"/>
-<text text-anchor="middle" x="2600" y="-689.48" font-family="Arial" font-size="10.00" fill="#111827">Hazard3 Debug Module</text>
-<text text-anchor="middle" x="2600" y="-678.48" font-family="Arial" font-size="10.00" fill="#111827">abstract commands, no SBA</text>
-<text text-anchor="middle" x="2600" y="-667.48" font-family="Arial" font-size="10.00" fill="#111827">management&#45;hart&#45;only reset</text>
+<path fill="#fce7f3" stroke="#4b5563" stroke-width="1.1" d="M2690.5,-703.48C2690.5,-703.48 2569.5,-703.48 2569.5,-703.48 2563.5,-703.48 2557.5,-697.48 2557.5,-691.48 2557.5,-691.48 2557.5,-670.48 2557.5,-670.48 2557.5,-664.48 2563.5,-658.48 2569.5,-658.48 2569.5,-658.48 2690.5,-658.48 2690.5,-658.48 2696.5,-658.48 2702.5,-664.48 2702.5,-670.48 2702.5,-670.48 2702.5,-691.48 2702.5,-691.48 2702.5,-697.48 2696.5,-703.48 2690.5,-703.48"/>
+<text text-anchor="middle" x="2630" y="-689.48" font-family="Arial" font-size="10.00" fill="#111827">Hazard3 Debug Module</text>
+<text text-anchor="middle" x="2630" y="-678.48" font-family="Arial" font-size="10.00" fill="#111827">abstract commands, no SBA</text>
+<text text-anchor="middle" x="2630" y="-667.48" font-family="Arial" font-size="10.00" fill="#111827">management&#45;hart&#45;only reset</text>
 </g>
 <!-- jtag_dtm&#45;&gt;debug_module -->
 <g id="edge4" class="edge">
 <title>jtag_dtm&#45;&gt;debug_module</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2411.33,-680.98C2446.12,-680.98 2485.91,-680.98 2519.95,-680.98"/>
-<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2520.12,-683.43 2527.12,-680.98 2520.12,-678.53 2520.12,-683.43"/>
-<text text-anchor="middle" x="2469.25" y="-686.58" font-family="Arial" font-size="8.00" fill="#374151">DMI, asynchronous CDC</text>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2441.33,-680.98C2476.12,-680.98 2515.91,-680.98 2549.95,-680.98"/>
+<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2550.12,-683.43 2557.12,-680.98 2550.12,-678.53 2550.12,-683.43"/>
+<text text-anchor="middle" x="2499.25" y="-686.58" font-family="Arial" font-size="8.00" fill="#374151">DMI, asynchronous CDC</text>
 </g>
 <!-- debug_module&#45;&gt;mgmt_core -->
 <g id="edge5" class="edge">
 <title>debug_module&#45;&gt;mgmt_core</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2672.75,-680.98C2713.99,-680.98 2766.09,-680.98 2810.69,-680.98"/>
-<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2810.77,-683.43 2817.77,-680.98 2810.77,-678.53 2810.77,-683.43"/>
-<text text-anchor="middle" x="2745.25" y="-686.58" font-family="Arial" font-size="8.00" fill="#374151">halt, resume, abstract commands</text>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2702.75,-680.98C2743.99,-680.98 2796.09,-680.98 2840.69,-680.98"/>
+<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2840.77,-683.43 2847.77,-680.98 2840.77,-678.53 2840.77,-683.43"/>
+<text text-anchor="middle" x="2775.25" y="-686.58" font-family="Arial" font-size="8.00" fill="#374151">halt, resume, abstract commands</text>
 </g>
 <!-- debug_module&#45;&gt;mgmt_adapter -->
 <g id="edge6" class="edge">
 <title>debug_module&#45;&gt;mgmt_adapter</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M2668.34,-658.47C2740.21,-635.84 2843,-603.48 2843,-603.48 2843,-603.48 2845.48,-602.65 2849.46,-601.31"/>
-<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2850.41,-603.58 2856.26,-599.03 2848.85,-598.94 2850.41,-603.58"/>
-<text text-anchor="middle" x="2802" y="-629.08" font-family="Arial" font-size="8.00" fill="#374151">reset after bridge idle</text>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M2698.34,-658.47C2770.21,-635.84 2873,-603.48 2873,-603.48 2873,-603.48 2875.48,-602.65 2879.46,-601.31"/>
+<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2880.41,-603.58 2886.26,-599.03 2878.85,-598.94 2880.41,-603.58"/>
+<text text-anchor="middle" x="2832" y="-629.08" font-family="Arial" font-size="8.00" fill="#374151">reset after bridge idle</text>
 </g>
 <!-- timers -->
 <g id="node28" class="node">
@@ -225,31 +225,31 @@
 <!-- debug_module&#45;&gt;timers -->
 <g id="edge7" class="edge">
 <title>debug_module&#45;&gt;timers</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M2527.3,-671.05C2479.22,-665.15 2425,-658.48 2425,-658.48 2425,-658.48 1328,-581.98 1328,-581.98 1328,-581.98 1328,-581.98 1328,-356 1328,-356 1323,-289 1323,-289 1323,-289 991,-266 991,-266 991,-266 984.42,-264.48 974.38,-262.17"/>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M2557.3,-671.05C2509.22,-665.15 2455,-658.48 2455,-658.48 2455,-658.48 1325,-581.98 1325,-581.98 1325,-581.98 1325,-581.98 1325,-356 1325,-356 1320,-289 1320,-289 1320,-289 991,-266 991,-266 991,-266 984.42,-264.48 974.38,-262.17"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="974.69,-259.72 967.32,-260.54 973.59,-264.5 974.69,-259.72"/>
-<text text-anchor="middle" x="1339" y="-464.84" font-family="Arial" font-size="8.00" fill="#374151">halted</text>
+<text text-anchor="middle" x="1336" y="-464.84" font-family="Arial" font-size="8.00" fill="#374151">halted</text>
 </g>
 <!-- mgmt_adapter&#45;&gt;fabric -->
 <g id="edge10" class="edge">
 <title>mgmt_adapter&#45;&gt;fabric</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2881.64,-562.94C2859.83,-548.28 2827.52,-526.56 2799.26,-507.57"/>
-<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2800.48,-505.44 2793.3,-503.57 2797.74,-509.5 2800.48,-505.44"/>
-<text text-anchor="middle" x="2847" y="-529.08" font-family="Arial" font-size="8.00" fill="#374151">AXI4</text>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2911.64,-562.94C2889.83,-548.28 2857.52,-526.56 2829.26,-507.57"/>
+<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2830.48,-505.44 2823.3,-503.57 2827.74,-509.5 2830.48,-505.44"/>
+<text text-anchor="middle" x="2877" y="-529.08" font-family="Arial" font-size="8.00" fill="#374151">AXI4</text>
 </g>
 <!-- user_core -->
 <g id="node13" class="node">
 <title>user_core</title>
-<path fill="#ddf2e3" stroke="#4b5563" stroke-width="1.1" d="M2817,-603.48C2817,-603.48 2741,-603.48 2741,-603.48 2735,-603.48 2729,-597.48 2729,-591.48 2729,-591.48 2729,-570.48 2729,-570.48 2729,-564.48 2735,-558.48 2741,-558.48 2741,-558.48 2817,-558.48 2817,-558.48 2823,-558.48 2829,-564.48 2829,-570.48 2829,-570.48 2829,-591.48 2829,-591.48 2829,-597.48 2823,-603.48 2817,-603.48"/>
-<text text-anchor="middle" x="2779" y="-589.48" font-family="Arial" font-size="10.00" fill="#111827">Selected user core</text>
-<text text-anchor="middle" x="2779" y="-578.48" font-family="Arial" font-size="10.00" fill="#111827">C0&#45;C5, one active</text>
-<text text-anchor="middle" x="2779" y="-567.48" font-family="Arial" font-size="10.00" fill="#111827">PicoRV32 at C5</text>
+<path fill="#ddf2e3" stroke="#4b5563" stroke-width="1.1" d="M2847,-603.48C2847,-603.48 2771,-603.48 2771,-603.48 2765,-603.48 2759,-597.48 2759,-591.48 2759,-591.48 2759,-570.48 2759,-570.48 2759,-564.48 2765,-558.48 2771,-558.48 2771,-558.48 2847,-558.48 2847,-558.48 2853,-558.48 2859,-564.48 2859,-570.48 2859,-570.48 2859,-591.48 2859,-591.48 2859,-597.48 2853,-603.48 2847,-603.48"/>
+<text text-anchor="middle" x="2809" y="-589.48" font-family="Arial" font-size="10.00" fill="#111827">Selected user core</text>
+<text text-anchor="middle" x="2809" y="-578.48" font-family="Arial" font-size="10.00" fill="#111827">C0&#45;C5, one active</text>
+<text text-anchor="middle" x="2809" y="-567.48" font-family="Arial" font-size="10.00" fill="#111827">PicoRV32 at C5</text>
 </g>
 <!-- user_core&#45;&gt;fabric -->
 <g id="edge11" class="edge">
 <title>user_core&#45;&gt;fabric</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2771.48,-558.34C2766.79,-544.85 2760.6,-527.03 2754.95,-510.75"/>
-<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2757.17,-509.7 2752.56,-503.89 2752.54,-511.31 2757.17,-509.7"/>
-<text text-anchor="middle" x="2771" y="-529.08" font-family="Arial" font-size="8.00" fill="#374151">AXI4</text>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2801.48,-558.34C2796.79,-544.85 2790.6,-527.03 2784.95,-510.75"/>
+<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2787.17,-509.7 2782.56,-503.89 2782.54,-511.31 2787.17,-509.7"/>
+<text text-anchor="middle" x="2801" y="-529.08" font-family="Arial" font-size="8.00" fill="#374151">AXI4</text>
 </g>
 <!-- dma -->
 <g id="node14" class="node">
@@ -261,9 +261,9 @@
 <!-- dma&#45;&gt;fabric -->
 <g id="edge12" class="edge">
 <title>dma&#45;&gt;fabric</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1863.31,-569.93C2023.64,-551.24 2369.85,-510.88 2575.99,-486.86"/>
-<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2576.29,-489.29 2582.96,-486.05 2575.72,-484.42 2576.29,-489.29"/>
-<text text-anchor="middle" x="2238" y="-529.08" font-family="Arial" font-size="8.00" fill="#374151">AXI4</text>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1863.39,-570.22C2028.43,-551.56 2391.09,-510.57 2604.34,-486.47"/>
+<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2604.87,-488.87 2611.55,-485.65 2604.32,-484 2604.87,-488.87"/>
+<text text-anchor="middle" x="2252" y="-529.08" font-family="Arial" font-size="8.00" fill="#374151">AXI4</text>
 </g>
 <!-- stream_io -->
 <g id="node24" class="node">
@@ -277,10 +277,10 @@
 <!-- dma&#45;&gt;stream_io -->
 <g id="edge13" class="edge">
 <title>dma&#45;&gt;stream_io</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1870.2,-575.24C2127.54,-562.16 2829,-526.48 2829,-526.48 2829,-526.48 3346,-503.48 3346,-503.48 3346,-503.48 4267,-266 4267,-266 4267,-266 4269.6,-265.28 4273.96,-264.06"/>
-<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1869.96,-572.8 1863.09,-575.61 1870.21,-577.7 1869.96,-572.8"/>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1870.52,-575.36C2133.25,-562.37 2859,-526.48 2859,-526.48 2859,-526.48 3376,-503.48 3376,-503.48 3376,-503.48 4267,-266 4267,-266 4267,-266 4269.6,-265.28 4273.96,-264.06"/>
+<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1870.13,-572.93 1863.26,-575.72 1870.37,-577.82 1870.13,-572.93"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="4274.81,-266.37 4280.9,-262.13 4273.5,-261.65 4274.81,-266.37"/>
-<text text-anchor="middle" x="3776.5" y="-400.6" font-family="Arial" font-size="8.00" fill="#374151">AXI4&#45;Stream</text>
+<text text-anchor="middle" x="3793.5" y="-400.6" font-family="Arial" font-size="8.00" fill="#374151">AXI4&#45;Stream</text>
 </g>
 <!-- uart0 -->
 <g id="node25" class="node">
@@ -308,9 +308,9 @@
 <!-- dma&#45;&gt;i2c_controllers -->
 <g id="edge47" class="edge">
 <title>dma&#45;&gt;i2c_controllers</title>
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-<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1426.66,-260.39 1419.25,-260.64 1425.2,-265.07 1426.66,-260.39"/>
-<text text-anchor="middle" x="1656" y="-400.6" font-family="Arial" font-size="8.00" fill="#374151">DATA_CMD / RXDATA</text>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M1761.16,-562.65C1703.89,-500.01 1511,-289 1511,-289 1511,-289 1468.1,-275.68 1426.59,-262.79"/>
+<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1427.09,-260.38 1419.68,-260.64 1425.64,-265.06 1427.09,-260.38"/>
+<text text-anchor="middle" x="1657" y="-400.6" font-family="Arial" font-size="8.00" fill="#374151">DATA_CMD / RXDATA</text>
 </g>
 <!-- ws2812 -->
 <g id="node29" class="node">
@@ -330,59 +330,59 @@
 <!-- fault -->
 <g id="node16" class="node">
 <title>fault</title>
-<path fill="#fce7f3" stroke="#4b5563" stroke-width="1.1" d="M3320.5,-484.74C3320.5,-484.74 3211.5,-484.74 3211.5,-484.74 3205.5,-484.74 3199.5,-478.74 3199.5,-472.74 3199.5,-472.74 3199.5,-460.74 3199.5,-460.74 3199.5,-454.74 3205.5,-448.74 3211.5,-448.74 3211.5,-448.74 3320.5,-448.74 3320.5,-448.74 3326.5,-448.74 3332.5,-454.74 3332.5,-460.74 3332.5,-460.74 3332.5,-472.74 3332.5,-472.74 3332.5,-478.74 3326.5,-484.74 3320.5,-484.74"/>
-<text text-anchor="middle" x="3266" y="-469.74" font-family="Arial" font-size="10.00" fill="#111827">Error slave</text>
-<text text-anchor="middle" x="3266" y="-458.74" font-family="Arial" font-size="10.00" fill="#111827">access and protocol faults</text>
+<path fill="#fce7f3" stroke="#4b5563" stroke-width="1.1" d="M3350.5,-484.74C3350.5,-484.74 3241.5,-484.74 3241.5,-484.74 3235.5,-484.74 3229.5,-478.74 3229.5,-472.74 3229.5,-472.74 3229.5,-460.74 3229.5,-460.74 3229.5,-454.74 3235.5,-448.74 3241.5,-448.74 3241.5,-448.74 3350.5,-448.74 3350.5,-448.74 3356.5,-448.74 3362.5,-454.74 3362.5,-460.74 3362.5,-460.74 3362.5,-472.74 3362.5,-472.74 3362.5,-478.74 3356.5,-484.74 3350.5,-484.74"/>
+<text text-anchor="middle" x="3296" y="-469.74" font-family="Arial" font-size="10.00" fill="#111827">Error slave</text>
+<text text-anchor="middle" x="3296" y="-458.74" font-family="Arial" font-size="10.00" fill="#111827">access and protocol faults</text>
 </g>
 <!-- fabric&#45;&gt;fault -->
 <g id="edge14" class="edge">
 <title>fabric&#45;&gt;fault</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2884.8,-494.31C2964.94,-509.57 3048.5,-525.48 3048.5,-525.48 3048.5,-525.48 3101.5,-525.48 3101.5,-525.48 3101.5,-525.48 3186,-503.48 3186,-503.48 3186,-503.48 3202.11,-496.08 3219.88,-487.93"/>
-<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2884.89,-491.84 2877.56,-492.94 2883.98,-496.65 2884.89,-491.84"/>
-<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3221.13,-490.05 3226.47,-484.9 3219.08,-485.59 3221.13,-490.05"/>
-<text text-anchor="middle" x="3075" y="-529.08" font-family="Arial" font-size="8.00" fill="#374151">invalid / denied</text>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2914.8,-494.31C2994.94,-509.57 3078.5,-525.48 3078.5,-525.48 3078.5,-525.48 3131.5,-525.48 3131.5,-525.48 3131.5,-525.48 3216,-503.48 3216,-503.48 3216,-503.48 3232.11,-496.08 3249.88,-487.93"/>
+<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2914.89,-491.84 2907.56,-492.94 2913.98,-496.65 2914.89,-491.84"/>
+<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3251.13,-490.05 3256.47,-484.9 3249.08,-485.59 3251.13,-490.05"/>
+<text text-anchor="middle" x="3105" y="-529.08" font-family="Arial" font-size="8.00" fill="#374151">invalid / denied</text>
 </g>
 <!-- sram -->
 <g id="node17" class="node">
 <title>sram</title>
-<path fill="#fff3c9" stroke="#4b5563" stroke-width="1.1" d="M3160.5,-484.74C3160.5,-484.74 3017.5,-484.74 3017.5,-484.74 3011.5,-484.74 3005.5,-478.74 3005.5,-472.74 3005.5,-472.74 3005.5,-460.74 3005.5,-460.74 3005.5,-454.74 3011.5,-448.74 3017.5,-448.74 3017.5,-448.74 3160.5,-448.74 3160.5,-448.74 3166.5,-448.74 3172.5,-454.74 3172.5,-460.74 3172.5,-460.74 3172.5,-472.74 3172.5,-472.74 3172.5,-478.74 3166.5,-484.74 3160.5,-484.74"/>
-<text text-anchor="middle" x="3089" y="-469.74" font-family="Arial" font-size="10.00" fill="#111827">On&#45;chip SRAM</text>
-<text text-anchor="middle" x="3089" y="-458.74" font-family="Arial" font-size="10.00" fill="#111827">optional pipelined AXI42RAM path</text>
+<path fill="#fff3c9" stroke="#4b5563" stroke-width="1.1" d="M3190.5,-484.74C3190.5,-484.74 3047.5,-484.74 3047.5,-484.74 3041.5,-484.74 3035.5,-478.74 3035.5,-472.74 3035.5,-472.74 3035.5,-460.74 3035.5,-460.74 3035.5,-454.74 3041.5,-448.74 3047.5,-448.74 3047.5,-448.74 3190.5,-448.74 3190.5,-448.74 3196.5,-448.74 3202.5,-454.74 3202.5,-460.74 3202.5,-460.74 3202.5,-472.74 3202.5,-472.74 3202.5,-478.74 3196.5,-484.74 3190.5,-484.74"/>
+<text text-anchor="middle" x="3119" y="-469.74" font-family="Arial" font-size="10.00" fill="#111827">On&#45;chip SRAM</text>
+<text text-anchor="middle" x="3119" y="-458.74" font-family="Arial" font-size="10.00" fill="#111827">optional pipelined AXI42RAM path</text>
 </g>
 <!-- fabric&#45;&gt;sram -->
 <g id="edge15" class="edge">
 <title>fabric&#45;&gt;sram</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2952.32,-466.74C2968.24,-466.74 2983.72,-466.74 2998.2,-466.74"/>
-<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2998.22,-469.19 3005.22,-466.74 2998.22,-464.29 2998.22,-469.19"/>
-<text text-anchor="middle" x="2978.89" y="-472.34" font-family="Arial" font-size="8.00" fill="#374151">AXI4</text>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2982.32,-466.74C2998.24,-466.74 3013.72,-466.74 3028.2,-466.74"/>
+<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3028.22,-469.19 3035.22,-466.74 3028.22,-464.29 3028.22,-469.19"/>
+<text text-anchor="middle" x="3008.89" y="-472.34" font-family="Arial" font-size="8.00" fill="#374151">AXI4</text>
 </g>
-<!-- apb4_adapter -->
+<!-- apb4_periph -->
 <g id="node18" class="node">
-<title>apb4_adapter</title>
+<title>apb4_periph</title>
 <path fill="#e5e7eb" stroke="#4b5563" stroke-width="1.1" d="M1922.5,-375C1922.5,-375 1817.5,-375 1817.5,-375 1811.5,-375 1805.5,-369 1805.5,-363 1805.5,-363 1805.5,-351 1805.5,-351 1805.5,-345 1811.5,-339 1817.5,-339 1817.5,-339 1922.5,-339 1922.5,-339 1928.5,-339 1934.5,-345 1934.5,-351 1934.5,-351 1934.5,-363 1934.5,-363 1934.5,-369 1928.5,-375 1922.5,-375"/>
 <text text-anchor="middle" x="1870" y="-360" font-family="Arial" font-size="10.00" fill="#111827">AXI42APB</text>
 <text text-anchor="middle" x="1870" y="-349" font-family="Arial" font-size="10.00" fill="#111827">APB4 configuration plane</text>
 </g>
-<!-- fabric&#45;&gt;apb4_adapter -->
+<!-- fabric&#45;&gt;apb4_periph -->
 <g id="edge17" class="edge">
-<title>fabric&#45;&gt;apb4_adapter</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2585.46,-446.6C2395.67,-423.1 2081.71,-384.22 1941.49,-366.85"/>
-<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1941.78,-364.42 1934.53,-365.99 1941.18,-369.28 1941.78,-364.42"/>
-<text text-anchor="middle" x="2272.5" y="-400.6" font-family="Arial" font-size="8.00" fill="#374151">AXI4 config</text>
+<title>fabric&#45;&gt;apb4_periph</title>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2614,-447.07C2417.16,-423.5 2086.85,-383.96 1941.89,-366.61"/>
+<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1941.95,-364.15 1934.71,-365.75 1941.36,-369.01 1941.95,-364.15"/>
+<text text-anchor="middle" x="2286.5" y="-400.6" font-family="Arial" font-size="8.00" fill="#374151">AXI4 config</text>
 </g>
-<!-- apb_adapter -->
+<!-- apb4_system -->
 <g id="node19" class="node">
-<title>apb_adapter</title>
-<path fill="#e5e7eb" stroke="#4b5563" stroke-width="1.1" d="M3118,-375C3118,-375 3048,-375 3048,-375 3042,-375 3036,-369 3036,-363 3036,-363 3036,-351 3036,-351 3036,-345 3042,-339 3048,-339 3048,-339 3118,-339 3118,-339 3124,-339 3130,-345 3130,-351 3130,-351 3130,-363 3130,-363 3130,-369 3124,-375 3118,-375"/>
-<text text-anchor="middle" x="3083" y="-360" font-family="Arial" font-size="10.00" fill="#111827">AXI42APB</text>
-<text text-anchor="middle" x="3083" y="-349" font-family="Arial" font-size="10.00" fill="#111827">direct APB bridge</text>
+<title>apb4_system</title>
+<path fill="#e5e7eb" stroke="#4b5563" stroke-width="1.1" d="M3123,-375C3123,-375 3053,-375 3053,-375 3047,-375 3041,-369 3041,-363 3041,-363 3041,-351 3041,-351 3041,-345 3047,-339 3053,-339 3053,-339 3123,-339 3123,-339 3129,-339 3135,-345 3135,-351 3135,-351 3135,-363 3135,-363 3135,-369 3129,-375 3123,-375"/>
+<text text-anchor="middle" x="3088" y="-360" font-family="Arial" font-size="10.00" fill="#111827">AXI42APB</text>
+<text text-anchor="middle" x="3088" y="-349" font-family="Arial" font-size="10.00" fill="#111827">direct APB bridge</text>
 </g>
-<!-- fabric&#45;&gt;apb_adapter -->
+<!-- fabric&#45;&gt;apb4_system -->
 <g id="edge18" class="edge">
-<title>fabric&#45;&gt;apb_adapter</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2850.42,-431.06C2910.15,-412.3 2981.25,-389.96 3028.98,-374.97"/>
-<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3029.9,-377.25 3035.85,-372.81 3028.43,-372.57 3029.9,-377.25"/>
-<text text-anchor="middle" x="2961" y="-400.6" font-family="Arial" font-size="8.00" fill="#374151">AXI4</text>
+<title>fabric&#45;&gt;apb4_system</title>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2875.89,-429.87C2928.88,-411.91 2990.77,-390.94 3033.97,-376.31"/>
+<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3034.89,-378.58 3040.74,-374.01 3033.32,-373.94 3034.89,-378.58"/>
+<text text-anchor="middle" x="2975" y="-400.6" font-family="Arial" font-size="8.00" fill="#374151">AXI4</text>
 </g>
 <!-- memory_targets -->
 <g id="node23" class="node">
@@ -395,9 +395,9 @@
 <!-- fabric&#45;&gt;memory_targets -->
 <g id="edge16" class="edge">
 <title>fabric&#45;&gt;memory_targets</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2867.27,-437.16C2985.69,-410.56 3144,-375 3144,-375 3144,-375 3292,-316 3292,-316 3292,-316 3354,-289 3354,-289 3354,-289 4035,-266 4035,-266 4035,-266 4041.52,-264.48 4051.47,-262.17"/>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2894.1,-436.03C3004.63,-409.57 3149,-375 3149,-375 3149,-375 3322,-316 3322,-316 3322,-316 3384,-289 3384,-289 3384,-289 4035,-266 4035,-266 4035,-266 4041.52,-264.48 4051.47,-262.17"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="4052.21,-264.51 4058.47,-260.54 4051.1,-259.74 4052.21,-264.51"/>
-<text text-anchor="middle" x="3250" y="-355.1" font-family="Arial" font-size="8.00" fill="#374151">AXI4 data</text>
+<text text-anchor="middle" x="3270" y="-355.1" font-family="Arial" font-size="8.00" fill="#374151">AXI4 data</text>
 </g>
 <!-- sysctrl -->
 <g id="node20" class="node">
@@ -407,45 +407,45 @@
 <text text-anchor="middle" x="2273" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">PLL, user&#45;core select/reset/bus enable</text>
 <text text-anchor="middle" x="2273" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">fault and performance control</text>
 </g>
-<!-- apb4_adapter&#45;&gt;sysctrl -->
+<!-- apb4_periph&#45;&gt;sysctrl -->
 <g id="edge19" class="edge">
-<title>apb4_adapter&#45;&gt;sysctrl</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1922.09,-338.92C1955.25,-328.05 1992,-316 1992,-316 1992,-316 2074,-289 2074,-289 2074,-289 2166,-266 2166,-266 2166,-266 2171.79,-264.54 2180.67,-262.3"/>
+<title>apb4_periph&#45;&gt;sysctrl</title>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1922.09,-338.92C1955.25,-328.05 1992,-316 1992,-316 1992,-316 2070,-289 2070,-289 2070,-289 2166,-266 2166,-266 2166,-266 2171.79,-264.54 2180.67,-262.3"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2181.47,-264.62 2187.65,-260.54 2180.27,-259.87 2181.47,-264.62"/>
-<text text-anchor="middle" x="2084.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
+<text text-anchor="middle" x="2080.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
 </g>
-<!-- apb4_adapter&#45;&gt;clint -->
+<!-- apb4_periph&#45;&gt;clint -->
 <g id="edge20" class="edge">
-<title>apb4_adapter&#45;&gt;clint</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1805.28,-339.82C1803.2,-339.3 1802,-339 1802,-339 1802,-339 1434,-316 1434,-316 1434,-316 1332,-289 1332,-289 1332,-289 554,-266 554,-266 554,-266 549.74,-264.68 543.1,-262.62"/>
+<title>apb4_periph&#45;&gt;clint</title>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1805.28,-339.82C1803.2,-339.3 1802,-339 1802,-339 1802,-339 1430,-316 1430,-316 1430,-316 1329,-289 1329,-289 1329,-289 554,-266 554,-266 554,-266 549.74,-264.68 543.1,-262.62"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="543.81,-260.27 536.39,-260.54 542.35,-264.95 543.81,-260.27"/>
-<text text-anchor="middle" x="1444.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
+<text text-anchor="middle" x="1440.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
 </g>
-<!-- apb4_targets -->
+<!-- apb4_periph_targets -->
 <g id="node22" class="node">
-<title>apb4_targets</title>
+<title>apb4_periph_targets</title>
 <path fill="#f9e1e7" stroke="#4b5563" stroke-width="1.1" d="M2140.5,-260.5C2140.5,-260.5 1941.5,-260.5 1941.5,-260.5 1935.5,-260.5 1929.5,-254.5 1929.5,-248.5 1929.5,-248.5 1929.5,-227.5 1929.5,-227.5 1929.5,-221.5 1935.5,-215.5 1941.5,-215.5 1941.5,-215.5 2140.5,-215.5 2140.5,-215.5 2146.5,-215.5 2152.5,-221.5 2152.5,-227.5 2152.5,-227.5 2152.5,-248.5 2152.5,-248.5 2152.5,-254.5 2146.5,-260.5 2140.5,-260.5"/>
 <text text-anchor="middle" x="2041" y="-246.5" font-family="Arial" font-size="10.00" fill="#111827">APB4 configuration targets</text>
 <text text-anchor="middle" x="2041" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">XPI, SDRAM, PSRAM, SPI&#45;SD, DVP and I2S</text>
 <text text-anchor="middle" x="2041" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">SDRAM config is a dedicated top&#45;level port</text>
 </g>
-<!-- apb4_adapter&#45;&gt;apb4_targets -->
+<!-- apb4_periph&#45;&gt;apb4_periph_targets -->
 <g id="edge21" class="edge">
-<title>apb4_adapter&#45;&gt;apb4_targets</title>
+<title>apb4_periph&#45;&gt;apb4_periph_targets</title>
 <path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1894.86,-338.99C1923.38,-319.48 1970.43,-287.28 2003.43,-264.71"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2005.02,-266.59 2009.41,-260.61 2002.25,-262.54 2005.02,-266.59"/>
 <text text-anchor="middle" x="1975.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
 </g>
-<!-- apb4_adapter&#45;&gt;uart0 -->
+<!-- apb4_periph&#45;&gt;uart0 -->
 <g id="edge22" class="edge">
-<title>apb4_adapter&#45;&gt;uart0</title>
+<title>apb4_periph&#45;&gt;uart0</title>
 <path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1844,-338.92C1813.78,-319.07 1768,-289 1768,-289 1768,-289 1723.05,-275.62 1679.65,-262.71"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1680.12,-260.29 1672.71,-260.64 1678.72,-264.98 1680.12,-260.29"/>
 <text text-anchor="middle" x="1816.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
 </g>
-<!-- apb4_adapter&#45;&gt;i2c_controllers -->
+<!-- apb4_periph&#45;&gt;i2c_controllers -->
 <g id="edge23" class="edge">
-<title>apb4_adapter&#45;&gt;i2c_controllers</title>
+<title>apb4_periph&#45;&gt;i2c_controllers</title>
 <path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1814.92,-338.92C1779.86,-328.05 1741,-316 1741,-316 1741,-316 1692,-289 1692,-289 1692,-289 1469,-266 1469,-266 1469,-266 1462.18,-264.45 1451.81,-262.1"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1452.29,-259.7 1444.92,-260.54 1451.2,-264.47 1452.29,-259.7"/>
 <text text-anchor="middle" x="1751.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
@@ -458,41 +458,41 @@
 <text text-anchor="middle" x="2481" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">user + management APB4 windows</text>
 <text text-anchor="middle" x="2481" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">atomic I/O, filter, locks, IRQ18</text>
 </g>
-<!-- apb4_adapter&#45;&gt;gpio_controller -->
+<!-- apb4_periph&#45;&gt;gpio_controller -->
 <g id="edge24" class="edge">
-<title>apb4_adapter&#45;&gt;gpio_controller</title>
+<title>apb4_periph&#45;&gt;gpio_controller</title>
 <path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1934.55,-352.83C2127.08,-343.37 2684,-316 2684,-316 2684,-316 2684,-289 2684,-289 2684,-289 2628.59,-275.35 2575.67,-262.32"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2575.95,-259.86 2568.56,-260.57 2574.77,-264.62 2575.95,-259.86"/>
 <text text-anchor="middle" x="2704" y="-305.1" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
 <text text-anchor="middle" x="2704" y="-296.1" font-family="Arial" font-size="8.00" fill="#374151">user/admin</text>
 </g>
-<!-- apb4_adapter&#45;&gt;timers -->
+<!-- apb4_periph&#45;&gt;timers -->
 <g id="edge25" class="edge">
-<title>apb4_adapter&#45;&gt;timers</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1805.23,-346.37C1725.63,-334.53 1601,-316 1601,-316 1601,-316 1510,-289 1510,-289 1510,-289 991,-266 991,-266 991,-266 984.42,-264.48 974.38,-262.17"/>
+<title>apb4_periph&#45;&gt;timers</title>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1805.23,-346.37C1725.63,-334.53 1601,-316 1601,-316 1601,-316 1511,-289 1511,-289 1511,-289 991,-266 991,-266 991,-266 984.42,-264.48 974.38,-262.17"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="974.69,-259.72 967.32,-260.54 973.59,-264.5 974.69,-259.72"/>
 <text text-anchor="middle" x="1611.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
 </g>
-<!-- apb4_adapter&#45;&gt;ws2812 -->
+<!-- apb4_periph&#45;&gt;ws2812 -->
 <g id="edge26" class="edge">
-<title>apb4_adapter&#45;&gt;ws2812</title>
+<title>apb4_periph&#45;&gt;ws2812</title>
 <path fill="none" stroke="#4b5563" stroke-width="1.2" d="M1863.31,-338.99C1855.95,-320.26 1843.99,-289.86 1835.2,-267.48"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1837.42,-266.44 1832.58,-260.82 1832.86,-268.23 1837.42,-266.44"/>
 <text text-anchor="middle" x="1863.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
 </g>
-<!-- apb_targets -->
+<!-- apb4_system_targets -->
 <g id="node30" class="node">
-<title>apb_targets</title>
+<title>apb4_system_targets</title>
 <path fill="#e6f4ea" stroke="#4b5563" stroke-width="1.1" d="M3774,-256C3774,-256 3694,-256 3694,-256 3688,-256 3682,-250 3682,-244 3682,-244 3682,-232 3682,-232 3682,-226 3688,-220 3694,-220 3694,-220 3774,-220 3774,-220 3780,-220 3786,-226 3786,-232 3786,-232 3786,-244 3786,-244 3786,-250 3780,-256 3774,-256"/>
 <text text-anchor="middle" x="3734" y="-241" font-family="Arial" font-size="10.00" fill="#111827">APB target wrapper</text>
 <text text-anchor="middle" x="3734" y="-230" font-family="Arial" font-size="10.00" fill="#111827">User IP target</text>
 </g>
-<!-- apb_adapter&#45;&gt;apb_targets -->
+<!-- apb4_system&#45;&gt;apb4_system_targets -->
 <g id="edge34" class="edge">
-<title>apb_adapter&#45;&gt;apb_targets</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3130.27,-339.27C3161.23,-328.31 3196,-316 3196,-316 3196,-316 3226,-289 3226,-289 3226,-289 3669,-266 3669,-266 3669,-266 3676.36,-262.94 3686.12,-258.89"/>
+<title>apb4_system&#45;&gt;apb4_system_targets</title>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3135.3,-341.22C3171.76,-329.82 3216,-316 3216,-316 3216,-316 3246,-289 3246,-289 3246,-289 3669,-266 3669,-266 3669,-266 3676.36,-262.94 3686.12,-258.89"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3687.31,-261.05 3692.83,-256.1 3685.43,-256.52 3687.31,-261.05"/>
-<text text-anchor="middle" x="3234" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
+<text text-anchor="middle" x="3256.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
 </g>
 <!-- pwm -->
 <g id="node31" class="node">
@@ -502,19 +502,19 @@
 <text text-anchor="middle" x="3281" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">2 timers, 4 action channels, 2 operators</text>
 <text text-anchor="middle" x="3281" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">fades, dead time, carrier, fault and capture, IRQ11</text>
 </g>
-<!-- apb_adapter&#45;&gt;pwm -->
+<!-- apb4_system&#45;&gt;pwm -->
 <g id="edge33" class="edge">
-<title>apb_adapter&#45;&gt;pwm</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3095.1,-338.75C3109.03,-318.89 3130,-289 3130,-289 3130,-289 3170.07,-275.73 3208.92,-262.87"/>
-<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3209.77,-265.17 3215.65,-260.64 3208.23,-260.51 3209.77,-265.17"/>
-<text text-anchor="middle" x="3138" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
+<title>apb4_system&#45;&gt;pwm</title>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3101.39,-338.75C3116.8,-318.89 3140,-289 3140,-289 3140,-289 3177.11,-275.84 3213.25,-263.03"/>
+<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3214.2,-265.29 3219.98,-260.64 3212.56,-260.67 3214.2,-265.29"/>
+<text text-anchor="middle" x="3150.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
 </g>
-<!-- apb_adapter&#45;&gt;wdg -->
+<!-- apb4_system&#45;&gt;wdg -->
 <g id="edge31" class="edge">
-<title>apb_adapter&#45;&gt;wdg</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3035.7,-354.81C2771.27,-348.18 1488,-316 1488,-316 1488,-316 1457,-289 1457,-289 1457,-289 758,-266 758,-266 758,-266 752.59,-264.57 744.26,-262.36"/>
+<title>apb4_system&#45;&gt;wdg</title>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3040.86,-354.82C2775.92,-348.22 1484,-316 1484,-316 1484,-316 1453,-289 1453,-289 1453,-289 758,-266 758,-266 758,-266 752.59,-264.57 744.26,-262.36"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="744.75,-259.96 737.36,-260.54 743.5,-264.7 744.75,-259.96"/>
-<text text-anchor="middle" x="1496" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
+<text text-anchor="middle" x="1494.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
 </g>
 <!-- crc -->
 <g id="node33" class="node">
@@ -524,19 +524,19 @@
 <text text-anchor="middle" x="3917" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">programmable 7/8/16/32&#45;bit streaming CRC</text>
 <text text-anchor="middle" x="3917" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">byte, halfword and word APB feed</text>
 </g>
-<!-- apb_adapter&#45;&gt;crc -->
+<!-- apb4_system&#45;&gt;crc -->
 <g id="edge32" class="edge">
-<title>apb_adapter&#45;&gt;crc</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3130,-344.32C3177.52,-332.52 3244,-316 3244,-316 3244,-316 3274,-289 3274,-289 3274,-289 3800,-266 3800,-266 3800,-266 3806.58,-264.48 3816.62,-262.17"/>
+<title>apb4_system&#45;&gt;crc</title>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3135.08,-345.59C3188.71,-333.74 3269,-316 3269,-316 3269,-316 3299,-289 3299,-289 3299,-289 3800,-266 3800,-266 3800,-266 3806.58,-264.48 3816.62,-262.17"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3817.41,-264.5 3823.68,-260.54 3816.31,-259.72 3817.41,-264.5"/>
-<text text-anchor="middle" x="3282" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
+<text text-anchor="middle" x="3309.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
 </g>
-<!-- apb_adapter&#45;&gt;rtc -->
+<!-- apb4_system&#45;&gt;rtc -->
 <g id="edge30" class="edge">
-<title>apb_adapter&#45;&gt;rtc</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3035.69,-354.02C2843.19,-345.95 2129,-316 2129,-316 2129,-316 2097,-289 2097,-289 2097,-289 1232,-266 1232,-266 1232,-266 1225.07,-264.45 1214.52,-262.1"/>
+<title>apb4_system&#45;&gt;rtc</title>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3040.85,-354.04C2847.31,-346.01 2124,-316 2124,-316 2124,-316 2093,-289 2093,-289 2093,-289 1232,-266 1232,-266 1232,-266 1225.07,-264.45 1214.52,-262.1"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1214.88,-259.67 1207.51,-260.54 1213.81,-264.45 1214.88,-259.67"/>
-<text text-anchor="middle" x="2137" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
+<text text-anchor="middle" x="2134.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
 </g>
 <!-- archinfo -->
 <g id="node35" class="node">
@@ -546,12 +546,12 @@
 <text text-anchor="middle" x="3541" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">read&#45;only build, topology and technology identity</text>
 <text text-anchor="middle" x="3541" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">lifecycle&#45;gated 128&#45;bit device ID</text>
 </g>
-<!-- apb_adapter&#45;&gt;archinfo -->
+<!-- apb4_system&#45;&gt;archinfo -->
 <g id="edge27" class="edge">
-<title>apb_adapter&#45;&gt;archinfo</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3110.94,-338.8C3128.56,-327.96 3148,-316 3148,-316 3148,-316 3178,-289 3178,-289 3178,-289 3414,-266 3414,-266 3414,-266 3421.42,-264.42 3432.66,-262.03"/>
+<title>apb4_system&#45;&gt;archinfo</title>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3120.24,-338.8C3140.57,-327.96 3163,-316 3163,-316 3163,-316 3193,-289 3193,-289 3193,-289 3414,-266 3414,-266 3414,-266 3421.42,-264.42 3432.66,-262.03"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3433.36,-264.39 3439.7,-260.54 3432.34,-259.6 3433.36,-264.39"/>
-<text text-anchor="middle" x="3186" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
+<text text-anchor="middle" x="3203.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
 </g>
 <!-- rng -->
 <g id="node36" class="node">
@@ -561,12 +561,12 @@
 <text text-anchor="middle" x="2762" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">8&#45;word FIFO, fail&#45;closed monitoring, IRQ16</text>
 <text text-anchor="middle" x="2762" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">management&#45;only, deterministic source unqualified</text>
 </g>
-<!-- apb_adapter&#45;&gt;rng -->
+<!-- apb4_system&#45;&gt;rng -->
 <g id="edge28" class="edge">
-<title>apb_adapter&#45;&gt;rng</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3062.66,-338.75C3039.25,-318.89 3004,-289 3004,-289 3004,-289 2936.86,-275.13 2873.31,-262"/>
+<title>apb4_system&#45;&gt;rng</title>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3065.65,-338.8C3051.55,-327.96 3036,-316 3036,-316 3036,-316 3004,-289 3004,-289 3004,-289 2936.86,-275.13 2873.31,-262"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2873.74,-259.58 2866.39,-260.57 2872.75,-264.38 2873.74,-259.58"/>
-<text text-anchor="middle" x="3042" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
+<text text-anchor="middle" x="3046.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
 </g>
 <!-- ps2 -->
 <g id="node37" class="node">
@@ -576,12 +576,12 @@
 <text text-anchor="middle" x="3045" y="-235.5" font-family="Arial" font-size="10.00" fill="#111827">bidirectional open&#45;drain transport</text>
 <text text-anchor="middle" x="3045" y="-224.5" font-family="Arial" font-size="10.00" fill="#111827">16&#45;byte RX/TX FIFOs, errors, IRQ12</text>
 </g>
-<!-- apb_adapter&#45;&gt;ps2 -->
+<!-- apb4_system&#45;&gt;ps2 -->
 <g id="edge29" class="edge">
-<title>apb_adapter&#45;&gt;ps2</title>
-<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3077.47,-338.99C3071.39,-320.26 3061.52,-289.86 3054.25,-267.48"/>
-<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3056.58,-266.72 3052.09,-260.82 3051.92,-268.23 3056.58,-266.72"/>
-<text text-anchor="middle" x="3077" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB</text>
+<title>apb4_system&#45;&gt;ps2</title>
+<path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3081.75,-338.99C3074.87,-320.26 3063.69,-289.86 3055.47,-267.48"/>
+<polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="3057.73,-266.54 3053.02,-260.82 3053.13,-268.23 3057.73,-266.54"/>
+<text text-anchor="middle" x="3082.5" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4</text>
 </g>
 <!-- irq -->
 <g id="node39" class="node">
@@ -597,23 +597,23 @@
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1476.84,-147.81 1483.68,-144.94 1476.54,-142.92 1476.84,-147.81"/>
 <text text-anchor="middle" x="968.5" y="-180.6" font-family="Arial" font-size="8.00" fill="#374151">machine IRQ0 / IRQ1</text>
 </g>
-<!-- apb4_targets&#45;&gt;memory_targets -->
+<!-- apb4_periph_targets&#45;&gt;memory_targets -->
 <g id="edge61" class="edge">
-<title>apb4_targets&#45;&gt;memory_targets</title>
+<title>apb4_periph_targets&#45;&gt;memory_targets</title>
 <path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M2141.6,-260.53C2155.97,-263.75 2166,-266 2166,-266 2166,-266 2801.5,-297 2801.5,-297 2801.5,-297 2870.5,-297 2870.5,-297 2870.5,-297 4035,-266 4035,-266 4035,-266 4041.14,-264.52 4050.6,-262.23"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="4051.41,-264.56 4057.64,-260.53 4050.26,-259.8 4051.41,-264.56"/>
 <text text-anchor="middle" x="2836" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4 configuration</text>
 </g>
-<!-- apb4_targets&#45;&gt;stream_io -->
+<!-- apb4_periph_targets&#45;&gt;stream_io -->
 <g id="edge62" class="edge">
-<title>apb4_targets&#45;&gt;stream_io</title>
+<title>apb4_periph_targets&#45;&gt;stream_io</title>
 <path fill="none" stroke="#4b5563" stroke-width="1.2" stroke-dasharray="5,2" d="M2141.6,-260.53C2155.97,-263.75 2166,-266 2166,-266 2166,-266 2933.5,-297 2933.5,-297 2933.5,-297 3002.5,-297 3002.5,-297 3002.5,-297 4267,-266 4267,-266 4267,-266 4269.6,-265.25 4273.96,-263.99"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="4274.85,-266.28 4280.9,-261.99 4273.49,-261.58 4274.85,-266.28"/>
 <text text-anchor="middle" x="2968" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">APB4 configuration</text>
 </g>
-<!-- apb4_targets&#45;&gt;gpio_controller -->
+<!-- apb4_periph_targets&#45;&gt;gpio_controller -->
 <g id="edge35" class="edge">
-<title>apb4_targets&#45;&gt;gpio_controller</title>
+<title>apb4_periph_targets&#45;&gt;gpio_controller</title>
 <path fill="none" stroke="#4b5563" stroke-width="1.2" d="M2107.78,-260.64C2156.84,-277.28 2215,-297 2215,-297 2215,-297 2281,-297 2281,-297 2281,-297 2342.68,-278.8 2397.54,-262.62"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2398.51,-264.89 2404.53,-260.56 2397.13,-260.19 2398.51,-264.89"/>
 <text text-anchor="middle" x="2248" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">alternate functions</text>
@@ -715,9 +715,9 @@
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="1646.13,-155.71 1638.74,-155.12 1644.15,-160.19 1646.13,-155.71"/>
 <text text-anchor="middle" x="1717" y="-180.6" font-family="Arial" font-size="8.00" fill="#374151">IRQ17</text>
 </g>
-<!-- apb_targets&#45;&gt;gpio_controller -->
+<!-- apb4_system_targets&#45;&gt;gpio_controller -->
 <g id="edge60" class="edge">
-<title>apb_targets&#45;&gt;gpio_controller</title>
+<title>apb4_system_targets&#45;&gt;gpio_controller</title>
 <path fill="none" stroke="#4b5563" stroke-width="1.2" d="M3692.1,-256.05C3679.52,-261.47 3669,-266 3669,-266 3669,-266 2796,-297 2796,-297 2796,-297 2760,-297 2760,-297 2760,-297 2656.67,-275.15 2575.77,-258.04"/>
 <polygon fill="#4b5563" stroke="#4b5563" stroke-width="1.2" points="2575.87,-255.56 2568.51,-256.51 2574.85,-260.35 2575.87,-255.56"/>
 <text text-anchor="middle" x="2778" y="-300.6" font-family="Arial" font-size="8.00" fill="#374151">user_gpio</text>

docs/rib-interconnect.md

@@ -15,8 +15,10 @@ each boundary.
 
 ## APB4 and RIBP
 
-Self-owned configuration targets now sit on APB4. `apb4_periph` decodes the
-former `0x1000_0000` island through `axi42apb_periph`. RIBP remains only as the
+Self-owned configuration targets sit on the `apb4_periph` island at
+`0x1000_0000` and are decoded by `axi42apb4_periph`. Cluster and platform
+targets sit on the `apb4_system` island at `0x2000_0000` and are decoded by
+`axi42apb4_system`. Both islands use `apb4_if`. RIBP remains only as the
 MPW user-core compatibility contract.
 A master presents
 `valid`, `addr`, `wdata`, and `wstrb`; a slave completes the request with

docs/rtl-coding-style.md

@@ -143,10 +143,10 @@ The following rules are normative:
    or `_controller`, `_reg`, `_core`, `_if`, `_pkg`, `_formal`,
    `_formal_props`, and `_tb`.
 2. Name bus adapters with the repository's numeric `2` convention:
-   `rib2apb`, `rib2ram`, `axi42apb`, `axi4_word_bridge`, and `axi42ram`. New code
+   `rib2apb`, `rib2ram`, `axi42apb4_periph`, `axi42apb4_system`, `axi4_word_bridge`, and `axi42ram`. New code
    MUST NOT introduce another `_to_` spelling for the same conversion.
 3. Use function-qualified interface instances such as `cfg_apb4`,
-   `mem_axi4`, `dma_axi`, and `apb_periph`. Do not use `if0`, `bus0`,
+   `mem_axi4`, `dma_axi`, and `apb4_periph`. Do not use `if0`, `bus0`,
    `interface_a`, or names based only on declaration order.
 4. Keep standard protocol field names unchanged. AXI, APB, and RIB
    fields such as `valid`, `ready`, `wdata`, `wstrb`, `rdata`, `resp`, and

rtl/ip/peripheral/sysctrl_core.sv

@@ -46,10 +46,14 @@ module sysctrl_core (
   localparam sysctrl_offset_t PerfUserWaitHi = sysctrl_offset_t'(`APB4_SYSCTRL__PERF_USER_WAIT_HI);
   localparam sysctrl_offset_t PerfDmaWaitLo = sysctrl_offset_t'(`APB4_SYSCTRL__PERF_DMA_WAIT_LO);
   localparam sysctrl_offset_t PerfDmaWaitHi = sysctrl_offset_t'(`APB4_SYSCTRL__PERF_DMA_WAIT_HI);
-  localparam sysctrl_offset_t PerfApb4WaitLo = sysctrl_offset_t'(`APB4_SYSCTRL__PERF_APB4_WAIT_LO);
-  localparam sysctrl_offset_t PerfApb4WaitHi = sysctrl_offset_t'(`APB4_SYSCTRL__PERF_APB4_WAIT_HI);
-  localparam sysctrl_offset_t PerfApbWaitLo = sysctrl_offset_t'(`APB4_SYSCTRL__PERF_APB_WAIT_LO);
-  localparam sysctrl_offset_t PerfApbWaitHi = sysctrl_offset_t'(`APB4_SYSCTRL__PERF_APB_WAIT_HI);
+  localparam sysctrl_offset_t PerfApb4PeriphWaitLo =
+      sysctrl_offset_t'(`APB4_SYSCTRL__PERF_APB4_PERIPH_WAIT_LO);
+  localparam sysctrl_offset_t PerfApb4PeriphWaitHi =
+      sysctrl_offset_t'(`APB4_SYSCTRL__PERF_APB4_PERIPH_WAIT_HI);
+  localparam sysctrl_offset_t PerfApb4SystemWaitLo =
+      sysctrl_offset_t'(`APB4_SYSCTRL__PERF_APB4_SYSTEM_WAIT_LO);
+  localparam sysctrl_offset_t PerfApb4SystemWaitHi =
+      sysctrl_offset_t'(`APB4_SYSCTRL__PERF_APB4_SYSTEM_WAIT_HI);
   localparam sysctrl_offset_t PerfSdramWaitLo =
       sysctrl_offset_t'(`APB4_SYSCTRL__PERF_SDRAM_WAIT_LO);
   localparam sysctrl_offset_t PerfSdramWaitHi =
@@ -91,8 +95,8 @@ module sysctrl_core (
   logic [63:0] s_perf_mgmt_wait_d, s_perf_mgmt_wait_q;
   logic [63:0] s_perf_user_wait_d, s_perf_user_wait_q;
   logic [63:0] s_perf_dma_wait_d, s_perf_dma_wait_q;
-  logic [63:0] s_perf_apb4_wait_d, s_perf_apb4_wait_q;
-  logic [63:0] s_perf_apb_wait_d, s_perf_apb_wait_q;
+  logic [63:0] s_perf_apb4_periph_wait_d, s_perf_apb4_periph_wait_q;
+  logic [63:0] s_perf_apb4_system_wait_d, s_perf_apb4_system_wait_q;
   logic [63:0] s_perf_sdram_wait_d, s_perf_sdram_wait_q;
   logic [63:0] s_perf_psram_wait_d, s_perf_psram_wait_q;
   logic [63:0] s_perf_flash_wait_d, s_perf_flash_wait_q;
@@ -290,27 +294,27 @@ module sysctrl_core (
   assign s_perf_clear    = s_perf_write_en && write_data_i[`APB4_SYSCTRL__PERF_CTRL_CLEAR];
   assign s_perf_snapshot = s_perf_write_en && write_data_i[`APB4_SYSCTRL__PERF_CTRL_SNAPSHOT];
   always_comb begin
-    s_perf_en_d         = s_perf_en_q;
-    s_perf_mgmt_wait_d  = s_perf_mgmt_wait_q;
-    s_perf_user_wait_d  = s_perf_user_wait_q;
-    s_perf_dma_wait_d   = s_perf_dma_wait_q;
-    s_perf_apb4_wait_d  = s_perf_apb4_wait_q;
-    s_perf_apb_wait_d   = s_perf_apb_wait_q;
-    s_perf_sdram_wait_d = s_perf_sdram_wait_q;
-    s_perf_psram_wait_d = s_perf_psram_wait_q;
-    s_perf_flash_wait_d = s_perf_flash_wait_q;
+    s_perf_en_d               = s_perf_en_q;
+    s_perf_mgmt_wait_d        = s_perf_mgmt_wait_q;
+    s_perf_user_wait_d        = s_perf_user_wait_q;
+    s_perf_dma_wait_d         = s_perf_dma_wait_q;
+    s_perf_apb4_periph_wait_d = s_perf_apb4_periph_wait_q;
+    s_perf_apb4_system_wait_d = s_perf_apb4_system_wait_q;
+    s_perf_sdram_wait_d       = s_perf_sdram_wait_q;
+    s_perf_psram_wait_d       = s_perf_psram_wait_q;
+    s_perf_flash_wait_d       = s_perf_flash_wait_q;
     if (s_perf_write_en) begin
       s_perf_en_d = write_data_i[`APB4_SYSCTRL__PERF_CTRL_ENABLE];
     end
     if (s_perf_snapshot) begin
-      s_perf_mgmt_wait_d  = sysctrl.perf_mgmt_wait_i;
-      s_perf_user_wait_d  = sysctrl.perf_user_wait_i;
-      s_perf_dma_wait_d   = sysctrl.perf_dma_wait_i;
-      s_perf_apb4_wait_d  = sysctrl.perf_apb4_wait_i;
-      s_perf_apb_wait_d   = sysctrl.perf_apb_wait_i;
-      s_perf_sdram_wait_d = sysctrl.perf_sdram_wait_i;
-      s_perf_psram_wait_d = sysctrl.perf_psram_wait_i;
-      s_perf_flash_wait_d = sysctrl.perf_flash_wait_i;
+      s_perf_mgmt_wait_d        = sysctrl.perf_mgmt_wait_i;
+      s_perf_user_wait_d        = sysctrl.perf_user_wait_i;
+      s_perf_dma_wait_d         = sysctrl.perf_dma_wait_i;
+      s_perf_apb4_periph_wait_d = sysctrl.perf_apb4_periph_wait_i;
+      s_perf_apb4_system_wait_d = sysctrl.perf_apb4_system_wait_i;
+      s_perf_sdram_wait_d       = sysctrl.perf_sdram_wait_i;
+      s_perf_psram_wait_d       = sysctrl.perf_psram_wait_i;
+      s_perf_flash_wait_d       = sysctrl.perf_flash_wait_i;
     end
   end
 
@@ -340,77 +344,77 @@ module sysctrl_core (
 
   always_ff @(posedge clk_i or negedge rst_n_i) begin
     if (!rst_n_i) begin
-      s_sysctrl_coresel_q  <= '0;
-      s_user_reset_q       <= '1;
-      s_user_running_q     <= 1'b0;
-      s_user_draining_q    <= 1'b0;
-      s_user_config_err_q  <= 1'b0;
-      s_sysctrl_ipsel_q    <= '0;
-      s_pll_cfg_q          <= '0;
-      s_pll_req_valid_q    <= 1'b0;
-      s_pll_busy_q         <= 1'b0;
-      s_pll_err_q          <= 1'b0;
-      s_pll_err_reason_q   <= '0;
-      s_pll_active_sel_q   <= '0;
-      s_pll_active_valid_q <= 1'b0;
-      s_pll_safe_clk_q     <= 1'b1;
-      s_pll_lock_q         <= 1'b0;
-      s_fault_pending_q    <= 1'b0;
-      s_fault_write_q      <= 1'b0;
-      s_fault_reason_q     <= '0;
-      s_fault_detail_q     <= '0;
-      s_fault_addr_q       <= '0;
-      s_fault_count_q      <= '0;
-      s_fault_master_q     <= '0;
-      s_perf_en_q          <= 1'b0;
-      s_perf_mgmt_wait_q   <= '0;
-      s_perf_user_wait_q   <= '0;
-      s_perf_dma_wait_q    <= '0;
-      s_perf_apb4_wait_q   <= '0;
-      s_perf_apb_wait_q    <= '0;
-      s_perf_sdram_wait_q  <= '0;
-      s_perf_psram_wait_q  <= '0;
-      s_perf_flash_wait_q  <= '0;
-      s_test_done_q        <= 1'b0;
-      s_test_pass_q        <= 1'b0;
-      s_test_code_q        <= '0;
-      s_rtc_wake_seen_q    <= 1'b0;
+      s_sysctrl_coresel_q       <= '0;
+      s_user_reset_q            <= '1;
+      s_user_running_q          <= 1'b0;
+      s_user_draining_q         <= 1'b0;
+      s_user_config_err_q       <= 1'b0;
+      s_sysctrl_ipsel_q         <= '0;
+      s_pll_cfg_q               <= '0;
+      s_pll_req_valid_q         <= 1'b0;
+      s_pll_busy_q              <= 1'b0;
+      s_pll_err_q               <= 1'b0;
+      s_pll_err_reason_q        <= '0;
+      s_pll_active_sel_q        <= '0;
+      s_pll_active_valid_q      <= 1'b0;
+      s_pll_safe_clk_q          <= 1'b1;
+      s_pll_lock_q              <= 1'b0;
+      s_fault_pending_q         <= 1'b0;
+      s_fault_write_q           <= 1'b0;
+      s_fault_reason_q          <= '0;
+      s_fault_detail_q          <= '0;
+      s_fault_addr_q            <= '0;
+      s_fault_count_q           <= '0;
+      s_fault_master_q          <= '0;
+      s_perf_en_q               <= 1'b0;
+      s_perf_mgmt_wait_q        <= '0;
+      s_perf_user_wait_q        <= '0;
+      s_perf_dma_wait_q         <= '0;
+      s_perf_apb4_periph_wait_q <= '0;
+      s_perf_apb4_system_wait_q <= '0;
+      s_perf_sdram_wait_q       <= '0;
+      s_perf_psram_wait_q       <= '0;
+      s_perf_flash_wait_q       <= '0;
+      s_test_done_q             <= 1'b0;
+      s_test_pass_q             <= 1'b0;
+      s_test_code_q             <= '0;
+      s_rtc_wake_seen_q         <= 1'b0;
     end else begin
-      s_sysctrl_coresel_q  <= s_sysctrl_coresel_d;
-      s_user_reset_q       <= s_user_reset_d;
-      s_user_running_q     <= s_user_running_d;
-      s_user_draining_q    <= s_user_draining_d;
-      s_user_config_err_q  <= s_user_config_err_d;
-      s_sysctrl_ipsel_q    <= s_sysctrl_ipsel_d;
-      s_pll_cfg_q          <= s_pll_cfg_d;
-      s_pll_req_valid_q    <= s_pll_req_valid_d;
-      s_pll_busy_q         <= s_pll_busy_d;
-      s_pll_err_q          <= s_pll_err_d;
-      s_pll_err_reason_q   <= s_pll_err_reason_d;
-      s_pll_active_sel_q   <= s_pll_active_sel_d;
-      s_pll_active_valid_q <= s_pll_active_valid_d;
-      s_pll_safe_clk_q     <= s_pll_safe_clk_d;
-      s_pll_lock_q         <= s_pll_lock_d;
-      s_fault_pending_q    <= s_fault_pending_d;
-      s_fault_write_q      <= s_fault_write_d;
-      s_fault_reason_q     <= s_fault_reason_d;
-      s_fault_detail_q     <= s_fault_detail_d;
-      s_fault_addr_q       <= s_fault_addr_d;
-      s_fault_count_q      <= s_fault_count_d;
-      s_fault_master_q     <= s_fault_master_d;
-      s_perf_en_q          <= s_perf_en_d;
-      s_perf_mgmt_wait_q   <= s_perf_mgmt_wait_d;
-      s_perf_user_wait_q   <= s_perf_user_wait_d;
-      s_perf_dma_wait_q    <= s_perf_dma_wait_d;
-      s_perf_apb4_wait_q   <= s_perf_apb4_wait_d;
-      s_perf_apb_wait_q    <= s_perf_apb_wait_d;
-      s_perf_sdram_wait_q  <= s_perf_sdram_wait_d;
-      s_perf_psram_wait_q  <= s_perf_psram_wait_d;
-      s_perf_flash_wait_q  <= s_perf_flash_wait_d;
-      s_test_done_q        <= s_test_done_d;
-      s_test_pass_q        <= s_test_pass_d;
-      s_test_code_q        <= s_test_code_d;
-      s_rtc_wake_seen_q    <= s_rtc_wake_seen_d;
+      s_sysctrl_coresel_q       <= s_sysctrl_coresel_d;
+      s_user_reset_q            <= s_user_reset_d;
+      s_user_running_q          <= s_user_running_d;
+      s_user_draining_q         <= s_user_draining_d;
+      s_user_config_err_q       <= s_user_config_err_d;
+      s_sysctrl_ipsel_q         <= s_sysctrl_ipsel_d;
+      s_pll_cfg_q               <= s_pll_cfg_d;
+      s_pll_req_valid_q         <= s_pll_req_valid_d;
+      s_pll_busy_q              <= s_pll_busy_d;
+      s_pll_err_q               <= s_pll_err_d;
+      s_pll_err_reason_q        <= s_pll_err_reason_d;
+      s_pll_active_sel_q        <= s_pll_active_sel_d;
+      s_pll_active_valid_q      <= s_pll_active_valid_d;
+      s_pll_safe_clk_q          <= s_pll_safe_clk_d;
+      s_pll_lock_q              <= s_pll_lock_d;
+      s_fault_pending_q         <= s_fault_pending_d;
+      s_fault_write_q           <= s_fault_write_d;
+      s_fault_reason_q          <= s_fault_reason_d;
+      s_fault_detail_q          <= s_fault_detail_d;
+      s_fault_addr_q            <= s_fault_addr_d;
+      s_fault_count_q           <= s_fault_count_d;
+      s_fault_master_q          <= s_fault_master_d;
+      s_perf_en_q               <= s_perf_en_d;
+      s_perf_mgmt_wait_q        <= s_perf_mgmt_wait_d;
+      s_perf_user_wait_q        <= s_perf_user_wait_d;
+      s_perf_dma_wait_q         <= s_perf_dma_wait_d;
+      s_perf_apb4_periph_wait_q <= s_perf_apb4_periph_wait_d;
+      s_perf_apb4_system_wait_q <= s_perf_apb4_system_wait_d;
+      s_perf_sdram_wait_q       <= s_perf_sdram_wait_d;
+      s_perf_psram_wait_q       <= s_perf_psram_wait_d;
+      s_perf_flash_wait_q       <= s_perf_flash_wait_d;
+      s_test_done_q             <= s_test_done_d;
+      s_test_pass_q             <= s_test_pass_d;
+      s_test_code_q             <= s_test_code_d;
+      s_rtc_wake_seen_q         <= s_rtc_wake_seen_d;
     end
   end
 
@@ -456,10 +460,10 @@ module sysctrl_core (
       PerfUserWaitHi: read_data_o = s_perf_user_wait_q[63:32];
       PerfDmaWaitLo: read_data_o = s_perf_dma_wait_q[31:0];
       PerfDmaWaitHi: read_data_o = s_perf_dma_wait_q[63:32];
-      PerfApb4WaitLo: read_data_o = s_perf_apb4_wait_q[31:0];
-      PerfApb4WaitHi: read_data_o = s_perf_apb4_wait_q[63:32];
-      PerfApbWaitLo: read_data_o = s_perf_apb_wait_q[31:0];
-      PerfApbWaitHi: read_data_o = s_perf_apb_wait_q[63:32];
+      PerfApb4PeriphWaitLo: read_data_o = s_perf_apb4_periph_wait_q[31:0];
+      PerfApb4PeriphWaitHi: read_data_o = s_perf_apb4_periph_wait_q[63:32];
+      PerfApb4SystemWaitLo: read_data_o = s_perf_apb4_system_wait_q[31:0];
+      PerfApb4SystemWaitHi: read_data_o = s_perf_apb4_system_wait_q[63:32];
       PerfSdramWaitLo: read_data_o = s_perf_sdram_wait_q[31:0];
       PerfSdramWaitHi: read_data_o = s_perf_sdram_wait_q[63:32];
       PerfPsramWaitLo: read_data_o = s_perf_psram_wait_q[31:0];

rtl/ip/peripheral/sysctrl_define.svh

@@ -7,37 +7,37 @@
 `include "mmap_define.svh"
 
 // verilog_format: off -- preserve reviewed column alignment
-`define APB4_SYSCTRL__CORESEL              `SOC_SYSCTRL_CORESEL_OFFSET
-`define APB4_SYSCTRL__IPSEL                `SOC_SYSCTRL_IPSEL_OFFSET
-`define APB4_SYSCTRL__PLL_CFG              `SOC_SYSCTRL_PLL_CFG_OFFSET
-`define APB4_SYSCTRL__PLL_CMD              `SOC_SYSCTRL_PLL_CMD_OFFSET
-`define APB4_SYSCTRL__FAULT_STATUS         `SOC_SYSCTRL_FAULT_STATUS_OFFSET
-`define APB4_SYSCTRL__FAULT_ADDR           `SOC_SYSCTRL_FAULT_ADDR_OFFSET
-`define APB4_SYSCTRL__FAULT_COUNT          `SOC_SYSCTRL_FAULT_COUNT_OFFSET
-`define APB4_SYSCTRL__PLL_STATUS           `SOC_SYSCTRL_PLL_STATUS_OFFSET
-`define APB4_SYSCTRL__USER_CORE_RESET      `SOC_SYSCTRL_USER_CORE_RESET_OFFSET
-`define APB4_SYSCTRL__USER_CORE_STATUS     `SOC_SYSCTRL_USER_CORE_STATUS_OFFSET
-`define APB4_SYSCTRL__FAULT_MASTER         `SOC_SYSCTRL_FAULT_MASTER_OFFSET
-`define APB4_SYSCTRL__FAULT_DETAIL         `SOC_SYSCTRL_FAULT_DETAIL_OFFSET
-`define APB4_SYSCTRL__PERF_CTRL            `SOC_SYSCTRL_PERF_CTRL_OFFSET
-`define APB4_SYSCTRL__PERF_MGMT_WAIT_LO    `SOC_SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET
-`define APB4_SYSCTRL__PERF_MGMT_WAIT_HI    `SOC_SYSCTRL_PERF_MGMT_WAIT_HI_OFFSET
-`define APB4_SYSCTRL__PERF_USER_WAIT_LO    `SOC_SYSCTRL_PERF_USER_WAIT_LO_OFFSET
-`define APB4_SYSCTRL__PERF_USER_WAIT_HI    `SOC_SYSCTRL_PERF_USER_WAIT_HI_OFFSET
-`define APB4_SYSCTRL__PERF_DMA_WAIT_LO     `SOC_SYSCTRL_PERF_DMA_WAIT_LO_OFFSET
-`define APB4_SYSCTRL__PERF_DMA_WAIT_HI     `SOC_SYSCTRL_PERF_DMA_WAIT_HI_OFFSET
-`define APB4_SYSCTRL__PERF_APB4_WAIT_LO    `SOC_SYSCTRL_PERF_APB4_WAIT_LO_OFFSET
-`define APB4_SYSCTRL__PERF_APB4_WAIT_HI    `SOC_SYSCTRL_PERF_APB4_WAIT_HI_OFFSET
-`define APB4_SYSCTRL__PERF_APB_WAIT_LO     `SOC_SYSCTRL_PERF_APB_WAIT_LO_OFFSET
-`define APB4_SYSCTRL__PERF_APB_WAIT_HI     `SOC_SYSCTRL_PERF_APB_WAIT_HI_OFFSET
-`define APB4_SYSCTRL__PERF_SDRAM_WAIT_LO   `SOC_SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET
-`define APB4_SYSCTRL__PERF_SDRAM_WAIT_HI   `SOC_SYSCTRL_PERF_SDRAM_WAIT_HI_OFFSET
-`define APB4_SYSCTRL__PERF_PSRAM_WAIT_LO   `SOC_SYSCTRL_PERF_PSRAM_WAIT_LO_OFFSET
-`define APB4_SYSCTRL__PERF_PSRAM_WAIT_HI   `SOC_SYSCTRL_PERF_PSRAM_WAIT_HI_OFFSET
-`define APB4_SYSCTRL__PERF_FLASH_WAIT_LO   `SOC_SYSCTRL_PERF_FLASH_WAIT_LO_OFFSET
-`define APB4_SYSCTRL__PERF_FLASH_WAIT_HI   `SOC_SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET
-`define APB4_SYSCTRL__TEST_STATUS          `SOC_SYSCTRL_TEST_STATUS_OFFSET
-`define APB4_SYSCTRL__RTC_WAKE_STATUS      `SOC_SYSCTRL_RTC_WAKE_STATUS_OFFSET
+`define APB4_SYSCTRL__CORESEL                  `SOC_SYSCTRL_CORESEL_OFFSET
+`define APB4_SYSCTRL__IPSEL                    `SOC_SYSCTRL_IPSEL_OFFSET
+`define APB4_SYSCTRL__PLL_CFG                  `SOC_SYSCTRL_PLL_CFG_OFFSET
+`define APB4_SYSCTRL__PLL_CMD                  `SOC_SYSCTRL_PLL_CMD_OFFSET
+`define APB4_SYSCTRL__FAULT_STATUS             `SOC_SYSCTRL_FAULT_STATUS_OFFSET
+`define APB4_SYSCTRL__FAULT_ADDR               `SOC_SYSCTRL_FAULT_ADDR_OFFSET
+`define APB4_SYSCTRL__FAULT_COUNT              `SOC_SYSCTRL_FAULT_COUNT_OFFSET
+`define APB4_SYSCTRL__PLL_STATUS               `SOC_SYSCTRL_PLL_STATUS_OFFSET
+`define APB4_SYSCTRL__USER_CORE_RESET          `SOC_SYSCTRL_USER_CORE_RESET_OFFSET
+`define APB4_SYSCTRL__USER_CORE_STATUS         `SOC_SYSCTRL_USER_CORE_STATUS_OFFSET
+`define APB4_SYSCTRL__FAULT_MASTER             `SOC_SYSCTRL_FAULT_MASTER_OFFSET
+`define APB4_SYSCTRL__FAULT_DETAIL             `SOC_SYSCTRL_FAULT_DETAIL_OFFSET
+`define APB4_SYSCTRL__PERF_CTRL                `SOC_SYSCTRL_PERF_CTRL_OFFSET
+`define APB4_SYSCTRL__PERF_MGMT_WAIT_LO        `SOC_SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET
+`define APB4_SYSCTRL__PERF_MGMT_WAIT_HI        `SOC_SYSCTRL_PERF_MGMT_WAIT_HI_OFFSET
+`define APB4_SYSCTRL__PERF_USER_WAIT_LO        `SOC_SYSCTRL_PERF_USER_WAIT_LO_OFFSET
+`define APB4_SYSCTRL__PERF_USER_WAIT_HI        `SOC_SYSCTRL_PERF_USER_WAIT_HI_OFFSET
+`define APB4_SYSCTRL__PERF_DMA_WAIT_LO         `SOC_SYSCTRL_PERF_DMA_WAIT_LO_OFFSET
+`define APB4_SYSCTRL__PERF_DMA_WAIT_HI         `SOC_SYSCTRL_PERF_DMA_WAIT_HI_OFFSET
+`define APB4_SYSCTRL__PERF_APB4_PERIPH_WAIT_LO `SOC_SYSCTRL_PERF_APB4_PERIPH_WAIT_LO_OFFSET
+`define APB4_SYSCTRL__PERF_APB4_PERIPH_WAIT_HI `SOC_SYSCTRL_PERF_APB4_PERIPH_WAIT_HI_OFFSET
+`define APB4_SYSCTRL__PERF_APB4_SYSTEM_WAIT_LO `SOC_SYSCTRL_PERF_APB4_SYSTEM_WAIT_LO_OFFSET
+`define APB4_SYSCTRL__PERF_APB4_SYSTEM_WAIT_HI `SOC_SYSCTRL_PERF_APB4_SYSTEM_WAIT_HI_OFFSET
+`define APB4_SYSCTRL__PERF_SDRAM_WAIT_LO       `SOC_SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET
+`define APB4_SYSCTRL__PERF_SDRAM_WAIT_HI       `SOC_SYSCTRL_PERF_SDRAM_WAIT_HI_OFFSET
+`define APB4_SYSCTRL__PERF_PSRAM_WAIT_LO       `SOC_SYSCTRL_PERF_PSRAM_WAIT_LO_OFFSET
+`define APB4_SYSCTRL__PERF_PSRAM_WAIT_HI       `SOC_SYSCTRL_PERF_PSRAM_WAIT_HI_OFFSET
+`define APB4_SYSCTRL__PERF_FLASH_WAIT_LO       `SOC_SYSCTRL_PERF_FLASH_WAIT_LO_OFFSET
+`define APB4_SYSCTRL__PERF_FLASH_WAIT_HI       `SOC_SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET
+`define APB4_SYSCTRL__TEST_STATUS              `SOC_SYSCTRL_TEST_STATUS_OFFSET
+`define APB4_SYSCTRL__RTC_WAKE_STATUS          `SOC_SYSCTRL_RTC_WAKE_STATUS_OFFSET
 
 `define APB4_SYSCTRL__PLL_CMD_APPLY         0
 `define APB4_SYSCTRL__PLL_CMD_CLEAR_ERROR   1

rtl/ip/peripheral/sysctrl_if.sv

@@ -16,8 +16,8 @@ interface sysctrl_if ();
   logic [                   63:0] perf_mgmt_wait_i;
   logic [                   63:0] perf_user_wait_i;
   logic [                   63:0] perf_dma_wait_i;
-  logic [                   63:0] perf_apb4_wait_i;
-  logic [                   63:0] perf_apb_wait_i;
+  logic [                   63:0] perf_apb4_periph_wait_i;
+  logic [                   63:0] perf_apb4_system_wait_i;
   logic [                   63:0] perf_sdram_wait_i;
   logic [                   63:0] perf_psram_wait_i;
   logic [                   63:0] perf_flash_wait_i;
@@ -35,8 +35,8 @@ interface sysctrl_if ();
       input perf_mgmt_wait_i,
       input perf_user_wait_i,
       input perf_dma_wait_i,
-      input perf_apb4_wait_i,
-      input perf_apb_wait_i,
+      input perf_apb4_periph_wait_i,
+      input perf_apb4_system_wait_i,
       input perf_sdram_wait_i,
       input perf_psram_wait_i,
       input perf_flash_wait_i,

rtl/mini/address_map/generate_memory_map.py

@@ -12,7 +12,7 @@ from typing import Any
 
 
 MAX_ADDRESS = 1 << 32
-VALID_ROUTES = {"apb4", "axi4", "apb", "ram", "reserved"}
+VALID_ROUTES = {"apb4_periph", "apb4_system", "axi4", "ram", "reserved"}
 VALID_KINDS = {"active", "reserved"}
 VALID_USER_ACCESS = {"none", "ro", "rw"}
 VALID_BURST = {"incr1", "incr4", "incr16"}
@@ -160,7 +160,7 @@ def render_rtl(
             f"{range_expression(symbol, region['base'], region['end'])}",
         ]
     lines.append("")
-    for route in ("apb4", "axi4", "apb", "ram", "reserved"):
+    for route in ("apb4_periph", "apb4_system", "axi4", "ram", "reserved"):
         selected = [
             f"`SOC_ADDR_IS_{region['symbol']}(addr)"
             for region in regions
@@ -170,7 +170,7 @@ def render_rtl(
     legacy_rib_targets = [
         f"`SOC_ADDR_IS_{region['symbol']}(addr)"
         for region in regions
-        if region["route"] in {"apb4", "axi4"}
+        if region["route"] in {"apb4_periph", "axi4"}
     ]
     lines.append(
         f"`define SOC_ADDR_IS_RIB_LEGACY_TARGET(addr) ({join_or(legacy_rib_targets)})"

rtl/mini/address_map/memory_map.json

@@ -79,19 +79,19 @@
       "offset": "0x58"
     },
     {
-      "symbol": "PERF_APB4_WAIT_LO",
+      "symbol": "PERF_APB4_PERIPH_WAIT_LO",
       "offset": "0x5C"
     },
     {
-      "symbol": "PERF_APB4_WAIT_HI",
+      "symbol": "PERF_APB4_PERIPH_WAIT_HI",
       "offset": "0x60"
     },
     {
-      "symbol": "PERF_APB_WAIT_LO",
+      "symbol": "PERF_APB4_SYSTEM_WAIT_LO",
       "offset": "0x64"
     },
     {
-      "symbol": "PERF_APB_WAIT_HI",
+      "symbol": "PERF_APB4_SYSTEM_WAIT_HI",
       "offset": "0x68"
     },
     {
@@ -143,7 +143,7 @@
       "symbol": "APB4_GPIO",
       "base": "0x10000000",
       "size": "0x00001000",
-      "route": "apb4",
+      "route": "apb4_periph",
       "kind": "active",
       "public": true,
       "user_access": "rw"
@@ -152,7 +152,7 @@
       "symbol": "APB4_UART0",
       "base": "0x10001000",
       "size": "0x00001000",
-      "route": "apb4",
+      "route": "apb4_periph",
       "kind": "active",
       "public": true,
       "user_access": "rw"
@@ -161,7 +161,7 @@
       "symbol": "APB4_TIM0",
       "base": "0x10002000",
       "size": "0x00001000",
-      "route": "apb4",
+      "route": "apb4_periph",
       "kind": "active",
       "public": true,
       "user_access": "rw"
@@ -170,7 +170,7 @@
       "symbol": "APB4_TIM1",
       "base": "0x10003000",
       "size": "0x00001000",
-      "route": "apb4",
+      "route": "apb4_periph",
       "kind": "active",
       "public": true,
       "user_access": "rw"
@@ -179,7 +179,7 @@
       "symbol": "APB4_PSRAM",
       "base": "0x10004000",
       "size": "0x00001000",
-      "route": "apb4",
+      "route": "apb4_periph",
       "kind": "active",
       "public": true,
       "user_access": "none"
@@ -188,7 +188,7 @@
       "symbol": "APB4_SPISD",
       "base": "0x10005000",
       "size": "0x00001000",
-      "route": "apb4",
+      "route": "apb4_periph",
       "kind": "active",
       "public": true,
       "user_access": "rw"
@@ -197,7 +197,7 @@
       "symbol": "APB4_I2C0",
       "base": "0x10006000",
       "size": "0x00001000",
-      "route": "apb4",
+      "route": "apb4_periph",
       "kind": "active",
       "public": true,
       "user_access": "rw"
@@ -206,7 +206,7 @@
       "symbol": "APB4_I2S",
       "base": "0x10007000",
       "size": "0x00001000",
-      "route": "apb4",
+      "route": "apb4_periph",
       "kind": "active",
       "public": true,
       "user_access": "rw"
@@ -215,7 +215,7 @@
       "symbol": "APB4_WS2812",
       "base": "0x10008000",
       "size": "0x00001000",
-      "route": "apb4",
+      "route": "apb4_periph",
       "kind": "active",
       "public": true,
       "user_access": "rw"
@@ -224,7 +224,7 @@
       "symbol": "APB4_XPI",
       "base": "0x10009000",
       "size": "0x00001000",
-      "route": "apb4",
+      "route": "apb4_periph",
       "kind": "active",
       "public": true,
       "user_access": "none"
@@ -233,7 +233,7 @@
       "symbol": "APB4_DMA",
       "base": "0x1000A000",
       "size": "0x00001000",
-      "route": "apb4",
+      "route": "apb4_periph",
       "kind": "active",
       "public": true,
       "user_access": "none"
@@ -242,7 +242,7 @@
       "symbol": "APB4_SYSCTRL",
       "base": "0x1000B000",
       "size": "0x00001000",
-      "route": "apb4",
+      "route": "apb4_periph",
       "kind": "active",
       "public": true,
       "user_access": "none"
@@ -251,7 +251,7 @@
       "symbol": "APB4_CLINT",
       "base": "0x10020000",
       "size": "0x00010000",
-      "route": "apb4",
+      "route": "apb4_periph",
       "kind": "active",
       "public": true,
       "user_access": "none"
@@ -260,7 +260,7 @@
       "symbol": "APB4_SDRAM",
       "base": "0x1000D000",
       "size": "0x00001000",
-      "route": "apb4",
+      "route": "apb4_periph",
       "kind": "active",
       "public": true,
       "user_access": "none"
@@ -269,7 +269,7 @@
       "symbol": "APB4_DVP",
       "base": "0x1000E000",
       "size": "0x00001000",
-      "route": "apb4",
+      "route": "apb4_periph",
       "kind": "active",
       "public": true,
       "user_access": "rw"
@@ -296,7 +296,7 @@
       "symbol": "APB4_I2C1",
       "base": "0x10011000",
       "size": "0x00001000",
-      "route": "apb4",
+      "route": "apb4_periph",
       "kind": "active",
       "public": true,
       "user_access": "rw"
@@ -323,79 +323,79 @@
       "symbol": "APB4_GPIO_ADMIN",
       "base": "0x10014000",
       "size": "0x00001000",
-      "route": "apb4",
+      "route": "apb4_periph",
       "kind": "active",
       "public": true,
       "user_access": "none"
     },
     {
-      "symbol": "APB_ARCHINFO",
+      "symbol": "APB4_ARCHINFO",
       "base": "0x20000000",
       "size": "0x00001000",
-      "route": "apb",
+      "route": "apb4_system",
       "kind": "active",
       "public": true,
       "user_access": "ro"
     },
     {
-      "symbol": "APB_RNG",
+      "symbol": "APB4_RNG",
       "base": "0x20001000",
       "size": "0x00001000",
-      "route": "apb",
+      "route": "apb4_system",
       "kind": "active",
       "public": true,
       "user_access": "none"
     },
     {
-      "symbol": "APB_PWM",
+      "symbol": "APB4_PWM",
       "base": "0x20002000",
       "size": "0x00001000",
-      "route": "apb",
+      "route": "apb4_system",
       "kind": "active",
       "public": true,
       "user_access": "rw"
     },
     {
-      "symbol": "APB_PS2",
+      "symbol": "APB4_PS2",
       "base": "0x20003000",
       "size": "0x00001000",
-      "route": "apb",
+      "route": "apb4_system",
       "kind": "active",
       "public": true,
       "user_access": "rw"
     },
     {
-      "symbol": "APB_RTC",
+      "symbol": "APB4_RTC",
       "base": "0x20004000",
       "size": "0x00001000",
-      "route": "apb",
+      "route": "apb4_system",
       "kind": "active",
       "public": true,
       "user_access": "rw"
     },
     {
-      "symbol": "APB_WDG",
+      "symbol": "APB4_WDG",
       "base": "0x20005000",
       "size": "0x00001000",
-      "route": "apb",
+      "route": "apb4_system",
       "kind": "active",
       "public": true,
       "user_access": "none"
     },
     {
-      "symbol": "APB_CRC",
+      "symbol": "APB4_CRC",
       "base": "0x20006000",
       "size": "0x00001000",
-      "route": "apb",
+      "route": "apb4_system",
       "kind": "active",
       "public": true,
       "user_access": "rw"
     },
     {
-      "symbol": "APB_USER_IP",
+      "symbol": "APB4_USER_IP",
       "base": "0x20007000",
       "size": "0x00001000",
-      "route": "apb",
+      "route": "apb4_system",
       "kind": "active",
       "public": true,
       "user_access": "rw"

rtl/mini/filelist/top.fl

@@ -8,8 +8,8 @@
 /top/axi4_error_slave.sv
 /top/rib2axi4.sv
 /top/ahbl2axi4.sv
-/top/axi42apb.sv
-/top/axi42apb_periph.sv
+/top/axi42apb4_system.sv
+/top/axi42apb4_periph.sv
 /top/axi4_word_bridge.sv
 /top/axi42ram.sv
 /top/rib_error_slave.sv

rtl/mini/formal/bus_formal.sv

@@ -197,32 +197,32 @@ module bus_formal_design (
   );
 
   rib_bus u_dut (
-      .clk_i            (clk_i),
-      .rst_n_i          (rst_n_i),
-      .mgmt_rib         (mgmt_rib),
-      .user_rib         (user_rib),
-      .dma_rib          (dma_rib),
-      .user_bus_enable_i(1'b1),
-      .user_bus_idle_o  (user_idle),
-      .rib              (rib),
-      .apb_rib          (apb_rib),
-      .perf_enable_i    (1'b0),
-      .perf_clear_i     (1'b0),
-      .fault_valid_o    (fault_valid),
-      .fault_addr_o     (fault_addr),
-      .fault_wstrb_o    (fault_wstrb),
-      .fault_reserved_o (fault_reserved),
-      .fault_access_o   (fault_access),
-      .fault_master_o   (fault_master),
-      .fault_code_o     (fault_code),
-      .perf_mgmt_wait_o (),
-      .perf_user_wait_o (),
-      .perf_dma_wait_o  (),
-      .perf_apb4_wait_o (),
-      .perf_apb_wait_o  (),
-      .perf_sdram_wait_o(),
-      .perf_psram_wait_o(),
-      .perf_flash_wait_o()
+      .clk_i                  (clk_i),
+      .rst_n_i                (rst_n_i),
+      .mgmt_rib               (mgmt_rib),
+      .user_rib               (user_rib),
+      .dma_rib                (dma_rib),
+      .user_bus_enable_i      (1'b1),
+      .user_bus_idle_o        (user_idle),
+      .rib                    (rib),
+      .apb_rib                (apb_rib),
+      .perf_enable_i          (1'b0),
+      .perf_clear_i           (1'b0),
+      .fault_valid_o          (fault_valid),
+      .fault_addr_o           (fault_addr),
+      .fault_wstrb_o          (fault_wstrb),
+      .fault_reserved_o       (fault_reserved),
+      .fault_access_o         (fault_access),
+      .fault_master_o         (fault_master),
+      .fault_code_o           (fault_code),
+      .perf_mgmt_wait_o       (),
+      .perf_user_wait_o       (),
+      .perf_dma_wait_o        (),
+      .perf_apb4_periph_wait_o(),
+      .perf_apb4_system_wait_o(),
+      .perf_sdram_wait_o      (),
+      .perf_psram_wait_o      (),
+      .perf_flash_wait_o      ()
   );
 
   assign arb_locked   = u_dut.s_mstr_lock_q;

rtl/mini/formal/sysctrl_formal.sv

@@ -76,8 +76,8 @@ module sysctrl_formal_design (
   assign sysctrl.perf_mgmt_wait_i = '0;
   assign sysctrl.perf_user_wait_i = '0;
   assign sysctrl.perf_dma_wait_i = '0;
-  assign sysctrl.perf_apb4_wait_i = '0;
-  assign sysctrl.perf_apb_wait_i = '0;
+  assign sysctrl.perf_apb4_periph_wait_i = '0;
+  assign sysctrl.perf_apb4_system_wait_i = '0;
   assign sysctrl.perf_sdram_wait_i = '0;
   assign sysctrl.perf_psram_wait_i = '0;
   assign sysctrl.perf_flash_wait_i = '0;

rtl/mini/integration/README.md

@@ -3,35 +3,36 @@
 `soc_topology.json` is the source of truth for internal Mini SoC integration
 that is not part of the software address-map ABI or the package pad map.
 
-The topology generator validates APB4 and APB target ownership against
+The topology generator validates APB4 island ownership against
 `../address_map/memory_map.json` and emits generated SystemVerilog include
-files for `apb4_periph.sv`, `apb4_system.sv`, `axi42apb.sv`, and
-`retrosoc.sv`. The APB4 platform subsystem is `apb4_system`, instantiated as
-`u_apb4_system`; its AXI4 configuration port is wired by generated
-`soc_apb4_system_fabric.svh`. `apb4_periph` remains the APB4 peripheral
-container. Generated fabric links are explicit 32-bit AXI4 interfaces.
+files for `apb4_periph.sv`, `apb4_system.sv`, `axi42apb4_periph.sv`,
+`axi42apb4_system.sv`, and `retrosoc.sv`. The two APB4 islands share one
+decoder template. `apb4_system` is instantiated as `u_apb4_system`; its AXI4
+configuration port is wired by generated `apb4_system_fabric.svh`.
+`apb4_periph` remains the self-owned APB4 peripheral container. Generated fabric links are explicit 32-bit AXI4 interfaces.
 Interface arrays are confined to the AXI4 bus implementation and flattened by
 the existing synthesis/export flow before FPGA or netlist simulation.
 
-The `apb4_targets` list uses stable response slots for the former RIBP island
-at `0x1000_0000`. Every active APB4 memory-map region must appear exactly
-once. Disabled targets keep their slot and interface declaration but cannot
-own an address region. This list stays separate from `apb_targets`, which
-owns the `0x2000_0000` `apb4_system` island.
+The `apb4_periph_targets` list uses stable response slots for the former
+RIBP island at `0x1000_0000`. Every active `apb4_periph` memory-map region
+must appear exactly once. Disabled targets keep their slot and interface
+declaration but cannot own an address region. This list stays separate from
+`apb4_system_targets`, which owns the `0x2000_0000` `apb4_system` island.
 
 Each `gpio_alt_functions` entry defines both alternate modes for one GPIO pin.
 `inputs` are driven from the selected GPIO input, and `do` and `oe` define the
 peripheral output path. Values are restricted to scalar signal references and
 one-bit constants so malformed expressions are rejected before RTL generation.
 
-The `apb_targets` list defines the stable APB response slot, timed/pure APB
-interface names, and corresponding active APB address-map region. APB slots are
-contiguous from zero. The user-IP target is part of the fixed platform
-integration and its presence is checked against the canonical memory map.
+The `apb4_system_targets` list defines the stable APB4 response slot,
+timed/pure APB4 interface names, and corresponding active `apb4_system`
+address-map region. Slots are contiguous from zero. The user-IP target is
+part of the fixed platform integration and its presence is checked against
+the canonical memory map.
 
 `irq_vector_width`, `irq_groups`, and `interrupts` define the complete core
-interrupt topology. `apb4` and `apb` group entries declare the wrapper output
-width and the associated `retrosoc.sv` signal. Every group bit must be present
+interrupt topology. `apb4_periph` and `apb4_system` group entries declare the
+wrapper output width and the associated `retrosoc.sv` signal. Every group bit must be present
 exactly once, each core-vector bit must have one source, and sources are limited
 to scalar signal references or one-bit constants. The generator emits the two
 wrapper bindings, the core-vector wiring, and simulation-only assertions.

rtl/mini/integration/generate_soc_topology.py

@@ -16,30 +16,30 @@ from typing import Any
 SV_IDENTIFIER_RE = re.compile(r"[A-Za-z_][A-Za-z0-9_]*$")
 SV_REFERENCE_RE = re.compile(r"[A-Za-z_][A-Za-z0-9_]*(?:\.[A-Za-z_][A-Za-z0-9_]*)*(?:\[[0-9]+\])?$")
 SV_CONSTANT_RE = re.compile(r"(?:1'[bB][01]|'[01])$")
-FABRIC_LINK_NAMES = ("mgmt", "user", "dma", "cfg", "apb")
+FABRIC_LINK_NAMES = ("mgmt", "user", "dma", "cfg", "system")
 FABRIC_PROTOCOLS = {name: "axi4" for name in FABRIC_LINK_NAMES}
-IRQ_GROUP_NAMES = ("apb4", "apb")
+IRQ_GROUP_NAMES = ("apb4_periph", "apb4_system")
 IRQ_VECTOR_WIDTH = 32
 COMPATIBILITY_IRQ_BINDINGS = (
-    ("clint_software", "apb4", 0, 0, "u_clint_if.software_irq_o[0]"),
-    ("clint_timer", "apb4", 1, 1, "u_clint_if.timer_irq_o[0]"),
-    ("uart0", "apb4", 2, 2, "uart.irq_o"),
-    ("timer0", "apb4", 3, 3, "s_tim0_irq"),
-    ("timer1", "apb4", 4, 4, "s_tim1_irq"),
-    ("psram", "apb4", 5, 5, "psram.irq_o"),
-    ("spisd", "apb4", 6, 6, "spisd.irq_o"),
-    ("i2c0", "apb4", 7, 7, "i2c0.irq_o"),
-    ("i2s", "apb4", 8, 8, "i2s.irq_o"),
-    ("xpi", "apb4", 9, 9, "xpi.irq_o"),
-    ("pwm", "apb", 0, 11, "pwm.irq_o"),
-    ("ps2", "apb", 1, 12, "ps2.irq_o"),
-    ("rtc", "apb", 2, 13, "u_rtc_if.irq_o"),
-    ("watchdog_early_warning", "apb", 3, 14, "u_wdg_if.irq_o"),
-    ("rng", "apb", 4, 16, "s_rng_irq"),
-    ("ws2812", "apb4", 10, 17, "ws2812.irq_o"),
-    ("gpio", "apb4", 11, 18, "gpio.irq_o"),
-    ("i2c1", "apb4", 12, 19, "i2c1.irq_o"),
-    ("dvp", "apb4", 13, 15, "s_dvp_irq"),
+    ("clint_software", "apb4_periph", 0, 0, "u_clint_if.software_irq_o[0]"),
+    ("clint_timer", "apb4_periph", 1, 1, "u_clint_if.timer_irq_o[0]"),
+    ("uart0", "apb4_periph", 2, 2, "uart.irq_o"),
+    ("timer0", "apb4_periph", 3, 3, "s_tim0_irq"),
+    ("timer1", "apb4_periph", 4, 4, "s_tim1_irq"),
+    ("psram", "apb4_periph", 5, 5, "psram.irq_o"),
+    ("spisd", "apb4_periph", 6, 6, "spisd.irq_o"),
+    ("i2c0", "apb4_periph", 7, 7, "i2c0.irq_o"),
+    ("i2s", "apb4_periph", 8, 8, "i2s.irq_o"),
+    ("xpi", "apb4_periph", 9, 9, "xpi.irq_o"),
+    ("pwm", "apb4_system", 0, 11, "pwm.irq_o"),
+    ("ps2", "apb4_system", 1, 12, "ps2.irq_o"),
+    ("rtc", "apb4_system", 2, 13, "u_rtc_if.irq_o"),
+    ("watchdog_early_warning", "apb4_system", 3, 14, "u_wdg_if.irq_o"),
+    ("rng", "apb4_system", 4, 16, "s_rng_irq"),
+    ("ws2812", "apb4_periph", 10, 17, "ws2812.irq_o"),
+    ("gpio", "apb4_periph", 11, 18, "gpio.irq_o"),
+    ("i2c1", "apb4_periph", 12, 19, "i2c1.irq_o"),
+    ("dvp", "apb4_periph", 13, 15, "s_dvp_irq"),
 )
 
 
@@ -171,11 +171,14 @@ def parse_regions(value: Any, field: str) -> tuple[str, ...]:
     return regions
 
 
-def parse_apb4_targets(
-    value: Any, memory_regions: dict[str, dict[str, Any]]
+def parse_apb4_island_targets(
+    value: Any,
+    memory_regions: dict[str, dict[str, Any]],
+    field: str,
+    expected_route: str,
 ) -> list[ApbTarget]:
     if not isinstance(value, list) or not value:
-        raise ValueError("apb4_targets must be a non-empty list")
+        raise ValueError(f"{field} must be a non-empty list")
     targets: list[ApbTarget] = []
     claimed_regions: set[str] = set()
     names: set[str] = set()
@@ -183,57 +186,58 @@ def parse_apb4_targets(
     pure_interfaces: set[str] = set()
     slots: set[int] = set()
     for index, entry in enumerate(value):
-        target = require_object(entry, f"apb4_targets[{index}]")
+        target = require_object(entry, f"{field}[{index}]")
         slot = target.get("slot")
         if not isinstance(slot, int) or slot < 0:
-            raise ValueError(f"apb4_targets[{index}].slot must be a non-negative integer")
-        name = require_identifier(target.get("name"), f"apb4_targets[{index}].name")
+            raise ValueError(f"{field}[{index}].slot must be a non-negative integer")
+        name = require_identifier(target.get("name"), f"{field}[{index}].name")
         timed_interface = require_identifier(
-            target.get("timed_interface"), f"apb4_targets[{index}].timed_interface"
+            target.get("timed_interface"), f"{field}[{index}].timed_interface"
         )
         pure_interface = require_identifier(
-            target.get("pure_interface"), f"apb4_targets[{index}].pure_interface"
+            target.get("pure_interface"), f"{field}[{index}].pure_interface"
         )
         disabled = target.get("disabled", False)
         if not isinstance(disabled, bool):
-            raise ValueError(f"apb4_targets[{index}].disabled must be boolean")
+            raise ValueError(f"{field}[{index}].disabled must be boolean")
         if disabled:
             if "regions" in target or "region" in target:
-                raise ValueError(f"apb4_targets[{index}] is disabled but declares regions")
+                raise ValueError(f"{field}[{index}] is disabled but declares regions")
             regions: tuple[str, ...] = ()
         elif "regions" in target:
-            regions = parse_regions(target.get("regions"), f"apb4_targets[{index}].regions")
+            regions = parse_regions(target.get("regions"), f"{field}[{index}].regions")
         else:
             region_name = require_identifier(
-                target.get("region"), f"apb4_targets[{index}].region"
+                target.get("region"), f"{field}[{index}].region"
             )
             regions = (region_name,)
         for region_name in regions:
             region = memory_regions.get(region_name)
             if region is None:
                 raise ValueError(
-                    f"apb4_targets[{index}] references unknown region {region_name}"
+                    f"{field}[{index}] references unknown region {region_name}"
                 )
-            if region.get("route") != "apb4" or region.get("kind") != "active":
+            if region.get("route") != expected_route or region.get("kind") != "active":
                 raise ValueError(
-                    f"apb4_targets[{index}] region {region_name} is not an active APB4 region"
+                    f"{field}[{index}] region {region_name} is not an active "
+                    f"{expected_route} region"
                 )
             if region_name in claimed_regions:
-                raise ValueError(f"APB4 region {region_name} has multiple targets")
+                raise ValueError(f"{expected_route} region {region_name} has multiple targets")
             claimed_regions.add(region_name)
         external = target.get("external", False)
         if not isinstance(external, bool):
-            raise ValueError(f"apb4_targets[{index}].external must be boolean")
+            raise ValueError(f"{field}[{index}].external must be boolean")
         if external and disabled:
-            raise ValueError(f"apb4_targets[{index}] cannot be both external and disabled")
+            raise ValueError(f"{field}[{index}] cannot be both external and disabled")
         if name in names:
-            raise ValueError(f"APB4 target name {name} is duplicated")
+            raise ValueError(f"{field} target name {name} is duplicated")
         if timed_interface in timed_interfaces:
-            raise ValueError(f"APB4 timed interface {timed_interface} is duplicated")
+            raise ValueError(f"{field} timed interface {timed_interface} is duplicated")
         if pure_interface in pure_interfaces:
-            raise ValueError(f"APB4 pure interface {pure_interface} is duplicated")
+            raise ValueError(f"{field} pure interface {pure_interface} is duplicated")
         if slot in slots:
-            raise ValueError(f"APB4 target slot {slot} is duplicated")
+            raise ValueError(f"{field} target slot {slot} is duplicated")
         names.add(name)
         timed_interfaces.add(timed_interface)
         pure_interfaces.add(pure_interface)
@@ -244,83 +248,12 @@ def parse_apb4_targets(
 
     ordered = sorted(targets, key=lambda item: item.slot)
     if [target.slot for target in ordered] != list(range(len(ordered))):
-        raise ValueError("APB4 target slots must be contiguous from zero")
-    active_apb4_regions = {
-        symbol
-        for symbol, region in memory_regions.items()
-        if region.get("route") == "apb4" and region.get("kind") == "active"
-    }
-    if claimed_regions != active_apb4_regions:
-        missing = sorted(active_apb4_regions - claimed_regions)
-        extra = sorted(claimed_regions - active_apb4_regions)
-        details: list[str] = []
-        if missing:
-            details.append(f"missing {', '.join(missing)}")
-        if extra:
-            details.append(f"extra {', '.join(extra)}")
-        raise ValueError(
-            f"APB4 target regions do not cover the memory map ({'; '.join(details)})"
-        )
-    return ordered
-
-
-def parse_apb_targets(value: Any, memory_regions: dict[str, dict[str, Any]]) -> list[ApbTarget]:
-    if not isinstance(value, list) or not value:
-        raise ValueError("apb_targets must be a non-empty list")
-    targets: list[ApbTarget] = []
-    names: set[str] = set()
-    timed_interfaces: set[str] = set()
-    pure_interfaces: set[str] = set()
-    regions: set[str] = set()
-    slots: set[int] = set()
-    for index, entry in enumerate(value):
-        target = require_object(entry, f"apb_targets[{index}]")
-        slot = target.get("slot")
-        if not isinstance(slot, int) or slot < 0:
-            raise ValueError(f"apb_targets[{index}].slot must be a non-negative integer")
-        name = require_identifier(target.get("name"), f"apb_targets[{index}].name")
-        timed_interface = require_identifier(
-            target.get("timed_interface"), f"apb_targets[{index}].timed_interface"
-        )
-        pure_interface = require_identifier(
-            target.get("pure_interface"), f"apb_targets[{index}].pure_interface"
-        )
-        region_name = require_identifier(target.get("region"), f"apb_targets[{index}].region")
-        region = memory_regions.get(region_name)
-        if region is None:
-            raise ValueError(f"apb_targets[{index}] references unknown region {region_name}")
-        if region.get("route") != "apb" or region.get("kind") != "active":
-            raise ValueError(
-                f"apb_targets[{index}] region {region_name} is not an active APB region"
-            )
-        if name in names:
-            raise ValueError(f"APB target name {name} is duplicated")
-        if timed_interface in timed_interfaces:
-            raise ValueError(f"APB timed interface {timed_interface} is duplicated")
-        if pure_interface in pure_interfaces:
-            raise ValueError(f"APB pure interface {pure_interface} is duplicated")
-        if region_name in regions:
-            raise ValueError(f"APB region {region_name} has multiple targets")
-        if slot in slots:
-            raise ValueError(f"APB target slot {slot} is duplicated")
-        names.add(name)
-        timed_interfaces.add(timed_interface)
-        pure_interfaces.add(pure_interface)
-        regions.add(region_name)
-        slots.add(slot)
-        targets.append(
-            ApbTarget(slot, name, timed_interface, pure_interface, (region_name,))
-        )
-
-    ordered = sorted(targets, key=lambda item: item.slot)
-    if [target.slot for target in ordered] != list(range(len(ordered))):
-        raise ValueError("enabled APB target slots must be contiguous from zero")
+        raise ValueError(f"{field} slots must be contiguous from zero")
     active_regions = {
         symbol
         for symbol, region in memory_regions.items()
-        if region.get("route") == "apb" and region.get("kind") == "active"
+        if region.get("route") == expected_route and region.get("kind") == "active"
     }
-    claimed_regions = {region for target in ordered for region in target.regions}
     if claimed_regions != active_regions:
         missing = sorted(active_regions - claimed_regions)
         extra = sorted(claimed_regions - active_regions)
@@ -329,7 +262,9 @@ def parse_apb_targets(value: Any, memory_regions: dict[str, dict[str, Any]]) ->
             details.append(f"missing {', '.join(missing)}")
         if extra:
             details.append(f"extra {', '.join(extra)}")
-        raise ValueError(f"APB target regions do not cover the memory map ({'; '.join(details)})")
+        raise ValueError(
+            f"{field} regions do not cover the memory map ({'; '.join(details)})"
+        )
     return ordered
 
 
@@ -534,8 +469,18 @@ def read_topology(
     interrupts = parse_interrupts(document.get("interrupts"), irq_groups, irq_vector_width)
     validate_compatibility_irq_bindings(interrupts)
     return (
-        parse_apb4_targets(document.get("apb4_targets"), memory_regions),
-        parse_apb_targets(document.get("apb_targets"), memory_regions),
+        parse_apb4_island_targets(
+            document.get("apb4_periph_targets"),
+            memory_regions,
+            "apb4_periph_targets",
+            "apb4_periph",
+        ),
+        parse_apb4_island_targets(
+            document.get("apb4_system_targets"),
+            memory_regions,
+            "apb4_system_targets",
+            "apb4_system",
+        ),
         parse_fabric_links(document.get("fabric_links")),
         parse_gpio_functions(document.get("gpio_alt_functions"), gpio_pins),
         irq_vector_width,
@@ -558,7 +503,7 @@ def render_apb_bridges(targets: list[ApbTarget]) -> str:
     for target in targets:
         lines.extend(
             [
-                f"  apb4_if_bridge u_{target.name}_apb_bridge (",
+                f"  apb4_if_bridge u_{target.name}_apb4_bridge (",
                 f"      .apb_pure({target.pure_interface}),",
                 f"      .timed   ({target.timed_interface})",
                 "  );",
@@ -689,7 +634,7 @@ def render_bus_fabric_connections(links: list[FabricLink]) -> str:
         "user": "user_axi4",
         "dma": "dma_axi4",
         "cfg": "cfg_axi4",
-        "apb": "apb_axi4",
+        "system": "system_axi4",
     }
     interfaces = {link.name: link.interface for link in links}
     lines = ["// Generated by rtl/mini/integration/generate_soc_topology.py; do not edit."]
@@ -827,8 +772,8 @@ def render_irq_sva(vector_width: int, groups: list[IrqGroup], interrupts: list[I
 
 def generate(topology_path: Path, memory_map_path: Path, output_dir: Path) -> None:
     (
-        targets,
-        apb_targets,
+        periph_targets,
+        system_targets,
         fabric_links,
         gpio_functions,
         irq_vector_width,
@@ -836,22 +781,19 @@ def generate(topology_path: Path, memory_map_path: Path, output_dir: Path) -> No
         interrupts,
     ) = read_topology(topology_path, memory_map_path)
     rtl_dir = output_dir / "rtl"
-    atomic_write(rtl_dir / "apb4_periph_interfaces.svh", render_apb_interfaces(targets))
-    atomic_write(rtl_dir / "apb4_periph_bridges.svh", render_apb_bridges(targets))
-    atomic_write(rtl_dir / "apb4_periph_ports.svh", render_apb_ports(targets))
-    atomic_write(rtl_dir / "apb4_periph_connections.svh", render_apb_connections(targets))
-    atomic_write(rtl_dir / "apb4_periph_declarations.svh", render_apb_declarations(targets))
-    atomic_write(rtl_dir / "apb4_periph_request_routes.svh", render_apb_request_routes(targets))
-    atomic_write(rtl_dir / "apb4_periph_select_routes.svh", render_apb_select_routes(targets))
-    atomic_write(rtl_dir / "apb4_periph_response_mux.svh", render_apb_response_mux(targets))
-    atomic_write(rtl_dir / "soc_apb_interfaces.svh", render_apb_interfaces(apb_targets))
-    atomic_write(rtl_dir / "soc_apb_bridges.svh", render_apb_bridges(apb_targets))
-    atomic_write(rtl_dir / "soc_apb_ports.svh", render_apb_ports(apb_targets))
-    atomic_write(rtl_dir / "soc_apb_connections.svh", render_apb_connections(apb_targets))
-    atomic_write(rtl_dir / "soc_apb_declarations.svh", render_apb_declarations(apb_targets))
-    atomic_write(rtl_dir / "soc_apb_request_routes.svh", render_apb_request_routes(apb_targets))
-    atomic_write(rtl_dir / "soc_apb_select_routes.svh", render_apb_select_routes(apb_targets))
-    atomic_write(rtl_dir / "soc_apb_response_mux.svh", render_apb_response_mux(apb_targets))
+
+    def write_island(prefix: str, targets: list[ApbTarget]) -> None:
+        atomic_write(rtl_dir / f"{prefix}_interfaces.svh", render_apb_interfaces(targets))
+        atomic_write(rtl_dir / f"{prefix}_bridges.svh", render_apb_bridges(targets))
+        atomic_write(rtl_dir / f"{prefix}_ports.svh", render_apb_ports(targets))
+        atomic_write(rtl_dir / f"{prefix}_connections.svh", render_apb_connections(targets))
+        atomic_write(rtl_dir / f"{prefix}_declarations.svh", render_apb_declarations(targets))
+        atomic_write(rtl_dir / f"{prefix}_request_routes.svh", render_apb_request_routes(targets))
+        atomic_write(rtl_dir / f"{prefix}_select_routes.svh", render_apb_select_routes(targets))
+        atomic_write(rtl_dir / f"{prefix}_response_mux.svh", render_apb_response_mux(targets))
+
+    write_island("apb4_periph", periph_targets)
+    write_island("apb4_system", system_targets)
     atomic_write(rtl_dir / "soc_fabric_interfaces.svh", render_fabric_interfaces(fabric_links))
     atomic_write(
         rtl_dir / "soc_mgmt_core_wrapper_fabric.svh",
@@ -868,8 +810,8 @@ def generate(topology_path: Path, memory_map_path: Path, output_dir: Path) -> No
         + render_fabric_connection(fabric_links, "dma", "dma_axi4"),
     )
     atomic_write(
-        rtl_dir / "soc_apb4_system_fabric.svh",
-        render_fabric_connection(fabric_links, "apb", "axi4"),
+        rtl_dir / "apb4_system_fabric.svh",
+        render_fabric_connection(fabric_links, "system", "axi4"),
     )
     atomic_write(rtl_dir / "soc_gpio_alt_bindings.svh", render_gpio_bindings(gpio_functions))
     atomic_write(
@@ -877,7 +819,7 @@ def generate(topology_path: Path, memory_map_path: Path, output_dir: Path) -> No
         render_irq_config(irq_vector_width, irq_groups, interrupts),
     )
     for group in irq_groups:
-        filename = f"soc_{group.name}_irq_bindings.svh"
+        filename = f"{group.name}_irq_bindings.svh"
         atomic_write(
             rtl_dir / filename,
             render_irq_group_bindings(group, interrupts),

rtl/mini/integration/generate_user_extensions.py

@@ -269,7 +269,7 @@ def render_ip_bindings(extensions: ExtensionMap) -> str:
         lines.extend(
             [
                 f"  user_gpio_if #(`USER_GPIO_NUM) u_user_{target.slot}_gpio_if ();",
-                f"  apb4_if u_user_{target.slot}_apb_if (clk_i, rst_n_i);",
+                f"  apb4_if u_user_{target.slot}_apb4_if (clk_i, rst_n_i);",
             ]
         )
     lines.extend(
@@ -285,7 +285,7 @@ def render_ip_bindings(extensions: ExtensionMap) -> str:
     )
     for target in extensions.ip_targets:
         lines.extend(
-            f"    u_user_{target.slot}_apb_if.{signal} = '0;" for signal in APB_REQUEST_SIGNALS
+            f"    u_user_{target.slot}_apb4_if.{signal} = '0;" for signal in APB_REQUEST_SIGNALS
         )
     lines.append("    unique case (sel_i)")
     for target in extensions.ip_targets:
@@ -294,13 +294,13 @@ def render_ip_bindings(extensions: ExtensionMap) -> str:
                 f"      {extensions.ip_selector_width}'d{target.slot}: begin",
                 f"        gpio.do_o = u_user_{target.slot}_gpio_if.do_o;",
                 f"        gpio.oe_o = u_user_{target.slot}_gpio_if.oe_o;",
-                f"        apb.pready = u_user_{target.slot}_apb_if.pready;",
-                f"        apb.prdata = u_user_{target.slot}_apb_if.prdata;",
-                f"        apb.pslverr = u_user_{target.slot}_apb_if.pslverr;",
+                f"        apb.pready = u_user_{target.slot}_apb4_if.pready;",
+                f"        apb.prdata = u_user_{target.slot}_apb4_if.prdata;",
+                f"        apb.pslverr = u_user_{target.slot}_apb4_if.pslverr;",
             ]
         )
         lines.extend(
-            f"        u_user_{target.slot}_apb_if.{signal} = apb.{signal};"
+            f"        u_user_{target.slot}_apb4_if.{signal} = apb.{signal};"
             for signal in APB_REQUEST_SIGNALS
         )
         lines.append("      end")
@@ -315,7 +315,7 @@ def render_ip_bindings(extensions: ExtensionMap) -> str:
                 "      .clk_i  (clk_i),",
                 "      .rst_n_i(rst_n_i),",
                 f"      .gpio   (u_user_{target.slot}_gpio_if),",
-                f"      .apb    (u_user_{target.slot}_apb_if)",
+                f"      .apb    (u_user_{target.slot}_apb4_if)",
                 "  );",
                 "",
             ]

rtl/mini/integration/soc_topology.json

@@ -4,21 +4,21 @@
   "irq_vector_width": 32,
   "irq_groups": [
     {
-      "name": "apb4",
+      "name": "apb4_periph",
       "width": 14,
-      "top_signal": "s_apb4_irq"
+      "top_signal": "s_apb4_periph_irq"
     },
     {
-      "name": "apb",
+      "name": "apb4_system",
       "width": 5,
-      "top_signal": "s_apb_irq"
+      "top_signal": "s_apb4_system_irq"
     }
   ],
   "interrupts": [
     {
       "name": "clint_software",
       "description": "CLINT machine software interrupt",
-      "group": "apb4",
+      "group": "apb4_periph",
       "group_bit": 0,
       "core_bit": 0,
       "signal": "u_clint_if.software_irq_o[0]",
@@ -27,7 +27,7 @@
     {
       "name": "clint_timer",
       "description": "CLINT machine timer interrupt",
-      "group": "apb4",
+      "group": "apb4_periph",
       "group_bit": 1,
       "core_bit": 1,
       "signal": "u_clint_if.timer_irq_o[0]",
@@ -36,7 +36,7 @@
     {
       "name": "uart0",
       "description": "APB4 UART0 interrupt",
-      "group": "apb4",
+      "group": "apb4_periph",
       "group_bit": 2,
       "core_bit": 2,
       "signal": "uart.irq_o"
@@ -44,7 +44,7 @@
     {
       "name": "timer0",
       "description": "APB4 timer0 interrupt",
-      "group": "apb4",
+      "group": "apb4_periph",
       "group_bit": 3,
       "core_bit": 3,
       "signal": "s_tim0_irq"
@@ -52,7 +52,7 @@
     {
       "name": "timer1",
       "description": "APB4 timer1 interrupt",
-      "group": "apb4",
+      "group": "apb4_periph",
       "group_bit": 4,
       "core_bit": 4,
       "signal": "s_tim1_irq"
@@ -60,7 +60,7 @@
     {
       "name": "psram",
       "description": "PSRAM controller interrupt",
-      "group": "apb4",
+      "group": "apb4_periph",
       "group_bit": 5,
       "core_bit": 5,
       "signal": "psram.irq_o"
@@ -68,7 +68,7 @@
     {
       "name": "spisd",
       "description": "SPI SD controller interrupt",
-      "group": "apb4",
+      "group": "apb4_periph",
       "group_bit": 6,
       "core_bit": 6,
       "signal": "spisd.irq_o"
@@ -76,7 +76,7 @@
     {
       "name": "i2c0",
       "description": "APB4 I2C0 interrupt",
-      "group": "apb4",
+      "group": "apb4_periph",
       "group_bit": 7,
       "core_bit": 7,
       "signal": "i2c0.irq_o"
@@ -84,7 +84,7 @@
     {
       "name": "i2s",
       "description": "APB4 I2S interrupt",
-      "group": "apb4",
+      "group": "apb4_periph",
       "group_bit": 8,
       "core_bit": 8,
       "signal": "i2s.irq_o"
@@ -92,47 +92,47 @@
     {
       "name": "xpi",
       "description": "XPI controller interrupt",
-      "group": "apb4",
+      "group": "apb4_periph",
       "group_bit": 9,
       "core_bit": 9,
       "signal": "xpi.irq_o"
     },
     {
       "name": "pwm",
-      "description": "APB PWM interrupt",
-      "group": "apb",
+      "description": "APB4 PWM interrupt",
+      "group": "apb4_system",
       "group_bit": 0,
       "core_bit": 11,
       "signal": "pwm.irq_o"
     },
     {
       "name": "ps2",
-      "description": "APB PS2 interrupt",
-      "group": "apb",
+      "description": "APB4 PS2 interrupt",
+      "group": "apb4_system",
       "group_bit": 1,
       "core_bit": 12,
       "signal": "ps2.irq_o"
     },
     {
       "name": "rtc",
-      "description": "APB RTC interrupt",
-      "group": "apb",
+      "description": "APB4 RTC interrupt",
+      "group": "apb4_system",
       "group_bit": 2,
       "core_bit": 13,
       "signal": "u_rtc_if.irq_o"
     },
     {
       "name": "watchdog_early_warning",
-      "description": "APB watchdog early-warning interrupt",
-      "group": "apb",
+      "description": "APB4 watchdog early-warning interrupt",
+      "group": "apb4_system",
       "group_bit": 3,
       "core_bit": 14,
       "signal": "u_wdg_if.irq_o"
     },
     {
       "name": "rng",
-      "description": "APB RNG data/error interrupt",
-      "group": "apb",
+      "description": "APB4 RNG data/error interrupt",
+      "group": "apb4_system",
       "group_bit": 4,
       "core_bit": 16,
       "signal": "s_rng_irq",
@@ -141,7 +141,7 @@
     {
       "name": "ws2812",
       "description": "WS2812 transmitter interrupt",
-      "group": "apb4",
+      "group": "apb4_periph",
       "group_bit": 10,
       "core_bit": 17,
       "signal": "ws2812.irq_o"
@@ -149,7 +149,7 @@
     {
       "name": "gpio",
       "description": "APB4 GPIO combined interrupt",
-      "group": "apb4",
+      "group": "apb4_periph",
       "group_bit": 11,
       "core_bit": 18,
       "signal": "gpio.irq_o"
@@ -157,7 +157,7 @@
     {
       "name": "i2c1",
       "description": "APB4 I2C1 interrupt",
-      "group": "apb4",
+      "group": "apb4_periph",
       "group_bit": 12,
       "core_bit": 19,
       "signal": "i2c1.irq_o"
@@ -165,7 +165,7 @@
     {
       "name": "dvp",
       "description": "APB4 DVP capture interrupt",
-      "group": "apb4",
+      "group": "apb4_periph",
       "group_bit": 13,
       "core_bit": 15,
       "signal": "s_dvp_irq"
@@ -201,67 +201,203 @@
       "protocol": "axi4"
     },
     {
-      "name": "apb",
-      "interface": "u_apb_axi4_if",
+      "name": "system",
+      "interface": "u_system_axi4_if",
       "protocol": "axi4"
     }
   ],
-  "apb_targets": [
+  "apb4_periph_targets": [
+    {
+      "slot": 0,
+      "name": "uart0",
+      "timed_interface": "u_uart_apb4_if",
+      "pure_interface": "u_uart_apb4_pure_if",
+      "region": "APB4_UART0"
+    },
+    {
+      "slot": 1,
+      "name": "gpio",
+      "timed_interface": "u_gpio_apb4_if",
+      "pure_interface": "u_gpio_apb4_pure_if",
+      "region": "APB4_GPIO",
+      "regions": [
+        "APB4_GPIO",
+        "APB4_GPIO_ADMIN"
+      ]
+    },
+    {
+      "slot": 2,
+      "name": "tim0",
+      "timed_interface": "u_tim0_apb4_if",
+      "pure_interface": "u_tim0_apb4_pure_if",
+      "region": "APB4_TIM0"
+    },
+    {
+      "slot": 3,
+      "name": "tim1",
+      "timed_interface": "u_tim1_apb4_if",
+      "pure_interface": "u_tim1_apb4_pure_if",
+      "region": "APB4_TIM1"
+    },
+    {
+      "slot": 4,
+      "name": "psram",
+      "timed_interface": "u_psram_apb4_if",
+      "pure_interface": "u_psram_apb4_pure_if",
+      "region": "APB4_PSRAM"
+    },
+    {
+      "slot": 5,
+      "name": "spisd",
+      "timed_interface": "u_spisd_apb4_if",
+      "pure_interface": "u_spisd_apb4_pure_if",
+      "region": "APB4_SPISD"
+    },
+    {
+      "slot": 6,
+      "name": "i2c0",
+      "timed_interface": "u_i2c0_apb4_if",
+      "pure_interface": "u_i2c0_apb4_pure_if",
+      "region": "APB4_I2C0"
+    },
+    {
+      "slot": 7,
+      "name": "i2s",
+      "timed_interface": "u_i2s_apb4_if",
+      "pure_interface": "u_i2s_apb4_pure_if",
+      "region": "APB4_I2S"
+    },
+    {
+      "slot": 8,
+      "name": "ws2812",
+      "timed_interface": "u_ws2812_apb4_if",
+      "pure_interface": "u_ws2812_apb4_pure_if",
+      "region": "APB4_WS2812"
+    },
+    {
+      "slot": 9,
+      "name": "xpi",
+      "timed_interface": "u_xpi_apb4_if",
+      "pure_interface": "u_xpi_apb4_pure_if",
+      "region": "APB4_XPI"
+    },
+    {
+      "slot": 10,
+      "name": "dma",
+      "timed_interface": "u_dma_apb4_if",
+      "pure_interface": "u_dma_apb4_pure_if",
+      "region": "APB4_DMA"
+    },
+    {
+      "slot": 11,
+      "name": "sysctrl",
+      "timed_interface": "u_sysctrl_apb4_if",
+      "pure_interface": "u_sysctrl_apb4_pure_if",
+      "region": "APB4_SYSCTRL"
+    },
+    {
+      "slot": 12,
+      "name": "clint",
+      "timed_interface": "u_clint_apb4_if",
+      "pure_interface": "u_clint_apb4_pure_if",
+      "region": "APB4_CLINT"
+    },
+    {
+      "slot": 13,
+      "name": "sdram",
+      "timed_interface": "sdram_cfg",
+      "pure_interface": "sdram_cfg_pure",
+      "region": "APB4_SDRAM",
+      "regions": [
+        "APB4_SDRAM"
+      ],
+      "external": true
+    },
+    {
+      "slot": 14,
+      "name": "dvp",
+      "timed_interface": "u_dvp_apb4_if",
+      "pure_interface": "u_dvp_apb4_pure_if",
+      "region": "APB4_DVP"
+    },
+    {
+      "slot": 15,
+      "name": "sdio",
+      "timed_interface": "u_sdio_apb4_if",
+      "pure_interface": "u_sdio_apb4_pure_if",
+      "disabled": true
+    },
+    {
+      "slot": 16,
+      "name": "opipsram",
+      "timed_interface": "u_opipsram_apb4_if",
+      "pure_interface": "u_opipsram_apb4_pure_if",
+      "disabled": true
+    },
+    {
+      "slot": 17,
+      "name": "i2c1",
+      "timed_interface": "u_i2c1_apb4_if",
+      "pure_interface": "u_i2c1_apb4_pure_if",
+      "region": "APB4_I2C1"
+    }
+  ],
+  "apb4_system_targets": [
     {
       "slot": 0,
       "name": "archinfo",
-      "timed_interface": "u_archinfo_apb_if",
-      "pure_interface": "u_archinfo_apb_pure_if",
-      "region": "APB_ARCHINFO"
+      "timed_interface": "u_archinfo_apb4_if",
+      "pure_interface": "u_archinfo_apb4_pure_if",
+      "region": "APB4_ARCHINFO"
     },
     {
       "slot": 1,
       "name": "rng",
-      "timed_interface": "u_rng_apb_if",
-      "pure_interface": "u_rng_apb_pure_if",
-      "region": "APB_RNG"
+      "timed_interface": "u_rng_apb4_if",
+      "pure_interface": "u_rng_apb4_pure_if",
+      "region": "APB4_RNG"
     },
     {
       "slot": 2,
       "name": "pwm",
-      "timed_interface": "u_pwm_apb_if",
-      "pure_interface": "u_pwm_apb_pure_if",
-      "region": "APB_PWM"
+      "timed_interface": "u_pwm_apb4_if",
+      "pure_interface": "u_pwm_apb4_pure_if",
+      "region": "APB4_PWM"
     },
     {
       "slot": 3,
       "name": "ps2",
-      "timed_interface": "u_ps2_apb_if",
-      "pure_interface": "u_ps2_apb_pure_if",
-      "region": "APB_PS2"
+      "timed_interface": "u_ps2_apb4_if",
+      "pure_interface": "u_ps2_apb4_pure_if",
+      "region": "APB4_PS2"
     },
     {
       "slot": 4,
       "name": "rtc",
-      "timed_interface": "u_rtc_apb_if",
-      "pure_interface": "u_rtc_apb_pure_if",
-      "region": "APB_RTC"
+      "timed_interface": "u_rtc_apb4_if",
+      "pure_interface": "u_rtc_apb4_pure_if",
+      "region": "APB4_RTC"
     },
     {
       "slot": 5,
       "name": "wdg",
-      "timed_interface": "u_wdg_apb_if",
-      "pure_interface": "u_wdg_apb_pure_if",
-      "region": "APB_WDG"
+      "timed_interface": "u_wdg_apb4_if",
+      "pure_interface": "u_wdg_apb4_pure_if",
+      "region": "APB4_WDG"
     },
     {
       "slot": 6,
       "name": "crc",
-      "timed_interface": "u_crc_apb_if",
-      "pure_interface": "u_crc_apb_pure_if",
-      "region": "APB_CRC"
+      "timed_interface": "u_crc_apb4_if",
+      "pure_interface": "u_crc_apb4_pure_if",
+      "region": "APB4_CRC"
     },
     {
       "slot": 7,
       "name": "user_ip",
-      "timed_interface": "u_user_ip_apb_if",
-      "pure_interface": "u_user_ip_apb_pure_if",
-      "region": "APB_USER_IP"
+      "timed_interface": "u_user_ip_apb4_if",
+      "pure_interface": "u_user_ip_apb4_pure_if",
+      "region": "APB4_USER_IP"
     }
   ],
   "gpio_alt_functions": [
@@ -765,141 +901,5 @@
         "oe": "1'b0"
       }
     }
-  ],
-  "apb4_targets": [
-    {
-      "slot": 0,
-      "name": "uart0",
-      "timed_interface": "u_uart_apb_if",
-      "pure_interface": "u_uart_apb_pure_if",
-      "region": "APB4_UART0"
-    },
-    {
-      "slot": 1,
-      "name": "gpio",
-      "timed_interface": "u_gpio_apb_if",
-      "pure_interface": "u_gpio_apb_pure_if",
-      "region": "APB4_GPIO",
-      "regions": [
-        "APB4_GPIO",
-        "APB4_GPIO_ADMIN"
-      ]
-    },
-    {
-      "slot": 2,
-      "name": "tim0",
-      "timed_interface": "u_tim0_apb_if",
-      "pure_interface": "u_tim0_apb_pure_if",
-      "region": "APB4_TIM0"
-    },
-    {
-      "slot": 3,
-      "name": "tim1",
-      "timed_interface": "u_tim1_apb_if",
-      "pure_interface": "u_tim1_apb_pure_if",
-      "region": "APB4_TIM1"
-    },
-    {
-      "slot": 4,
-      "name": "psram",
-      "timed_interface": "u_psram_apb_if",
-      "pure_interface": "u_psram_apb_pure_if",
-      "region": "APB4_PSRAM"
-    },
-    {
-      "slot": 5,
-      "name": "spisd",
-      "timed_interface": "u_spisd_apb_if",
-      "pure_interface": "u_spisd_apb_pure_if",
-      "region": "APB4_SPISD"
-    },
-    {
-      "slot": 6,
-      "name": "i2c0",
-      "timed_interface": "u_i2c0_apb_if",
-      "pure_interface": "u_i2c0_apb_pure_if",
-      "region": "APB4_I2C0"
-    },
-    {
-      "slot": 7,
-      "name": "i2s",
-      "timed_interface": "u_i2s_apb_if",
-      "pure_interface": "u_i2s_apb_pure_if",
-      "region": "APB4_I2S"
-    },
-    {
-      "slot": 8,
-      "name": "ws2812",
-      "timed_interface": "u_ws2812_apb_if",
-      "pure_interface": "u_ws2812_apb_pure_if",
-      "region": "APB4_WS2812"
-    },
-    {
-      "slot": 9,
-      "name": "xpi",
-      "timed_interface": "u_xpi_apb_if",
-      "pure_interface": "u_xpi_apb_pure_if",
-      "region": "APB4_XPI"
-    },
-    {
-      "slot": 10,
-      "name": "dma",
-      "timed_interface": "u_dma_apb_if",
-      "pure_interface": "u_dma_apb_pure_if",
-      "region": "APB4_DMA"
-    },
-    {
-      "slot": 11,
-      "name": "sysctrl",
-      "timed_interface": "u_sysctrl_apb_if",
-      "pure_interface": "u_sysctrl_apb_pure_if",
-      "region": "APB4_SYSCTRL"
-    },
-    {
-      "slot": 12,
-      "name": "clint",
-      "timed_interface": "u_clint_apb_if",
-      "pure_interface": "u_clint_apb_pure_if",
-      "region": "APB4_CLINT"
-    },
-    {
-      "slot": 13,
-      "name": "sdram",
-      "timed_interface": "sdram_cfg",
-      "pure_interface": "sdram_cfg_pure",
-      "region": "APB4_SDRAM",
-      "regions": [
-        "APB4_SDRAM"
-      ],
-      "external": true
-    },
-    {
-      "slot": 14,
-      "name": "dvp",
-      "timed_interface": "u_dvp_apb_if",
-      "pure_interface": "u_dvp_apb_pure_if",
-      "region": "APB4_DVP"
-    },
-    {
-      "slot": 15,
-      "name": "sdio",
-      "timed_interface": "u_sdio_apb_if",
-      "pure_interface": "u_sdio_apb_pure_if",
-      "disabled": true
-    },
-    {
-      "slot": 16,
-      "name": "opipsram",
-      "timed_interface": "u_opipsram_apb_if",
-      "pure_interface": "u_opipsram_apb_pure_if",
-      "disabled": true
-    },
-    {
-      "slot": 17,
-      "name": "i2c1",
-      "timed_interface": "u_i2c1_apb_if",
-      "pure_interface": "u_i2c1_apb_pure_if",
-      "region": "APB4_I2C1"
-    }
   ]
 }

rtl/mini/top/apb4_periph.sv

@@ -14,38 +14,38 @@
 
 module apb4_periph (
     // verilog_format: off -- preserve reviewed column alignment
-    input logic                            clk_i,
-    input logic                            rst_n_i,
-    input logic                            clk_aud_i,
-    input logic                            rst_aud_n_i,
-    input logic                            debug_halted_i,
-    input logic                            timebase_tick_i,
-    axi4_if.slave                          cfg_axi4,
-    axi4_if.slave                          psram_axi4,
-    axi4_if.slave                          xpi_axi4,
-    axi4_if.slave                          spisd_axi4,
-    gpio_if.dut                            gpio,
-    user_gpio_if.padctrl                   user_gpio,
-    uart_if.dut                            uart,
-    psram_if.dut                           psram,
-    spi_if.dut                             spisd,
-    i2c_if.dut                             i2c0,
-    i2s_if.dut                             i2s,
-    ws2812_if.dut                          ws2812,
-    xpi_if.dut                             xpi,
-    axi4_if.master                         dma_axi4,
-    sysctrl_if.dut                         sysctrl,
-    pll_ctrl_if.sysctrl                    pll_ctrl,
-    apb4_if.master                         sdram_cfg,
-    dvp_if.dut                             dvp,
-    sdio_if.dut                            sdio,
-    opipsram_if.dut                        opipsram,
-    i2c_if.dut                             i2c1,
-    input logic                            fault_valid_i,
-    input logic [31:0]                     fault_addr_i,
-    input logic [3:0]                      fault_wstrb_i,
-    input logic                            fault_reserved_i,
-    output logic [`SOC_IRQ_APB4_WIDTH-1:0] irq_o
+    input logic                                   clk_i,
+    input logic                                   rst_n_i,
+    input logic                                   clk_aud_i,
+    input logic                                   rst_aud_n_i,
+    input logic                                   debug_halted_i,
+    input logic                                   timebase_tick_i,
+    axi4_if.slave                                 cfg_axi4,
+    axi4_if.slave                                 psram_axi4,
+    axi4_if.slave                                 xpi_axi4,
+    axi4_if.slave                                 spisd_axi4,
+    gpio_if.dut                                   gpio,
+    user_gpio_if.padctrl                          user_gpio,
+    uart_if.dut                                   uart,
+    psram_if.dut                                  psram,
+    spi_if.dut                                    spisd,
+    i2c_if.dut                                    i2c0,
+    i2s_if.dut                                    i2s,
+    ws2812_if.dut                                 ws2812,
+    xpi_if.dut                                    xpi,
+    axi4_if.master                                dma_axi4,
+    sysctrl_if.dut                                sysctrl,
+    pll_ctrl_if.sysctrl                           pll_ctrl,
+    apb4_if.master                                sdram_cfg,
+    dvp_if.dut                                    dvp,
+    sdio_if.dut                                   sdio,
+    opipsram_if.dut                               opipsram,
+    i2c_if.dut                                    i2c1,
+    input logic                                   fault_valid_i,
+    input logic [31:0]                            fault_addr_i,
+    input logic [3:0]                             fault_wstrb_i,
+    input logic                                   fault_reserved_i,
+    output logic [`SOC_IRQ_APB4_PERIPH_WIDTH-1:0] irq_o
     // verilog_format: on
 );
 
@@ -112,7 +112,7 @@ rib_if u_dma_rib_if ();
   localparam bit GPIO_HAS_PULL_DOWN = 1'b0;
 `endif
 
-  axi42apb_periph u_axi42apb_periph (
+  axi42apb4_periph u_axi42apb4_periph (
       .clk_i  (clk_i),
       .rst_n_i(rst_n_i),
       .axi4   (cfg_axi4),
@@ -137,7 +137,7 @@ rib_if u_dma_rib_if ();
   assign u_dma_hw_trg_if.i2c1_tx_proc = ~s_dma_i2c1_tx_stall;
   assign u_dma_hw_trg_if.i2c1_rx_proc = ~s_dma_i2c1_rx_stall;
 
-  `include "soc_apb4_irq_bindings.svh"
+  `include "apb4_periph_irq_bindings.svh"
 
   // verilog_format: off -- preserve reviewed column alignment
   apb4_gpio #(
@@ -149,7 +149,7 @@ rib_if u_dma_rib_if ();
   ) u_apb4_gpio (
       .clk_i     (clk_i),
       .rst_n_i   (rst_n_i),
-      .apb4      (u_gpio_apb_if),
+      .apb4      (u_gpio_apb4_if),
       .gpio      (gpio),
       .user_gpio (user_gpio)
   );
@@ -160,7 +160,7 @@ rib_if u_dma_rib_if ();
       .rst_n_i       (rst_n_i),
       .dma_tx_stall_o(s_dma_uart_tx_stall),
       .dma_rx_stall_o(s_dma_uart_rx_stall),
-      .apb4          (u_uart_apb_if),
+      .apb4          (u_uart_apb4_if),
       .uart          (uart)
   );
 
@@ -168,7 +168,7 @@ rib_if u_dma_rib_if ();
       .clk_i         (clk_i),
       .rst_n_i       (rst_n_i),
       .debug_halted_i(debug_halted_i),
-      .apb4          (u_tim0_apb_if),
+      .apb4          (u_tim0_apb4_if),
       .irq_o         (s_tim0_irq)
   );
 
@@ -176,14 +176,14 @@ rib_if u_dma_rib_if ();
       .clk_i         (clk_i),
       .rst_n_i       (rst_n_i),
       .debug_halted_i(debug_halted_i),
-      .apb4          (u_tim1_apb_if),
+      .apb4          (u_tim1_apb4_if),
       .irq_o         (s_tim1_irq)
   );
 
   apb4_psram u_apb4_psram (
       .clk_i   (clk_i),
       .rst_n_i (rst_n_i),
-      .cfg_apb4(u_psram_apb_if),
+      .cfg_apb4(u_psram_apb4_if),
       .mem_axi4(psram_axi4),
       .psram   (psram)
   );
@@ -191,7 +191,7 @@ rib_if u_dma_rib_if ();
   apb4_spisd u_apb4_spisd (
       .clk_i   (clk_i),
       .rst_n_i (rst_n_i),
-      .apb4    (u_spisd_apb_if),
+      .apb4    (u_spisd_apb4_if),
       .mem_axi4(spisd_axi4),
       .spi     (spisd)
   );
@@ -201,7 +201,7 @@ rib_if u_dma_rib_if ();
       .rst_n_i       (rst_n_i),
       .dma_tx_stall_o(s_dma_i2c0_tx_stall),
       .dma_rx_stall_o(s_dma_i2c0_rx_stall),
-      .apb4          (u_i2c0_apb_if),
+      .apb4          (u_i2c0_apb4_if),
       .i2c           (i2c0)
   );
 
@@ -212,7 +212,7 @@ rib_if u_dma_rib_if ();
       .rst_aud_n_i   (rst_aud_n_i),
       .dma_tx_stall_o(s_dma_i2s_tx_stall),
       .dma_rx_stall_o(s_dma_i2s_rx_stall),
-      .apb4          (u_i2s_apb_if),
+      .apb4          (u_i2s_apb4_if),
       .tx_axis       (u_i2s_tx_axis_if),
       .rx_axis       (u_i2s_rx_axis_if),
       .i2s           (i2s)
@@ -221,7 +221,7 @@ rib_if u_dma_rib_if ();
   apb4_ws2812 u_apb4_ws2812 (
       .clk_i  (clk_i),
       .rst_n_i(rst_n_i),
-      .apb4   (u_ws2812_apb_if),
+      .apb4   (u_ws2812_apb4_if),
       .ws2812 (ws2812)
   );
 
@@ -231,7 +231,7 @@ rib_if u_dma_rib_if ();
       .dma_xfer_done_i(s_dma_xfer_done),
       .dma_tx_stall_o (s_dma_xpi_tx_stall),
       .dma_rx_stall_o (s_dma_xpi_rx_stall),
-      .apb4           (u_xpi_apb_if),
+      .apb4           (u_xpi_apb4_if),
       .mem_axi4       (xpi_axi4),
       .xpi            (xpi)
   );
@@ -241,7 +241,7 @@ rib_if u_dma_rib_if ();
       .rst_n_i        (rst_n_i),
       .dma_xfer_done_o(s_dma_xfer_done),
       .hw_trg         (u_dma_hw_trg_if),
-      .apb4           (u_dma_apb_if),
+      .apb4           (u_dma_apb4_if),
       .rib            (u_dma_rib_if),
       .i2s_tx_axis    (u_i2s_tx_axis_if),
       .i2s_rx_axis    (u_i2s_rx_axis_if),
@@ -255,7 +255,7 @@ rib_if u_dma_rib_if ();
       .fault_addr_i    (fault_addr_i),
       .fault_wstrb_i   (fault_wstrb_i),
       .fault_reserved_i(fault_reserved_i),
-      .apb4            (u_sysctrl_apb_if),
+      .apb4            (u_sysctrl_apb4_if),
       .sysctrl         (sysctrl),
       .pll_ctrl        (pll_ctrl)
   );
@@ -264,14 +264,14 @@ rib_if u_dma_rib_if ();
       .clk_i          (clk_i),
       .rst_n_i        (rst_n_i),
       .timebase_tick_i(timebase_tick_i),
-      .apb4           (u_clint_apb_if),
+      .apb4           (u_clint_apb4_if),
       .clint          (u_clint_if)
   );
 
   axi4s_dvp u_axi4_dvp (
       .clk_i  (clk_i),
       .rst_n_i(rst_n_i),
-      .apb4   (u_dvp_apb_if),
+      .apb4   (u_dvp_apb4_if),
       .rx_axis(u_dvp_rx_axis_if),
       .dvp    (dvp),
       .irq_o  (s_dvp_irq)
@@ -280,14 +280,14 @@ rib_if u_dma_rib_if ();
   apb4_sdio u_apb4_sdio (
       .clk_i  (clk_i),
       .rst_n_i(rst_n_i),
-      .apb4   (u_sdio_apb_if),
+      .apb4   (u_sdio_apb4_if),
       .sdio   (sdio)
   );
 
   apb4_opipsram u_apb4_opipsram (
       .clk_i  (clk_i),
       .rst_n_i(rst_n_i),
-      .apb4   (u_opipsram_apb_if),
+      .apb4   (u_opipsram_apb4_if),
       .psram  (opipsram)
   );
 
@@ -296,7 +296,7 @@ rib_if u_dma_rib_if ();
       .rst_n_i       (rst_n_i),
       .dma_tx_stall_o(s_dma_i2c1_tx_stall),
       .dma_rx_stall_o(s_dma_i2c1_rx_stall),
-      .apb4          (u_i2c1_apb_if),
+      .apb4          (u_i2c1_apb4_if),
       .i2c           (i2c1)
   );
 

rtl/mini/top/apb4_system.sv

@@ -17,19 +17,19 @@
 
 module apb4_system (
     // verilog_format: off -- preserve reviewed column alignment
-    input  logic                          clk_i,
-    input  logic                          rst_n_i,
-    input  logic                          clk_aud_i,
-    input  logic                          rst_aud_n_i,
-    input  logic                          debug_halted_i,
-    axi4_if.slave                         axi4,
-    pwm_if.dut                            pwm,
-    ps2_if.dut                            ps2,
-    input  logic [`USER_IPSEL_WIDTH-1:0]  ip_sel_i,
-    user_gpio_if.user_ip                  user_gpio,
-    output logic                          rtc_wake_o,
-    output logic                          wdg_reset_req_o,
-    output logic [`SOC_IRQ_APB_WIDTH-1:0] irq_o
+    input  logic                                  clk_i,
+    input  logic                                  rst_n_i,
+    input  logic                                  clk_aud_i,
+    input  logic                                  rst_aud_n_i,
+    input  logic                                  debug_halted_i,
+    axi4_if.slave                                 axi4,
+    pwm_if.dut                                    pwm,
+    ps2_if.dut                                    ps2,
+    input  logic [`USER_IPSEL_WIDTH-1:0]          ip_sel_i,
+    user_gpio_if.user_ip                          user_gpio,
+    output logic                                  rtc_wake_o,
+    output logic                                  wdg_reset_req_o,
+    output logic [`SOC_IRQ_APB4_SYSTEM_WIDTH-1:0] irq_o
     // verilog_format: on
 );
 
@@ -84,7 +84,7 @@ module apb4_system (
 `endif
 
   // Generated timed and pure scalar APB interfaces preserve FPGA compatibility.
-  `include "soc_apb_interfaces.svh"
+  `include "apb4_system_interfaces.svh"
 
   // Low-frequency peripherals retain their dedicated interfaces.
   rtc_if u_rtc_if (
@@ -96,7 +96,7 @@ module apb4_system (
       .wdg_rst_n_i   (rst_aud_n_i),
       .debug_halted_i(debug_halted_i)
   );
-  `include "soc_apb_bridges.svh"
+  `include "apb4_system_bridges.svh"
 
   // verilog_format: off -- preserve reviewed column alignment
   apb4_archinfo #(
@@ -114,7 +114,7 @@ module apb4_system (
       .device_id_i            (128'h0000_0000_0000_0000_0000_0000_0000_0000),
       .device_id_valid_i      (1'b0),
       .device_id_read_enable_i(1'b0),
-      .apb4                   (u_archinfo_apb_if)
+      .apb4                   (u_archinfo_apb4_if)
   );
   // verilog_format: on
 
@@ -139,14 +139,14 @@ module apb4_system (
       .entropy_qualified_i(s_rng_entropy_qualified),
       .entropy_fault_i    (s_rng_entropy_fault),
       .irq_o              (s_rng_irq),
-      .apb4               (u_rng_apb_if)
+      .apb4               (u_rng_apb4_if)
   );
 
   apb4_pwm #(
       .PCLK_HZ(`SOC_EXT_CLK_HZ)
   ) u_apb4_pwm (
       .debug_halted_i(debug_halted_i),
-      .apb4          (u_pwm_apb_if),
+      .apb4          (u_pwm_apb4_if),
       .pwm           (pwm)
   );
 
@@ -155,14 +155,14 @@ module apb4_system (
       .RX_FIFO_DEPTH(16),
       .TX_FIFO_DEPTH(16)
   ) u_apb4_ps2 (
-      .apb4(u_ps2_apb_if),
+      .apb4(u_ps2_apb4_if),
       .ps2 (ps2)
   );
 
   apb4_rtc #(
       .RTC_CLOCK_HZ(`SOC_AUD_CLK_HZ)
   ) u_apb4_rtc (
-      .apb4(u_rtc_apb_if),
+      .apb4(u_rtc_apb4_if),
       .rtc (u_rtc_if)
   );
 
@@ -172,22 +172,22 @@ module apb4_system (
       .WDG_CLOCK_HZ      (`SOC_AUD_CLK_HZ),
       .RESET_PULSE_CYCLES(8)
   ) u_apb4_wdg (
-      .apb4(u_wdg_apb_if),
+      .apb4(u_wdg_apb4_if),
       .wdg (u_wdg_if)
   );
 
   assign wdg_reset_req_o = u_wdg_if.reset_req_o;
 
-  apb4_crc u_apb4_crc (.apb4(u_crc_apb_if));
+  apb4_crc u_apb4_crc (.apb4(u_crc_apb4_if));
 
   // Generated IRQ ownership and core-vector bit assignments are topology checked.
-  `include "soc_apb_irq_bindings.svh"
+  `include "apb4_system_irq_bindings.svh"
 
-axi42apb u_axi42apb (
+axi42apb4_system u_axi42apb4_system (
       .clk_i  (clk_i),
       .rst_n_i(rst_n_i),
       .axi4   (axi4),
-      `include "soc_apb_connections.svh"
+      `include "apb4_system_connections.svh"
   );
 
   user_ip_wrapper u_user_ip_wrapper (
@@ -195,7 +195,7 @@ axi42apb u_axi42apb (
       .rst_n_i(rst_n_i),
       .sel_i  (ip_sel_i),
       .gpio   (user_gpio),
-      .apb    (u_user_ip_apb_if)
+      .apb    (u_user_ip_apb4_if)
   );
 
 endmodule

rtl/mini/top/axi42apb.sv

@@ -1,254 +0,0 @@
-// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
-// retroSoC is licensed under Mulan PSL v2.
-// See LICENSE for the complete license text.
-
-`include "axi4_define.svh"
-`include "mmap_define.svh"
-
-module axi42apb (
-    input logic         clk_i,
-    input logic         rst_n_i,
-          axi4_if.slave axi4,
-    `include "soc_apb_ports.svh"
-);
-  localparam logic [3:0] FSM_IDLE = 4'd0;
-  localparam logic [3:0] FSM_DECODE = 4'd1;
-  localparam logic [3:0] FSM_WR_DATA = 4'd2;
-  localparam logic [3:0] FSM_SETP = 4'd3;
-  localparam logic [3:0] FSM_ENAB = 4'd4;
-  localparam logic [3:0] FSM_WR_RESP = 4'd5;
-  localparam logic [3:0] FSM_RD_RESP = 4'd6;
-  localparam logic [3:0] FSM_ERR_WR_DATA = 4'd7;
-  localparam logic [3:0] FSM_ERR_WR_RESP = 4'd8;
-  localparam logic [3:0] FSM_ERR_RD_RESP = 4'd9;
-
-  logic [3:0] s_fsm_d, s_fsm_q;
-  logic [31:0] s_addr_d, s_addr_q, s_decode_addr;
-  logic [31:0] s_wdata_d, s_wdata_q;
-  logic [3:0] s_wstrb_d, s_wstrb_q;
-  logic s_write_d, s_write_q;
-  logic s_id_d, s_id_q;
-  logic [7:0] s_len_d, s_len_q;
-  logic [7:0] s_beat_d, s_beat_q;
-  logic [31:0] s_rdata_d, s_rdata_q;
-  logic [1:0] s_resp_d, s_resp_q;
-  logic [31:0] s_rd_data;
-  logic s_xfer_valid, s_xfer_ready, s_xfer_err;
-  logic s_psel_valid;
-
-  `include "soc_apb_declarations.svh"
-
-  assign s_decode_addr = s_addr_q;
-  assign s_xfer_valid  = (s_fsm_q == FSM_SETP) || (s_fsm_q == FSM_ENAB);
-  `include "soc_apb_request_routes.svh"
-  `include "soc_apb_select_routes.svh"
-  `include "soc_apb_response_mux.svh"
-  assign s_psel_valid = |s_psel_comb;
-
-  assign axi4.awready = (s_fsm_q == FSM_IDLE) && !axi4.arvalid;
-  assign axi4.arready = (s_fsm_q == FSM_IDLE);
-  assign axi4.wready = (s_fsm_q == FSM_WR_DATA) || (s_fsm_q == FSM_ERR_WR_DATA);
-  assign axi4.bid = s_id_q;
-  assign axi4.bresp = s_resp_q;
-  assign axi4.buser = '0;
-  assign axi4.bvalid = (s_fsm_q == FSM_WR_RESP) || (s_fsm_q == FSM_ERR_WR_RESP);
-  assign axi4.rid = s_id_q;
-  assign axi4.rdata = (s_fsm_q == FSM_RD_RESP) ? s_rdata_q : '0;
-  assign axi4.rresp = s_resp_q;
-  assign axi4.rlast = (s_fsm_q == FSM_RD_RESP) ||
-                      ((s_fsm_q == FSM_ERR_RD_RESP) && (s_beat_q == s_len_q));
-  assign axi4.ruser = '0;
-  assign axi4.rvalid = (s_fsm_q == FSM_RD_RESP) || (s_fsm_q == FSM_ERR_RD_RESP);
-
-  always_comb begin
-    s_fsm_d   = s_fsm_q;
-    s_addr_d  = s_addr_q;
-    s_wdata_d = s_wdata_q;
-    s_wstrb_d = s_wstrb_q;
-    s_write_d = s_write_q;
-    s_id_d    = s_id_q;
-    s_len_d   = s_len_q;
-    s_beat_d  = s_beat_q;
-    s_rdata_d = s_rdata_q;
-    s_resp_d  = s_resp_q;
-
-    unique case (s_fsm_q)
-      FSM_IDLE: begin
-        s_beat_d = '0;
-        s_resp_d = `AXI4_RESP_OKAY;
-        if (axi4.arvalid && axi4.arready) begin
-          s_addr_d  = axi4.araddr;
-          s_write_d = 1'b0;
-          s_id_d    = axi4.arid;
-          s_len_d   = axi4.arlen;
-          if ((axi4.arlen != 8'd0) || (axi4.arburst != `AXI4_BURST_TYPE_INCR) || axi4.arlock) begin
-            s_resp_d = `AXI4_RESP_SLAVE_ERROR;
-            s_fsm_d  = FSM_ERR_RD_RESP;
-          end else begin
-            s_fsm_d = FSM_DECODE;
-          end
-        end else if (axi4.awvalid && axi4.awready) begin
-          s_addr_d  = axi4.awaddr;
-          s_write_d = 1'b1;
-          s_id_d    = axi4.awid;
-          s_len_d   = axi4.awlen;
-          if ((axi4.awlen != 8'd0) || (axi4.awburst != `AXI4_BURST_TYPE_INCR) || axi4.awlock) begin
-            s_resp_d = `AXI4_RESP_SLAVE_ERROR;
-            s_fsm_d  = FSM_ERR_WR_DATA;
-          end else begin
-            s_fsm_d = FSM_DECODE;
-          end
-        end
-      end
-      FSM_DECODE: begin
-        if (!s_psel_valid) begin
-          s_resp_d = `AXI4_RESP_DECODE_ERROR;
-          s_fsm_d  = s_write_q ? FSM_ERR_WR_DATA : FSM_ERR_RD_RESP;
-        end else begin
-          s_fsm_d = s_write_q ? FSM_WR_DATA : FSM_SETP;
-        end
-      end
-      FSM_WR_DATA: begin
-        if (axi4.wvalid && axi4.wready) begin
-          s_wdata_d = axi4.wdata;
-          s_wstrb_d = axi4.wstrb;
-          if (axi4.wlast) begin
-            s_fsm_d = FSM_SETP;
-          end else begin
-            s_resp_d = `AXI4_RESP_SLAVE_ERROR;
-            s_fsm_d  = FSM_ERR_WR_DATA;
-          end
-        end
-      end
-      FSM_SETP: s_fsm_d = FSM_ENAB;
-      FSM_ENAB: begin
-        if (s_xfer_ready) begin
-          s_resp_d = s_xfer_err ? `AXI4_RESP_SLAVE_ERROR : `AXI4_RESP_OKAY;
-          if (s_write_q) begin
-            s_fsm_d = FSM_WR_RESP;
-          end else begin
-            s_rdata_d = s_rd_data;
-            s_fsm_d   = FSM_RD_RESP;
-          end
-        end
-      end
-      FSM_WR_RESP: begin
-        if (axi4.bvalid && axi4.bready) s_fsm_d = FSM_IDLE;
-      end
-      FSM_RD_RESP: begin
-        if (axi4.rvalid && axi4.rready) s_fsm_d = FSM_IDLE;
-      end
-      FSM_ERR_WR_DATA: begin
-        if (axi4.wvalid && axi4.wready) begin
-          if ((s_beat_q == s_len_q) || axi4.wlast) begin
-            s_fsm_d = FSM_ERR_WR_RESP;
-          end else begin
-            s_beat_d = s_beat_q + 1'b1;
-          end
-        end
-      end
-      FSM_ERR_WR_RESP: begin
-        if (axi4.bvalid && axi4.bready) s_fsm_d = FSM_IDLE;
-      end
-      FSM_ERR_RD_RESP: begin
-        if (axi4.rvalid && axi4.rready) begin
-          if (s_beat_q == s_len_q) begin
-            s_fsm_d = FSM_IDLE;
-          end else begin
-            s_beat_d = s_beat_q + 1'b1;
-          end
-        end
-      end
-      default:  s_fsm_d = FSM_IDLE;
-    endcase
-  end
-
-  dffr #(
-      .DATA_WIDTH(4)
-  ) u_fsm_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  (s_fsm_d),
-      .dat_o  (s_fsm_q)
-  );
-  dffr #(
-      .DATA_WIDTH(32)
-  ) u_addr_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  (s_addr_d),
-      .dat_o  (s_addr_q)
-  );
-  dffr #(
-      .DATA_WIDTH(32)
-  ) u_wdata_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  (s_wdata_d),
-      .dat_o  (s_wdata_q)
-  );
-  dffr #(
-      .DATA_WIDTH(4)
-  ) u_wstrb_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  (s_wstrb_d),
-      .dat_o  (s_wstrb_q)
-  );
-  dffr #(
-      .DATA_WIDTH(1)
-  ) u_write_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  (s_write_d),
-      .dat_o  (s_write_q)
-  );
-  dffr #(
-      .DATA_WIDTH(1)
-  ) u_id_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  (s_id_d),
-      .dat_o  (s_id_q)
-  );
-  dffr #(
-      .DATA_WIDTH(8)
-  ) u_len_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  (s_len_d),
-      .dat_o  (s_len_q)
-  );
-  dffr #(
-      .DATA_WIDTH(8)
-  ) u_beat_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  (s_beat_d),
-      .dat_o  (s_beat_q)
-  );
-  dffr #(
-      .DATA_WIDTH(32)
-  ) u_rdata_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  (s_rdata_d),
-      .dat_o  (s_rdata_q)
-  );
-  dffr #(
-      .DATA_WIDTH(2)
-  ) u_resp_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  (s_resp_d),
-      .dat_o  (s_resp_q)
-  );
-  dffr #(
-      .DATA_WIDTH(NSLV)
-  ) u_psel_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  ((s_fsm_q == FSM_DECODE) ? s_psel_comb : s_psel_q),
-      .dat_o  (s_psel_q)
-  );
-endmodule

rtl/mini/top/axi42apb4.svh

@@ -0,0 +1,207 @@
+// Shared AXI4-to-APB4 decoder body for both APB4 islands.
+assign axi4.awready = (s_fsm_q == FSM_IDLE) && !axi4.arvalid;
+assign axi4.arready = (s_fsm_q == FSM_IDLE);
+assign axi4.wready = (s_fsm_q == FSM_WR_DATA) || (s_fsm_q == FSM_ERR_WR_DATA);
+assign axi4.bid = s_id_q;
+assign axi4.bresp = s_resp_q;
+assign axi4.buser = '0;
+assign axi4.bvalid = (s_fsm_q == FSM_WR_RESP) || (s_fsm_q == FSM_ERR_WR_RESP);
+assign axi4.rid = s_id_q;
+assign axi4.rdata = (s_fsm_q == FSM_RD_RESP) ? s_rdata_q : '0;
+assign axi4.rresp = s_resp_q;
+assign axi4.rlast = (s_fsm_q == FSM_RD_RESP) ||
+                      ((s_fsm_q == FSM_ERR_RD_RESP) && (s_beat_q == s_len_q));
+assign axi4.ruser = '0;
+assign axi4.rvalid = (s_fsm_q == FSM_RD_RESP) || (s_fsm_q == FSM_ERR_RD_RESP);
+
+always_comb begin
+  s_fsm_d   = s_fsm_q;
+  s_addr_d  = s_addr_q;
+  s_wdata_d = s_wdata_q;
+  s_wstrb_d = s_wstrb_q;
+  s_write_d = s_write_q;
+  s_id_d    = s_id_q;
+  s_len_d   = s_len_q;
+  s_beat_d  = s_beat_q;
+  s_rdata_d = s_rdata_q;
+  s_resp_d  = s_resp_q;
+
+  unique case (s_fsm_q)
+    FSM_IDLE: begin
+      s_beat_d = '0;
+      s_resp_d = `AXI4_RESP_OKAY;
+      if (axi4.arvalid && axi4.arready) begin
+        s_addr_d  = axi4.araddr;
+        s_write_d = 1'b0;
+        s_id_d    = axi4.arid;
+        s_len_d   = axi4.arlen;
+        if ((axi4.arlen != 8'd0) || (axi4.arburst != `AXI4_BURST_TYPE_INCR) || axi4.arlock) begin
+          s_resp_d = `AXI4_RESP_SLAVE_ERROR;
+          s_fsm_d  = FSM_ERR_RD_RESP;
+        end else begin
+          s_fsm_d = FSM_DECODE;
+        end
+      end else if (axi4.awvalid && axi4.awready) begin
+        s_addr_d  = axi4.awaddr;
+        s_write_d = 1'b1;
+        s_id_d    = axi4.awid;
+        s_len_d   = axi4.awlen;
+        if ((axi4.awlen != 8'd0) || (axi4.awburst != `AXI4_BURST_TYPE_INCR) || axi4.awlock) begin
+          s_resp_d = `AXI4_RESP_SLAVE_ERROR;
+          s_fsm_d  = FSM_ERR_WR_DATA;
+        end else begin
+          s_fsm_d = FSM_DECODE;
+        end
+      end
+    end
+    FSM_DECODE: begin
+      if (!s_psel_valid) begin
+        s_resp_d = `AXI4_RESP_DECODE_ERROR;
+        s_fsm_d  = s_write_q ? FSM_ERR_WR_DATA : FSM_ERR_RD_RESP;
+      end else begin
+        s_fsm_d = s_write_q ? FSM_WR_DATA : FSM_SETP;
+      end
+    end
+    FSM_WR_DATA: begin
+      if (axi4.wvalid && axi4.wready) begin
+        s_wdata_d = axi4.wdata;
+        s_wstrb_d = axi4.wstrb;
+        if (axi4.wlast) begin
+          s_fsm_d = FSM_SETP;
+        end else begin
+          s_resp_d = `AXI4_RESP_SLAVE_ERROR;
+          s_fsm_d  = FSM_ERR_WR_DATA;
+        end
+      end
+    end
+    FSM_SETP: s_fsm_d = FSM_ENAB;
+    FSM_ENAB: begin
+      if (s_xfer_ready) begin
+        s_resp_d = s_xfer_err ? `AXI4_RESP_SLAVE_ERROR : `AXI4_RESP_OKAY;
+        if (s_write_q) begin
+          s_fsm_d = FSM_WR_RESP;
+        end else begin
+          s_rdata_d = s_rd_data;
+          s_fsm_d   = FSM_RD_RESP;
+        end
+      end
+    end
+    FSM_WR_RESP: begin
+      if (axi4.bvalid && axi4.bready) s_fsm_d = FSM_IDLE;
+    end
+    FSM_RD_RESP: begin
+      if (axi4.rvalid && axi4.rready) s_fsm_d = FSM_IDLE;
+    end
+    FSM_ERR_WR_DATA: begin
+      if (axi4.wvalid && axi4.wready) begin
+        if ((s_beat_q == s_len_q) || axi4.wlast) begin
+          s_fsm_d = FSM_ERR_WR_RESP;
+        end else begin
+          s_beat_d = s_beat_q + 1'b1;
+        end
+      end
+    end
+    FSM_ERR_WR_RESP: begin
+      if (axi4.bvalid && axi4.bready) s_fsm_d = FSM_IDLE;
+    end
+    FSM_ERR_RD_RESP: begin
+      if (axi4.rvalid && axi4.rready) begin
+        if (s_beat_q == s_len_q) begin
+          s_fsm_d = FSM_IDLE;
+        end else begin
+          s_beat_d = s_beat_q + 1'b1;
+        end
+      end
+    end
+    default:  s_fsm_d = FSM_IDLE;
+  endcase
+end
+
+dffr #(
+    .DATA_WIDTH(4)
+) u_fsm_dffr (
+    .clk_i  (clk_i),
+    .rst_n_i(rst_n_i),
+    .dat_i  (s_fsm_d),
+    .dat_o  (s_fsm_q)
+);
+dffr #(
+    .DATA_WIDTH(32)
+) u_addr_dffr (
+    .clk_i  (clk_i),
+    .rst_n_i(rst_n_i),
+    .dat_i  (s_addr_d),
+    .dat_o  (s_addr_q)
+);
+dffr #(
+    .DATA_WIDTH(32)
+) u_wdata_dffr (
+    .clk_i  (clk_i),
+    .rst_n_i(rst_n_i),
+    .dat_i  (s_wdata_d),
+    .dat_o  (s_wdata_q)
+);
+dffr #(
+    .DATA_WIDTH(4)
+) u_wstrb_dffr (
+    .clk_i  (clk_i),
+    .rst_n_i(rst_n_i),
+    .dat_i  (s_wstrb_d),
+    .dat_o  (s_wstrb_q)
+);
+dffr #(
+    .DATA_WIDTH(1)
+) u_write_dffr (
+    .clk_i  (clk_i),
+    .rst_n_i(rst_n_i),
+    .dat_i  (s_write_d),
+    .dat_o  (s_write_q)
+);
+dffr #(
+    .DATA_WIDTH(1)
+) u_id_dffr (
+    .clk_i  (clk_i),
+    .rst_n_i(rst_n_i),
+    .dat_i  (s_id_d),
+    .dat_o  (s_id_q)
+);
+dffr #(
+    .DATA_WIDTH(8)
+) u_len_dffr (
+    .clk_i  (clk_i),
+    .rst_n_i(rst_n_i),
+    .dat_i  (s_len_d),
+    .dat_o  (s_len_q)
+);
+dffr #(
+    .DATA_WIDTH(8)
+) u_beat_dffr (
+    .clk_i  (clk_i),
+    .rst_n_i(rst_n_i),
+    .dat_i  (s_beat_d),
+    .dat_o  (s_beat_q)
+);
+dffr #(
+    .DATA_WIDTH(32)
+) u_rdata_dffr (
+    .clk_i  (clk_i),
+    .rst_n_i(rst_n_i),
+    .dat_i  (s_rdata_d),
+    .dat_o  (s_rdata_q)
+);
+dffr #(
+    .DATA_WIDTH(2)
+) u_resp_dffr (
+    .clk_i  (clk_i),
+    .rst_n_i(rst_n_i),
+    .dat_i  (s_resp_d),
+    .dat_o  (s_resp_q)
+);
+dffr #(
+    .DATA_WIDTH(NSLV)
+) u_psel_dffr (
+    .clk_i  (clk_i),
+    .rst_n_i(rst_n_i),
+    .dat_i  ((s_fsm_q == FSM_DECODE) ? s_psel_comb : s_psel_q),
+    .dat_o  (s_psel_q)
+);

rtl/mini/top/axi42apb4_periph.sv

@@ -0,0 +1,25 @@
+// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
+// retroSoC is licensed under Mulan PSL v2.
+// See LICENSE for the complete license text.
+
+`include "axi4_define.svh"
+`include "mmap_define.svh"
+
+module axi42apb4_periph (
+    input logic         clk_i,
+    input logic         rst_n_i,
+          axi4_if.slave axi4,
+    `include "apb4_periph_ports.svh"
+);
+  `include "axi42apb4_state.svh"
+  `include "apb4_periph_declarations.svh"
+
+  assign s_decode_addr = s_addr_q;
+  assign s_xfer_valid  = (s_fsm_q == FSM_SETP) || (s_fsm_q == FSM_ENAB);
+  `include "apb4_periph_request_routes.svh"
+  `include "apb4_periph_select_routes.svh"
+  `include "apb4_periph_response_mux.svh"
+  assign s_psel_valid = |s_psel_comb;
+
+  `include "axi42apb4.svh"
+endmodule

rtl/mini/top/axi42apb4_state.svh

@@ -0,0 +1,26 @@
+// Shared AXI4-to-APB4 decoder state for both APB4 islands.
+localparam logic [3:0] FSM_IDLE = 4'd0;
+localparam logic [3:0] FSM_DECODE = 4'd1;
+localparam logic [3:0] FSM_WR_DATA = 4'd2;
+localparam logic [3:0] FSM_SETP = 4'd3;
+localparam logic [3:0] FSM_ENAB = 4'd4;
+localparam logic [3:0] FSM_WR_RESP = 4'd5;
+localparam logic [3:0] FSM_RD_RESP = 4'd6;
+localparam logic [3:0] FSM_ERR_WR_DATA = 4'd7;
+localparam logic [3:0] FSM_ERR_WR_RESP = 4'd8;
+localparam logic [3:0] FSM_ERR_RD_RESP = 4'd9;
+
+logic [3:0] s_fsm_d, s_fsm_q;
+logic [31:0] s_addr_d, s_addr_q, s_decode_addr;
+logic [31:0] s_wdata_d, s_wdata_q;
+logic [3:0] s_wstrb_d, s_wstrb_q;
+logic s_write_d, s_write_q;
+logic s_id_d, s_id_q;
+logic [7:0] s_len_d, s_len_q;
+logic [7:0] s_beat_d, s_beat_q;
+logic [31:0] s_rdata_d, s_rdata_q;
+logic [1:0] s_resp_d, s_resp_q;
+logic [31:0] s_rd_data;
+logic s_xfer_valid, s_xfer_ready, s_xfer_err;
+logic s_psel_valid;
+

rtl/mini/top/axi42apb4_system.sv

@@ -0,0 +1,25 @@
+// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
+// retroSoC is licensed under Mulan PSL v2.
+// See LICENSE for the complete license text.
+
+`include "axi4_define.svh"
+`include "mmap_define.svh"
+
+module axi42apb4_system (
+    input logic         clk_i,
+    input logic         rst_n_i,
+          axi4_if.slave axi4,
+    `include "apb4_system_ports.svh"
+);
+  `include "axi42apb4_state.svh"
+  `include "apb4_system_declarations.svh"
+
+  assign s_decode_addr = s_addr_q;
+  assign s_xfer_valid  = (s_fsm_q == FSM_SETP) || (s_fsm_q == FSM_ENAB);
+  `include "apb4_system_request_routes.svh"
+  `include "apb4_system_select_routes.svh"
+  `include "apb4_system_response_mux.svh"
+  assign s_psel_valid = |s_psel_comb;
+
+  `include "axi42apb4.svh"
+endmodule

rtl/mini/top/axi42apb_periph.sv

@@ -1,254 +0,0 @@
-// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
-// retroSoC is licensed under Mulan PSL v2.
-// See LICENSE for the complete license text.
-
-`include "axi4_define.svh"
-`include "mmap_define.svh"
-
-module axi42apb_periph (
-    input logic         clk_i,
-    input logic         rst_n_i,
-          axi4_if.slave axi4,
-    `include "apb4_periph_ports.svh"
-);
-  localparam logic [3:0] FSM_IDLE = 4'd0;
-  localparam logic [3:0] FSM_DECODE = 4'd1;
-  localparam logic [3:0] FSM_WR_DATA = 4'd2;
-  localparam logic [3:0] FSM_SETP = 4'd3;
-  localparam logic [3:0] FSM_ENAB = 4'd4;
-  localparam logic [3:0] FSM_WR_RESP = 4'd5;
-  localparam logic [3:0] FSM_RD_RESP = 4'd6;
-  localparam logic [3:0] FSM_ERR_WR_DATA = 4'd7;
-  localparam logic [3:0] FSM_ERR_WR_RESP = 4'd8;
-  localparam logic [3:0] FSM_ERR_RD_RESP = 4'd9;
-
-  logic [3:0] s_fsm_d, s_fsm_q;
-  logic [31:0] s_addr_d, s_addr_q, s_decode_addr;
-  logic [31:0] s_wdata_d, s_wdata_q;
-  logic [3:0] s_wstrb_d, s_wstrb_q;
-  logic s_write_d, s_write_q;
-  logic s_id_d, s_id_q;
-  logic [7:0] s_len_d, s_len_q;
-  logic [7:0] s_beat_d, s_beat_q;
-  logic [31:0] s_rdata_d, s_rdata_q;
-  logic [1:0] s_resp_d, s_resp_q;
-  logic [31:0] s_rd_data;
-  logic s_xfer_valid, s_xfer_ready, s_xfer_err;
-  logic s_psel_valid;
-
-  `include "apb4_periph_declarations.svh"
-
-  assign s_decode_addr = s_addr_q;
-  assign s_xfer_valid  = (s_fsm_q == FSM_SETP) || (s_fsm_q == FSM_ENAB);
-  `include "apb4_periph_request_routes.svh"
-  `include "apb4_periph_select_routes.svh"
-  `include "apb4_periph_response_mux.svh"
-  assign s_psel_valid = |s_psel_comb;
-
-  assign axi4.awready = (s_fsm_q == FSM_IDLE) && !axi4.arvalid;
-  assign axi4.arready = (s_fsm_q == FSM_IDLE);
-  assign axi4.wready = (s_fsm_q == FSM_WR_DATA) || (s_fsm_q == FSM_ERR_WR_DATA);
-  assign axi4.bid = s_id_q;
-  assign axi4.bresp = s_resp_q;
-  assign axi4.buser = '0;
-  assign axi4.bvalid = (s_fsm_q == FSM_WR_RESP) || (s_fsm_q == FSM_ERR_WR_RESP);
-  assign axi4.rid = s_id_q;
-  assign axi4.rdata = (s_fsm_q == FSM_RD_RESP) ? s_rdata_q : '0;
-  assign axi4.rresp = s_resp_q;
-  assign axi4.rlast = (s_fsm_q == FSM_RD_RESP) ||
-                      ((s_fsm_q == FSM_ERR_RD_RESP) && (s_beat_q == s_len_q));
-  assign axi4.ruser = '0;
-  assign axi4.rvalid = (s_fsm_q == FSM_RD_RESP) || (s_fsm_q == FSM_ERR_RD_RESP);
-
-  always_comb begin
-    s_fsm_d   = s_fsm_q;
-    s_addr_d  = s_addr_q;
-    s_wdata_d = s_wdata_q;
-    s_wstrb_d = s_wstrb_q;
-    s_write_d = s_write_q;
-    s_id_d    = s_id_q;
-    s_len_d   = s_len_q;
-    s_beat_d  = s_beat_q;
-    s_rdata_d = s_rdata_q;
-    s_resp_d  = s_resp_q;
-
-    unique case (s_fsm_q)
-      FSM_IDLE: begin
-        s_beat_d = '0;
-        s_resp_d = `AXI4_RESP_OKAY;
-        if (axi4.arvalid && axi4.arready) begin
-          s_addr_d  = axi4.araddr;
-          s_write_d = 1'b0;
-          s_id_d    = axi4.arid;
-          s_len_d   = axi4.arlen;
-          if ((axi4.arlen != 8'd0) || (axi4.arburst != `AXI4_BURST_TYPE_INCR) || axi4.arlock) begin
-            s_resp_d = `AXI4_RESP_SLAVE_ERROR;
-            s_fsm_d  = FSM_ERR_RD_RESP;
-          end else begin
-            s_fsm_d = FSM_DECODE;
-          end
-        end else if (axi4.awvalid && axi4.awready) begin
-          s_addr_d  = axi4.awaddr;
-          s_write_d = 1'b1;
-          s_id_d    = axi4.awid;
-          s_len_d   = axi4.awlen;
-          if ((axi4.awlen != 8'd0) || (axi4.awburst != `AXI4_BURST_TYPE_INCR) || axi4.awlock) begin
-            s_resp_d = `AXI4_RESP_SLAVE_ERROR;
-            s_fsm_d  = FSM_ERR_WR_DATA;
-          end else begin
-            s_fsm_d = FSM_DECODE;
-          end
-        end
-      end
-      FSM_DECODE: begin
-        if (!s_psel_valid) begin
-          s_resp_d = `AXI4_RESP_DECODE_ERROR;
-          s_fsm_d  = s_write_q ? FSM_ERR_WR_DATA : FSM_ERR_RD_RESP;
-        end else begin
-          s_fsm_d = s_write_q ? FSM_WR_DATA : FSM_SETP;
-        end
-      end
-      FSM_WR_DATA: begin
-        if (axi4.wvalid && axi4.wready) begin
-          s_wdata_d = axi4.wdata;
-          s_wstrb_d = axi4.wstrb;
-          if (axi4.wlast) begin
-            s_fsm_d = FSM_SETP;
-          end else begin
-            s_resp_d = `AXI4_RESP_SLAVE_ERROR;
-            s_fsm_d  = FSM_ERR_WR_DATA;
-          end
-        end
-      end
-      FSM_SETP: s_fsm_d = FSM_ENAB;
-      FSM_ENAB: begin
-        if (s_xfer_ready) begin
-          s_resp_d = s_xfer_err ? `AXI4_RESP_SLAVE_ERROR : `AXI4_RESP_OKAY;
-          if (s_write_q) begin
-            s_fsm_d = FSM_WR_RESP;
-          end else begin
-            s_rdata_d = s_rd_data;
-            s_fsm_d   = FSM_RD_RESP;
-          end
-        end
-      end
-      FSM_WR_RESP: begin
-        if (axi4.bvalid && axi4.bready) s_fsm_d = FSM_IDLE;
-      end
-      FSM_RD_RESP: begin
-        if (axi4.rvalid && axi4.rready) s_fsm_d = FSM_IDLE;
-      end
-      FSM_ERR_WR_DATA: begin
-        if (axi4.wvalid && axi4.wready) begin
-          if ((s_beat_q == s_len_q) || axi4.wlast) begin
-            s_fsm_d = FSM_ERR_WR_RESP;
-          end else begin
-            s_beat_d = s_beat_q + 1'b1;
-          end
-        end
-      end
-      FSM_ERR_WR_RESP: begin
-        if (axi4.bvalid && axi4.bready) s_fsm_d = FSM_IDLE;
-      end
-      FSM_ERR_RD_RESP: begin
-        if (axi4.rvalid && axi4.rready) begin
-          if (s_beat_q == s_len_q) begin
-            s_fsm_d = FSM_IDLE;
-          end else begin
-            s_beat_d = s_beat_q + 1'b1;
-          end
-        end
-      end
-      default:  s_fsm_d = FSM_IDLE;
-    endcase
-  end
-
-  dffr #(
-      .DATA_WIDTH(4)
-  ) u_fsm_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  (s_fsm_d),
-      .dat_o  (s_fsm_q)
-  );
-  dffr #(
-      .DATA_WIDTH(32)
-  ) u_addr_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  (s_addr_d),
-      .dat_o  (s_addr_q)
-  );
-  dffr #(
-      .DATA_WIDTH(32)
-  ) u_wdata_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  (s_wdata_d),
-      .dat_o  (s_wdata_q)
-  );
-  dffr #(
-      .DATA_WIDTH(4)
-  ) u_wstrb_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  (s_wstrb_d),
-      .dat_o  (s_wstrb_q)
-  );
-  dffr #(
-      .DATA_WIDTH(1)
-  ) u_write_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  (s_write_d),
-      .dat_o  (s_write_q)
-  );
-  dffr #(
-      .DATA_WIDTH(1)
-  ) u_id_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  (s_id_d),
-      .dat_o  (s_id_q)
-  );
-  dffr #(
-      .DATA_WIDTH(8)
-  ) u_len_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  (s_len_d),
-      .dat_o  (s_len_q)
-  );
-  dffr #(
-      .DATA_WIDTH(8)
-  ) u_beat_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  (s_beat_d),
-      .dat_o  (s_beat_q)
-  );
-  dffr #(
-      .DATA_WIDTH(32)
-  ) u_rdata_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  (s_rdata_d),
-      .dat_o  (s_rdata_q)
-  );
-  dffr #(
-      .DATA_WIDTH(2)
-  ) u_resp_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  (s_resp_d),
-      .dat_o  (s_resp_q)
-  );
-  dffr #(
-      .DATA_WIDTH(NSLV)
-  ) u_psel_dffr (
-      .clk_i  (clk_i),
-      .rst_n_i(rst_n_i),
-      .dat_i  ((s_fsm_q == FSM_DECODE) ? s_psel_comb : s_psel_q),
-      .dat_o  (s_psel_q)
-  );
-endmodule

rtl/mini/top/axi4_bus.sv

@@ -16,7 +16,7 @@ module axi4_bus (
     axi4_if.slave       user_axi4,
     axi4_if.slave       dma_axi4,
     axi4_if.master      cfg_axi4,
-    axi4_if.master      apb_axi4,
+    axi4_if.master      system_axi4,
 `ifdef HAVE_SRAM_IF
     ram_if.master       ram,
 `endif
@@ -38,8 +38,8 @@ module axi4_bus (
     output logic [63:0] perf_mgmt_wait_o,
     output logic [63:0] perf_user_wait_o,
     output logic [63:0] perf_dma_wait_o,
-    output logic [63:0] perf_apb4_wait_o,
-    output logic [63:0] perf_apb_wait_o,
+    output logic [63:0] perf_apb4_periph_wait_o,
+    output logic [63:0] perf_apb4_system_wait_o,
     output logic [63:0] perf_sdram_wait_o,
     output logic [63:0] perf_psram_wait_o,
     output logic [63:0] perf_flash_wait_o
@@ -100,7 +100,7 @@ module axi4_bus (
 
   axi4_connector u_apb_connector (
       .source(u_target_axi4_if[1]),
-      .sink  (apb_axi4)
+      .sink  (system_axi4)
   );
 
   axi4_connector u_ram_connector (
@@ -132,29 +132,29 @@ module axi4_bus (
       .NumMasters(NumMasters),
       .NumTargets(NumTargets)
   ) u_axi4_interconnect (
-      .clk_i            (clk_i),
-      .rst_n_i          (rst_n_i),
-      .masters          (u_master_axi4_if),
-      .targets          (u_target_axi4_if),
-      .user_bus_enable_i(user_bus_enable_i),
-      .user_bus_idle_o  (user_bus_idle_o),
-      .perf_enable_i    (perf_enable_i),
-      .perf_clear_i     (perf_clear_i),
-      .fault_valid_o    (fault_valid_o),
-      .fault_addr_o     (fault_addr_o),
-      .fault_wstrb_o    (fault_wstrb_o),
-      .fault_reserved_o (fault_reserved_o),
-      .fault_access_o   (fault_access_o),
-      .fault_master_o   (fault_master_o),
-      .fault_code_o     (fault_code_o),
-      .perf_mgmt_wait_o (perf_mgmt_wait_o),
-      .perf_user_wait_o (perf_user_wait_o),
-      .perf_dma_wait_o  (perf_dma_wait_o),
-      .perf_apb4_wait_o (perf_apb4_wait_o),
-      .perf_apb_wait_o  (perf_apb_wait_o),
-      .perf_sdram_wait_o(perf_sdram_wait_o),
-      .perf_psram_wait_o(perf_psram_wait_o),
-      .perf_flash_wait_o(perf_flash_wait_o)
+      .clk_i                  (clk_i),
+      .rst_n_i                (rst_n_i),
+      .masters                (u_master_axi4_if),
+      .targets                (u_target_axi4_if),
+      .user_bus_enable_i      (user_bus_enable_i),
+      .user_bus_idle_o        (user_bus_idle_o),
+      .perf_enable_i          (perf_enable_i),
+      .perf_clear_i           (perf_clear_i),
+      .fault_valid_o          (fault_valid_o),
+      .fault_addr_o           (fault_addr_o),
+      .fault_wstrb_o          (fault_wstrb_o),
+      .fault_reserved_o       (fault_reserved_o),
+      .fault_access_o         (fault_access_o),
+      .fault_master_o         (fault_master_o),
+      .fault_code_o           (fault_code_o),
+      .perf_mgmt_wait_o       (perf_mgmt_wait_o),
+      .perf_user_wait_o       (perf_user_wait_o),
+      .perf_dma_wait_o        (perf_dma_wait_o),
+      .perf_apb4_periph_wait_o(perf_apb4_periph_wait_o),
+      .perf_apb4_system_wait_o(perf_apb4_system_wait_o),
+      .perf_sdram_wait_o      (perf_sdram_wait_o),
+      .perf_psram_wait_o      (perf_psram_wait_o),
+      .perf_flash_wait_o      (perf_flash_wait_o)
   );
 
 `ifdef HAVE_SRAM_IF

rtl/mini/top/axi4_interconnect.sv

@@ -12,8 +12,8 @@ module axi4_interconnect #(
 ) (
     input  logic                 clk_i,
     input  logic                 rst_n_i,
-           axi4_if.slave         masters          [NumMasters],
-           axi4_if.master        targets          [NumTargets],
+           axi4_if.slave         masters                [NumMasters],
+           axi4_if.master        targets                [NumTargets],
     input  logic                 user_bus_enable_i,
     output logic                 user_bus_idle_o,
     input  logic                 perf_enable_i,
@@ -28,8 +28,8 @@ module axi4_interconnect #(
     output logic          [63:0] perf_mgmt_wait_o,
     output logic          [63:0] perf_user_wait_o,
     output logic          [63:0] perf_dma_wait_o,
-    output logic          [63:0] perf_apb4_wait_o,
-    output logic          [63:0] perf_apb_wait_o,
+    output logic          [63:0] perf_apb4_periph_wait_o,
+    output logic          [63:0] perf_apb4_system_wait_o,
     output logic          [63:0] perf_sdram_wait_o,
     output logic          [63:0] perf_psram_wait_o,
     output logic          [63:0] perf_flash_wait_o
@@ -38,7 +38,7 @@ module axi4_interconnect #(
   localparam int TARGET_WIDTH = $clog2(NumTargets);
 
   localparam logic [TARGET_WIDTH-1:0] TARGET_CFG = TARGET_WIDTH'(0);
-  localparam logic [TARGET_WIDTH-1:0] TARGET_APB = TARGET_WIDTH'(1);
+  localparam logic [TARGET_WIDTH-1:0] TARGET_APB4_SYSTEM = TARGET_WIDTH'(1);
   localparam logic [TARGET_WIDTH-1:0] TARGET_RAM = TARGET_WIDTH'(2);
   localparam logic [TARGET_WIDTH-1:0] TARGET_SDRAM = TARGET_WIDTH'(3);
   localparam logic [TARGET_WIDTH-1:0] TARGET_PSRAM = TARGET_WIDTH'(4);
@@ -150,9 +150,9 @@ module axi4_interconnect #(
     if (`SOC_ADDR_IS_PSRAM(addr)) return TARGET_PSRAM;
     if (`SOC_ADDR_IS_FLASH(addr) || `SOC_ADDR_IS_XPI(addr)) return TARGET_XPI;
     if (`SOC_ADDR_IS_SPISD(addr)) return TARGET_SPISD;
-    if (`SOC_ADDR_IS_APB(addr)) return TARGET_APB;
+    if (`SOC_ADDR_IS_APB4_SYSTEM(addr)) return TARGET_APB4_SYSTEM;
     if (`SOC_ADDR_IS_RAM(addr)) return TARGET_RAM;
-    if (`SOC_ADDR_IS_APB4(addr)) return TARGET_CFG;
+    if (`SOC_ADDR_IS_APB4_PERIPH(addr)) return TARGET_CFG;
     return TARGET_DECERR;
   endfunction
 
@@ -442,8 +442,8 @@ module axi4_interconnect #(
       ));
       s_capture_target[master] = decode_target(addr);
       if (!s_protocol_legal[master] ||
-          ((s_capture_target[master] == TARGET_CFG || s_capture_target[master] == TARGET_APB) &&
-           (len != 8'd0))) begin
+          ((s_capture_target[master] == TARGET_CFG ||
+            s_capture_target[master] == TARGET_APB4_SYSTEM) && (len != 8'd0))) begin
         s_capture_target[master] = TARGET_SLVERR;
       end else if (!s_access_allowed[master]) begin
         s_capture_target[master] = TARGET_SLVERR;
@@ -569,14 +569,14 @@ module axi4_interconnect #(
     end
   end
 
-  assign perf_mgmt_wait_o  = s_perf_master_wait[0];
-  assign perf_user_wait_o  = s_perf_master_wait[1];
-  assign perf_dma_wait_o   = s_perf_master_wait[2];
-  assign perf_apb4_wait_o  = s_perf_target_wait[TARGET_CFG];
-  assign perf_apb_wait_o   = s_perf_target_wait[TARGET_APB];
-  assign perf_sdram_wait_o = s_perf_target_wait[TARGET_SDRAM];
-  assign perf_psram_wait_o = s_perf_target_wait[TARGET_PSRAM];
-  assign perf_flash_wait_o = s_perf_target_wait[TARGET_XPI];
+  assign perf_mgmt_wait_o        = s_perf_master_wait[0];
+  assign perf_user_wait_o        = s_perf_master_wait[1];
+  assign perf_dma_wait_o         = s_perf_master_wait[2];
+  assign perf_apb4_periph_wait_o = s_perf_target_wait[TARGET_CFG];
+  assign perf_apb4_system_wait_o = s_perf_target_wait[TARGET_APB4_SYSTEM];
+  assign perf_sdram_wait_o       = s_perf_target_wait[TARGET_SDRAM];
+  assign perf_psram_wait_o       = s_perf_target_wait[TARGET_PSRAM];
+  assign perf_flash_wait_o       = s_perf_target_wait[TARGET_XPI];
 
 `ifndef SYNTHESIS
   initial begin

rtl/mini/top/retrosoc.sv

@@ -71,49 +71,49 @@ module retrosoc (
   ps2_if      u_ps2_if      ();
   // verilog_format: on
 
-  logic                             s_mgmt_debug_halted;
-  logic [`SOC_IRQ_VECTOR_WIDTH-1:0] s_irq;
-  logic [  `SOC_IRQ_APB4_WIDTH-1:0] s_apb4_irq;
-  logic [   `SOC_IRQ_APB_WIDTH-1:0] s_apb_irq;
-  logic                             s_bus_fault_valid;
-  logic [                     31:0] s_bus_fault_addr;
-  logic [                      3:0] s_bus_fault_wstrb;
-  logic                             s_bus_fault_reserved;
-  logic                             s_bus_fault_access;
-  logic [                      1:0] s_bus_fault_master;
-  logic [                      2:0] s_bus_fault_code;
-  logic                             s_perf_en;
-  logic                             s_perf_clear;
-  logic [                     63:0] s_perf_mgmt_wait;
-  logic [                     63:0] s_perf_user_wait;
-  logic [                     63:0] s_perf_dma_wait;
-  logic [                     63:0] s_perf_apb4_wait;
-  logic [                     63:0] s_perf_apb_wait;
-  logic [                     63:0] s_perf_sdram_wait;
-  logic [                     63:0] s_perf_psram_wait;
-  logic [                     63:0] s_perf_flash_wait;
-  logic [`SOC_IRQ_VECTOR_WIDTH-1:0] s_user_irq;
-  logic                             s_rtc_wake;
+  logic                                  s_mgmt_debug_halted;
+  logic [     `SOC_IRQ_VECTOR_WIDTH-1:0] s_irq;
+  logic [`SOC_IRQ_APB4_PERIPH_WIDTH-1:0] s_apb4_periph_irq;
+  logic [`SOC_IRQ_APB4_SYSTEM_WIDTH-1:0] s_apb4_system_irq;
+  logic                                  s_bus_fault_valid;
+  logic [                          31:0] s_bus_fault_addr;
+  logic [                           3:0] s_bus_fault_wstrb;
+  logic                                  s_bus_fault_reserved;
+  logic                                  s_bus_fault_access;
+  logic [                           1:0] s_bus_fault_master;
+  logic [                           2:0] s_bus_fault_code;
+  logic                                  s_perf_en;
+  logic                                  s_perf_clear;
+  logic [                          63:0] s_perf_mgmt_wait;
+  logic [                          63:0] s_perf_user_wait;
+  logic [                          63:0] s_perf_dma_wait;
+  logic [                          63:0] s_perf_apb4_periph_wait;
+  logic [                          63:0] s_perf_apb4_system_wait;
+  logic [                          63:0] s_perf_sdram_wait;
+  logic [                          63:0] s_perf_psram_wait;
+  logic [                          63:0] s_perf_flash_wait;
+  logic [     `SOC_IRQ_VECTOR_WIDTH-1:0] s_user_irq;
+  logic                                  s_rtc_wake;
 
-  assign u_sysctrl_if.fault_access_i    = s_bus_fault_access;
-  assign u_sysctrl_if.fault_master_i    = s_bus_fault_master;
-  assign u_sysctrl_if.fault_code_i      = s_bus_fault_code;
-  assign s_perf_en                      = u_sysctrl_if.perf_enable_o;
-  assign s_perf_clear                   = u_sysctrl_if.perf_clear_o;
-  assign test_done_o                    = u_sysctrl_if.test_done_o;
-  assign test_pass_o                    = u_sysctrl_if.test_pass_o;
-  assign test_code_o                    = u_sysctrl_if.test_code_o;
-  assign u_sysctrl_if.perf_mgmt_wait_i  = s_perf_mgmt_wait;
-  assign u_sysctrl_if.perf_user_wait_i  = s_perf_user_wait;
-  assign u_sysctrl_if.perf_dma_wait_i   = s_perf_dma_wait;
-  assign u_sysctrl_if.perf_apb4_wait_i  = s_perf_apb4_wait;
-  assign u_sysctrl_if.perf_apb_wait_i   = s_perf_apb_wait;
-  assign u_sysctrl_if.perf_sdram_wait_i = s_perf_sdram_wait;
-  assign u_sysctrl_if.perf_psram_wait_i = s_perf_psram_wait;
-  assign u_sysctrl_if.perf_flash_wait_i = s_perf_flash_wait;
-  assign u_sysctrl_if.rtc_wake_i        = s_rtc_wake;
-  assign u_uart0_if.rx_i                = uart_rx_i;
-  assign uart_tx_o                      = u_uart0_if.tx_o;
+  assign u_sysctrl_if.fault_access_i          = s_bus_fault_access;
+  assign u_sysctrl_if.fault_master_i          = s_bus_fault_master;
+  assign u_sysctrl_if.fault_code_i            = s_bus_fault_code;
+  assign s_perf_en                            = u_sysctrl_if.perf_enable_o;
+  assign s_perf_clear                         = u_sysctrl_if.perf_clear_o;
+  assign test_done_o                          = u_sysctrl_if.test_done_o;
+  assign test_pass_o                          = u_sysctrl_if.test_pass_o;
+  assign test_code_o                          = u_sysctrl_if.test_code_o;
+  assign u_sysctrl_if.perf_mgmt_wait_i        = s_perf_mgmt_wait;
+  assign u_sysctrl_if.perf_user_wait_i        = s_perf_user_wait;
+  assign u_sysctrl_if.perf_dma_wait_i         = s_perf_dma_wait;
+  assign u_sysctrl_if.perf_apb4_periph_wait_i = s_perf_apb4_periph_wait;
+  assign u_sysctrl_if.perf_apb4_system_wait_i = s_perf_apb4_system_wait;
+  assign u_sysctrl_if.perf_sdram_wait_i       = s_perf_sdram_wait;
+  assign u_sysctrl_if.perf_psram_wait_i       = s_perf_psram_wait;
+  assign u_sysctrl_if.perf_flash_wait_i       = s_perf_flash_wait;
+  assign u_sysctrl_if.rtc_wake_i              = s_rtc_wake;
+  assign u_uart0_if.rx_i                      = uart_rx_i;
+  assign uart_tx_o                            = u_uart0_if.tx_o;
 
   gpio_pad_bridge u_gpio_pad_bridge (
       .inner(u_gpio_if),
@@ -150,35 +150,35 @@ core_wrapper u_core_wrapper (
   );
 
   axi4_bus u_bus (
-      .clk_i            (clk_i),
-      .rst_n_i          (rst_n_i),
+      .clk_i                  (clk_i),
+      .rst_n_i                (rst_n_i),
 `ifdef HAVE_SRAM_IF
-      .ram              (ram),
+      .ram                    (ram),
 `endif
-      .user_bus_enable_i(u_sysctrl_if.user_bus_enable_o),
-      .user_bus_idle_o  (u_sysctrl_if.user_bus_idle_i),
+      .user_bus_enable_i      (u_sysctrl_if.user_bus_enable_o),
+      .user_bus_idle_o        (u_sysctrl_if.user_bus_idle_i),
       `include "soc_bus_fabric.svh"
-      .sdram_axi4       (u_sdram_axi4_if),
-      .psram_axi4       (u_psram_axi4_if),
-      .xpi_axi4         (u_xpi_axi4_if),
-      .spisd_axi4       (u_spisd_axi4_if),
-      .perf_enable_i    (s_perf_en),
-      .perf_clear_i     (s_perf_clear),
-      .fault_valid_o    (s_bus_fault_valid),
-      .fault_addr_o     (s_bus_fault_addr),
-      .fault_wstrb_o    (s_bus_fault_wstrb),
-      .fault_reserved_o (s_bus_fault_reserved),
-      .fault_access_o   (s_bus_fault_access),
-      .fault_master_o   (s_bus_fault_master),
-      .fault_code_o     (s_bus_fault_code),
-      .perf_mgmt_wait_o (s_perf_mgmt_wait),
-      .perf_user_wait_o (s_perf_user_wait),
-      .perf_dma_wait_o  (s_perf_dma_wait),
-      .perf_apb4_wait_o (s_perf_apb4_wait),
-      .perf_apb_wait_o  (s_perf_apb_wait),
-      .perf_sdram_wait_o(s_perf_sdram_wait),
-      .perf_psram_wait_o(s_perf_psram_wait),
-      .perf_flash_wait_o(s_perf_flash_wait)
+      .sdram_axi4             (u_sdram_axi4_if),
+      .psram_axi4             (u_psram_axi4_if),
+      .xpi_axi4               (u_xpi_axi4_if),
+      .spisd_axi4             (u_spisd_axi4_if),
+      .perf_enable_i          (s_perf_en),
+      .perf_clear_i           (s_perf_clear),
+      .fault_valid_o          (s_bus_fault_valid),
+      .fault_addr_o           (s_bus_fault_addr),
+      .fault_wstrb_o          (s_bus_fault_wstrb),
+      .fault_reserved_o       (s_bus_fault_reserved),
+      .fault_access_o         (s_bus_fault_access),
+      .fault_master_o         (s_bus_fault_master),
+      .fault_code_o           (s_bus_fault_code),
+      .perf_mgmt_wait_o       (s_perf_mgmt_wait),
+      .perf_user_wait_o       (s_perf_user_wait),
+      .perf_dma_wait_o        (s_perf_dma_wait),
+      .perf_apb4_periph_wait_o(s_perf_apb4_periph_wait),
+      .perf_apb4_system_wait_o(s_perf_apb4_system_wait),
+      .perf_sdram_wait_o      (s_perf_sdram_wait),
+      .perf_psram_wait_o      (s_perf_psram_wait),
+      .perf_flash_wait_o      (s_perf_flash_wait)
   );
 
   apb4_periph u_apb4_periph (
@@ -212,7 +212,7 @@ core_wrapper u_core_wrapper (
       .fault_addr_i    (s_bus_fault_addr),
       .fault_wstrb_i   (s_bus_fault_wstrb),
       .fault_reserved_i(s_bus_fault_reserved),
-      .irq_o           (s_apb4_irq)
+      .irq_o           (s_apb4_periph_irq)
   );
 
   axi4_sdram u_axi4_sdram (
@@ -229,14 +229,14 @@ core_wrapper u_core_wrapper (
       .clk_aud_i      (clk_aud_i),
       .rst_aud_n_i    (rst_aud_n_i),
       .debug_halted_i (s_mgmt_debug_halted),
-      `include "soc_apb4_system_fabric.svh"
+      `include "apb4_system_fabric.svh"
       .pwm            (u_pwm_if),
       .ps2            (u_ps2_if),
       .ip_sel_i       (u_sysctrl_if.ip_sel_o),
       .user_gpio      (u_user_gpio_if),
       .rtc_wake_o     (s_rtc_wake),
       .wdg_reset_req_o(wdg_reset_req_o),
-      .irq_o          (s_apb_irq)
+      .irq_o          (s_apb4_system_irq)
   );
 
 endmodule

rtl/mini/top/rib2apb.sv

@@ -16,7 +16,7 @@ module rib2apb (
     input  logic       clk_i,
     input  logic       rst_n_i,
     rib_if.slave       rib,
-`include "soc_apb_ports.svh"
+`include "apb4_system_ports.svh"
     // verilog_format: on
 );
 
@@ -42,7 +42,7 @@ module rib2apb (
   logic [RSP_WIDTH-1:0] s_rsp_input_data, s_rsp_output_data;
 
   // Registered slave-select one-hot and APB response mux.
-  `include "soc_apb_declarations.svh"
+  `include "apb4_system_declarations.svh"
 
   assign s_cmd_hdshk   = rib.cmd_valid && rib.cmd_ready;
   assign s_decode_addr = rib.cmd_addr;
@@ -54,9 +54,9 @@ module rib2apb (
   assign s_xfer_valid  = (s_fsm_q == FSM_SETP) || (s_fsm_q == FSM_ENAB);
 
   // Generated APB routing uses the latched RIB request and selected target.
-  `include "soc_apb_request_routes.svh"
-  `include "soc_apb_select_routes.svh"
-  `include "soc_apb_response_mux.svh"
+  `include "apb4_system_request_routes.svh"
+  `include "apb4_system_select_routes.svh"
+  `include "apb4_system_response_mux.svh"
 
   assign s_psel_valid = |s_psel_comb;
 

rtl/mini/top/rib_bus.sv

@@ -37,8 +37,8 @@ module rib_bus (
     output logic [63:0] perf_mgmt_wait_o,
     output logic [63:0] perf_user_wait_o,
     output logic [63:0] perf_dma_wait_o,
-    output logic [63:0] perf_apb4_wait_o,
-    output logic [63:0] perf_apb_wait_o,
+    output logic [63:0] perf_apb4_periph_wait_o,
+    output logic [63:0] perf_apb4_system_wait_o,
     output logic [63:0] perf_sdram_wait_o,
     output logic [63:0] perf_psram_wait_o,
     output logic [63:0] perf_flash_wait_o
@@ -49,8 +49,8 @@ module rib_bus (
   localparam logic [1:0] MSTR_USER = 2'd1;
   localparam logic [1:0] MSTR_DMA = 2'd2;
 
-  localparam logic [1:0] TARGET_RIBP = 2'd0;
-  localparam logic [1:0] TARGET_APB = 2'd1;
+  localparam logic [1:0] TARGET_APB4_PERIPH = 2'd0;
+  localparam logic [1:0] TARGET_APB4_SYSTEM = 2'd1;
   localparam logic [1:0] TARGET_RAM = 2'd2;
   localparam logic [1:0] TARGET_FAULT = 2'd3;
 
@@ -65,7 +65,7 @@ module rib_bus (
   logic [1:0] s_target_d, s_target_q;
   logic s_user_req;
   logic s_terminal_rsp;
-  logic s_ribp_sel, s_apb_sel, s_ram_sel, s_fault_sel;
+  logic s_apb4_periph_sel, s_apb4_system_sel, s_ram_sel, s_fault_sel;
   logic s_access_denied, s_burst_legal, s_len_legal;
   logic        s_user_access_allowed;
   logic [31:0] s_last_addr;
@@ -82,8 +82,8 @@ module rib_bus (
   logic [63:0] s_perf_mgmt_wait_d, s_perf_mgmt_wait_q;
   logic [63:0] s_perf_user_wait_d, s_perf_user_wait_q;
   logic [63:0] s_perf_dma_wait_d, s_perf_dma_wait_q;
-  logic [63:0] s_perf_apb4_wait_d, s_perf_apb4_wait_q;
-  logic [63:0] s_perf_apb_wait_d, s_perf_apb_wait_q;
+  logic [63:0] s_perf_apb4_periph_wait_d, s_perf_apb4_periph_wait_q;
+  logic [63:0] s_perf_apb4_system_wait_d, s_perf_apb4_system_wait_q;
   logic [63:0] s_perf_sdram_wait_d, s_perf_sdram_wait_q;
   logic [63:0] s_perf_psram_wait_d, s_perf_psram_wait_q;
   logic [63:0] s_perf_flash_wait_d, s_perf_flash_wait_q;
@@ -322,11 +322,11 @@ module rib_bus (
   assign s_access_denied = (s_mstr_id_q == MSTR_USER) && ~s_user_access_allowed;
 
   // verilog_format: off -- preserve reviewed column alignment
-  assign s_ribp_sel = u_mstr_rib_if.cmd_valid && ~s_cmd_accepted_q && ~s_access_denied &&
+  assign s_apb4_periph_sel = u_mstr_rib_if.cmd_valid && ~s_cmd_accepted_q && ~s_access_denied &&
                      s_burst_legal && `SOC_ADDR_IS_RIB_LEGACY_TARGET(u_mstr_rib_if.cmd_addr);
-  assign s_apb_sel = u_mstr_rib_if.cmd_valid && ~s_cmd_accepted_q && ~s_access_denied &&
+  assign s_apb4_system_sel = u_mstr_rib_if.cmd_valid && ~s_cmd_accepted_q && ~s_access_denied &&
                      (u_mstr_rib_if.cmd_len == `RIB_LEN_INCR1) &&
-                     `SOC_ADDR_IS_APB(u_mstr_rib_if.cmd_addr);
+                     `SOC_ADDR_IS_APB4_SYSTEM(u_mstr_rib_if.cmd_addr);
 `ifdef HAVE_SRAM_IF
   assign s_ram_sel = u_mstr_rib_if.cmd_valid && ~s_cmd_accepted_q && ~s_access_denied &&
                      s_burst_legal && `SOC_ADDR_IS_RAM(u_mstr_rib_if.cmd_addr);
@@ -334,7 +334,7 @@ module rib_bus (
   assign s_ram_sel = 1'b0;
 `endif
   assign s_fault_sel = u_mstr_rib_if.cmd_valid && ~s_cmd_accepted_q &&
-                       ~(s_ribp_sel || s_apb_sel || s_ram_sel);
+                       ~(s_apb4_periph_sel || s_apb4_system_sel || s_ram_sel);
   // verilog_format: on
 
   always_comb begin
@@ -345,10 +345,10 @@ module rib_bus (
       s_fault_code = `RIB_RESP_RESERVED;
       // verilog_format: off -- preserve reviewed column alignment
     end else if ((`SOC_ADDR_IS_RIB_LEGACY_TARGET(u_mstr_rib_if.cmd_addr) ||
-                  `SOC_ADDR_IS_APB(u_mstr_rib_if.cmd_addr) ||
+                  `SOC_ADDR_IS_APB4_SYSTEM(u_mstr_rib_if.cmd_addr) ||
                   `SOC_ADDR_IS_RAM(u_mstr_rib_if.cmd_addr)) &&
                  (~s_burst_legal ||
-                  (`SOC_ADDR_IS_APB(u_mstr_rib_if.cmd_addr) &&
+                  (`SOC_ADDR_IS_APB4_SYSTEM(u_mstr_rib_if.cmd_addr) &&
                    (u_mstr_rib_if.cmd_len != `RIB_LEN_INCR1)))) begin
       // verilog_format: on
       s_fault_code = `RIB_RESP_BURSTERR;
@@ -356,11 +356,11 @@ module rib_bus (
   end
 
   // Command routing. Target selection is captured on command acceptance.
-  assign rib.cmd_valid            = s_ribp_sel;
+  assign rib.cmd_valid            = s_apb4_periph_sel;
   assign rib.cmd_addr             = u_mstr_rib_if.cmd_addr;
   assign rib.cmd_write            = u_mstr_rib_if.cmd_write;
   assign rib.cmd_len              = u_mstr_rib_if.cmd_len;
-  assign apb_rib.cmd_valid        = s_apb_sel;
+  assign apb_rib.cmd_valid        = s_apb4_system_sel;
   assign apb_rib.cmd_addr         = u_mstr_rib_if.cmd_addr;
   assign apb_rib.cmd_write        = u_mstr_rib_if.cmd_write;
   assign apb_rib.cmd_len          = u_mstr_rib_if.cmd_len;
@@ -375,9 +375,9 @@ module rib_bus (
 
   always_comb begin
     u_mstr_rib_if.cmd_ready = 1'b0;
-    if (s_ribp_sel) begin
+    if (s_apb4_periph_sel) begin
       u_mstr_rib_if.cmd_ready = rib.cmd_ready;
-    end else if (s_apb_sel) begin
+    end else if (s_apb4_system_sel) begin
       u_mstr_rib_if.cmd_ready = apb_rib.cmd_ready;
     end else if (s_ram_sel) begin
       u_mstr_rib_if.cmd_ready = u_ram_rib_if.cmd_ready;
@@ -389,10 +389,10 @@ module rib_bus (
   always_comb begin
     s_target_d = s_target_q;
     if (u_mstr_rib_if.cmd_valid && u_mstr_rib_if.cmd_ready) begin
-      if (s_ribp_sel) begin
-        s_target_d = TARGET_RIBP;
-      end else if (s_apb_sel) begin
-        s_target_d = TARGET_APB;
+      if (s_apb4_periph_sel) begin
+        s_target_d = TARGET_APB4_PERIPH;
+      end else if (s_apb4_system_sel) begin
+        s_target_d = TARGET_APB4_SYSTEM;
       end else if (s_ram_sel) begin
         s_target_d = TARGET_RAM;
       end else begin
@@ -410,21 +410,21 @@ module rib_bus (
   );
 
   // Write-data and response routing uses the captured target.
-  assign rib.w_valid = s_mstr_lock_q && s_cmd_accepted_q && (s_target_q == TARGET_RIBP) ?
+  assign rib.w_valid = s_mstr_lock_q && s_cmd_accepted_q && (s_target_q == TARGET_APB4_PERIPH) ?
                        u_mstr_rib_if.w_valid : 1'b0;
   assign rib.wdata = u_mstr_rib_if.wdata;
   assign rib.wstrb = u_mstr_rib_if.wstrb;
   assign rib.wlast = u_mstr_rib_if.wlast;
-  assign rib.rsp_ready = s_mstr_lock_q && s_cmd_accepted_q && (s_target_q == TARGET_RIBP) ?
+  assign rib.rsp_ready = s_mstr_lock_q && s_cmd_accepted_q && (s_target_q == TARGET_APB4_PERIPH) ?
                          u_mstr_rib_if.rsp_ready : 1'b0;
 
   assign apb_rib.w_valid = s_mstr_lock_q && s_cmd_accepted_q &&
-                            (s_target_q == TARGET_APB) ? u_mstr_rib_if.w_valid : 1'b0;
+                            (s_target_q == TARGET_APB4_SYSTEM) ? u_mstr_rib_if.w_valid : 1'b0;
   assign apb_rib.wdata = u_mstr_rib_if.wdata;
   assign apb_rib.wstrb = u_mstr_rib_if.wstrb;
   assign apb_rib.wlast = u_mstr_rib_if.wlast;
   assign apb_rib.rsp_ready = s_mstr_lock_q && s_cmd_accepted_q &&
-                              (s_target_q == TARGET_APB) ? u_mstr_rib_if.rsp_ready : 1'b0;
+                              (s_target_q == TARGET_APB4_SYSTEM) ? u_mstr_rib_if.rsp_ready : 1'b0;
 
   assign u_ram_rib_if.w_valid = s_mstr_lock_q && s_cmd_accepted_q &&
                                   (s_target_q == TARGET_RAM) ?
@@ -455,7 +455,7 @@ module rib_bus (
     u_mstr_rib_if.rsp_beat  = '0;
     u_mstr_rib_if.rsp_last  = 1'b0;
     unique case (s_target_q)
-      TARGET_RIBP: begin
+      TARGET_APB4_PERIPH: begin
         u_mstr_rib_if.w_ready   = s_cmd_accepted_q && rib.w_ready;
         u_mstr_rib_if.rsp_valid = s_cmd_accepted_q && rib.rsp_valid;
         u_mstr_rib_if.rdata     = rib.rdata;
@@ -464,7 +464,7 @@ module rib_bus (
         u_mstr_rib_if.rsp_beat  = rib.rsp_beat;
         u_mstr_rib_if.rsp_last  = rib.rsp_last;
       end
-      TARGET_APB: begin
+      TARGET_APB4_SYSTEM: begin
         u_mstr_rib_if.w_ready   = s_cmd_accepted_q && apb_rib.w_ready;
         u_mstr_rib_if.rsp_valid = s_cmd_accepted_q && apb_rib.rsp_valid;
         u_mstr_rib_if.rdata     = apb_rib.rdata;
@@ -566,31 +566,35 @@ module rib_bus (
                             ~u_mstr_rib_if.rsp_valid));
 
   always_comb begin
-    s_perf_mgmt_wait_d  = s_perf_mgmt_wait_q;
-    s_perf_user_wait_d  = s_perf_user_wait_q;
-    s_perf_dma_wait_d   = s_perf_dma_wait_q;
-    s_perf_apb4_wait_d  = s_perf_apb4_wait_q;
-    s_perf_apb_wait_d   = s_perf_apb_wait_q;
-    s_perf_sdram_wait_d = s_perf_sdram_wait_q;
-    s_perf_psram_wait_d = s_perf_psram_wait_q;
-    s_perf_flash_wait_d = s_perf_flash_wait_q;
+    s_perf_mgmt_wait_d        = s_perf_mgmt_wait_q;
+    s_perf_user_wait_d        = s_perf_user_wait_q;
+    s_perf_dma_wait_d         = s_perf_dma_wait_q;
+    s_perf_apb4_periph_wait_d = s_perf_apb4_periph_wait_q;
+    s_perf_apb4_system_wait_d = s_perf_apb4_system_wait_q;
+    s_perf_sdram_wait_d       = s_perf_sdram_wait_q;
+    s_perf_psram_wait_d       = s_perf_psram_wait_q;
+    s_perf_flash_wait_d       = s_perf_flash_wait_q;
     if (perf_clear_i) begin
-      s_perf_mgmt_wait_d  = '0;
-      s_perf_user_wait_d  = '0;
-      s_perf_dma_wait_d   = '0;
-      s_perf_apb4_wait_d  = '0;
-      s_perf_apb_wait_d   = '0;
-      s_perf_sdram_wait_d = '0;
-      s_perf_psram_wait_d = '0;
-      s_perf_flash_wait_d = '0;
+      s_perf_mgmt_wait_d        = '0;
+      s_perf_user_wait_d        = '0;
+      s_perf_dma_wait_d         = '0;
+      s_perf_apb4_periph_wait_d = '0;
+      s_perf_apb4_system_wait_d = '0;
+      s_perf_sdram_wait_d       = '0;
+      s_perf_psram_wait_d       = '0;
+      s_perf_flash_wait_d       = '0;
     end else if (perf_enable_i && s_xfer_stalled) begin
       unique case (s_mstr_id_q)
         MSTR_MGMT: s_perf_mgmt_wait_d = s_perf_mgmt_wait_q + 1'b1;
         MSTR_USER: s_perf_user_wait_d = s_perf_user_wait_q + 1'b1;
         default:   s_perf_dma_wait_d = s_perf_dma_wait_q + 1'b1;
       endcase
-      if (s_target_q == TARGET_RIBP) s_perf_apb4_wait_d = s_perf_apb4_wait_q + 1'b1;
-      if (s_target_q == TARGET_APB) s_perf_apb_wait_d = s_perf_apb_wait_q + 1'b1;
+      if (s_target_q == TARGET_APB4_PERIPH) begin
+        s_perf_apb4_periph_wait_d = s_perf_apb4_periph_wait_q + 1'b1;
+      end
+      if (s_target_q == TARGET_APB4_SYSTEM) begin
+        s_perf_apb4_system_wait_d = s_perf_apb4_system_wait_q + 1'b1;
+      end
       if (`SOC_ADDR_IS_SDRAM(s_xfer_addr_q)) begin
         s_perf_sdram_wait_d = s_perf_sdram_wait_q + 1'b1;
       end
@@ -629,19 +633,19 @@ module rib_bus (
   );
   dffr #(
       .DATA_WIDTH(64)
-  ) u_perf_apb4_wait_dffr (
+  ) u_perf_apb4_periph_wait_dffr (
       .clk_i  (clk_i),
       .rst_n_i(rst_n_i),
-      .dat_i  (s_perf_apb4_wait_d),
-      .dat_o  (s_perf_apb4_wait_q)
+      .dat_i  (s_perf_apb4_periph_wait_d),
+      .dat_o  (s_perf_apb4_periph_wait_q)
   );
   dffr #(
       .DATA_WIDTH(64)
-  ) u_perf_apb_wait_dffr (
+  ) u_perf_apb4_system_wait_dffr (
       .clk_i  (clk_i),
       .rst_n_i(rst_n_i),
-      .dat_i  (s_perf_apb_wait_d),
-      .dat_o  (s_perf_apb_wait_q)
+      .dat_i  (s_perf_apb4_system_wait_d),
+      .dat_o  (s_perf_apb4_system_wait_q)
   );
   dffr #(
       .DATA_WIDTH(64)
@@ -668,13 +672,13 @@ module rib_bus (
       .dat_o  (s_perf_flash_wait_q)
   );
 
-  assign perf_mgmt_wait_o  = s_perf_mgmt_wait_q;
-  assign perf_user_wait_o  = s_perf_user_wait_q;
-  assign perf_dma_wait_o   = s_perf_dma_wait_q;
-  assign perf_apb4_wait_o  = s_perf_apb4_wait_q;
-  assign perf_apb_wait_o   = s_perf_apb_wait_q;
-  assign perf_sdram_wait_o = s_perf_sdram_wait_q;
-  assign perf_psram_wait_o = s_perf_psram_wait_q;
-  assign perf_flash_wait_o = s_perf_flash_wait_q;
+  assign perf_mgmt_wait_o        = s_perf_mgmt_wait_q;
+  assign perf_user_wait_o        = s_perf_user_wait_q;
+  assign perf_dma_wait_o         = s_perf_dma_wait_q;
+  assign perf_apb4_periph_wait_o = s_perf_apb4_periph_wait_q;
+  assign perf_apb4_system_wait_o = s_perf_apb4_system_wait_q;
+  assign perf_sdram_wait_o       = s_perf_sdram_wait_q;
+  assign perf_psram_wait_o       = s_perf_psram_wait_q;
+  assign perf_flash_wait_o       = s_perf_flash_wait_q;
 
 endmodule

rtl/rtl_style_audit.json

@@ -206,8 +206,8 @@
       "apb4_if_bridge.sv",
       "apb4_periph.sv",
       "apb4_system.sv",
-      "axi42apb.sv",
-      "axi42apb_periph.sv",
+      "axi42apb4_system.sv",
+      "axi42apb4_periph.sv",
       "axi42ram.sv",
       "axi42ribp.sv",
       "axi42ribp_burst.sv",
@@ -245,7 +245,9 @@
       "user_extensions.svh",
       "user_ip_design_template.sv",
       "user_ip_top.sv",
-      "user_ip_wrapper.sv"
+      "user_ip_wrapper.sv",
+      "axi42apb4.svh",
+      "axi42apb4_state.svh"
     ]
   },
   "reviewed_boundaries": [

scripts/parse_performance_log.py

@@ -20,7 +20,7 @@ REQUIRED_FIELDS = {
     "checksum",
     "cycles",
     "mgmt_wait",
-    "apb4_wait",
+    "apb4_periph_wait",
     "sdram_wait",
     "psram_wait",
     "flash_wait",

tests/rtl/axi4_interconnect_tb.sv

@@ -44,29 +44,29 @@ module axi4_interconnect_tb;
       .NumMasters(NumMasters),
       .NumTargets(NumTargets)
   ) u_dut (
-      .clk_i            (clk_i),
-      .rst_n_i          (rst_n_i),
-      .masters          (masters),
-      .targets          (targets),
-      .user_bus_enable_i(1'b1),
-      .user_bus_idle_o  (user_bus_idle_o),
-      .perf_enable_i    (1'b0),
-      .perf_clear_i     (1'b0),
-      .fault_valid_o    (fault_valid_o),
-      .fault_addr_o     (fault_addr_o),
-      .fault_wstrb_o    (fault_wstrb_o),
-      .fault_reserved_o (fault_reserved_o),
-      .fault_access_o   (fault_access_o),
-      .fault_master_o   (fault_master_o),
-      .fault_code_o     (fault_code_o),
-      .perf_mgmt_wait_o (),
-      .perf_user_wait_o (),
-      .perf_dma_wait_o  (),
-      .perf_apb4_wait_o (),
-      .perf_apb_wait_o  (),
-      .perf_sdram_wait_o(),
-      .perf_psram_wait_o(),
-      .perf_flash_wait_o()
+      .clk_i                  (clk_i),
+      .rst_n_i                (rst_n_i),
+      .masters                (masters),
+      .targets                (targets),
+      .user_bus_enable_i      (1'b1),
+      .user_bus_idle_o        (user_bus_idle_o),
+      .perf_enable_i          (1'b0),
+      .perf_clear_i           (1'b0),
+      .fault_valid_o          (fault_valid_o),
+      .fault_addr_o           (fault_addr_o),
+      .fault_wstrb_o          (fault_wstrb_o),
+      .fault_reserved_o       (fault_reserved_o),
+      .fault_access_o         (fault_access_o),
+      .fault_master_o         (fault_master_o),
+      .fault_code_o           (fault_code_o),
+      .perf_mgmt_wait_o       (),
+      .perf_user_wait_o       (),
+      .perf_dma_wait_o        (),
+      .perf_apb4_periph_wait_o(),
+      .perf_apb4_system_wait_o(),
+      .perf_sdram_wait_o      (),
+      .perf_psram_wait_o      (),
+      .perf_flash_wait_o      ()
   );
 
   for (genvar target = 0; target < NumTargets; target++) begin : GEN_TARGETS

tests/rtl/rib_bus_tb.sv

@@ -67,32 +67,32 @@ module rib_bus_tb;
   assign apb_rib.rsp_last  = 1'b1;
 
   rib_bus u_bus (
-      .clk_i            (clk_i),
-      .rst_n_i          (rst_n_i),
-      .mgmt_rib         (mgmt_rib),
-      .user_rib         (user_rib),
-      .dma_rib          (dma_rib),
-      .user_bus_enable_i(1'b1),
-      .user_bus_idle_o  (user_bus_idle_o),
-      .rib              (rib),
-      .apb_rib          (apb_rib),
-      .perf_enable_i    (1'b0),
-      .perf_clear_i     (1'b0),
-      .fault_valid_o    (fault_valid_o),
-      .fault_addr_o     (),
-      .fault_wstrb_o    (),
-      .fault_reserved_o (),
-      .fault_access_o   (),
-      .fault_master_o   (),
-      .fault_code_o     (fault_code_o),
-      .perf_mgmt_wait_o (),
-      .perf_user_wait_o (),
-      .perf_dma_wait_o  (),
-      .perf_apb4_wait_o (),
-      .perf_apb_wait_o  (),
-      .perf_sdram_wait_o(),
-      .perf_psram_wait_o(),
-      .perf_flash_wait_o()
+      .clk_i                  (clk_i),
+      .rst_n_i                (rst_n_i),
+      .mgmt_rib               (mgmt_rib),
+      .user_rib               (user_rib),
+      .dma_rib                (dma_rib),
+      .user_bus_enable_i      (1'b1),
+      .user_bus_idle_o        (user_bus_idle_o),
+      .rib                    (rib),
+      .apb_rib                (apb_rib),
+      .perf_enable_i          (1'b0),
+      .perf_clear_i           (1'b0),
+      .fault_valid_o          (fault_valid_o),
+      .fault_addr_o           (),
+      .fault_wstrb_o          (),
+      .fault_reserved_o       (),
+      .fault_access_o         (),
+      .fault_master_o         (),
+      .fault_code_o           (fault_code_o),
+      .perf_mgmt_wait_o       (),
+      .perf_user_wait_o       (),
+      .perf_dma_wait_o        (),
+      .perf_apb4_periph_wait_o(),
+      .perf_apb4_system_wait_o(),
+      .perf_sdram_wait_o      (),
+      .perf_psram_wait_o      (),
+      .perf_flash_wait_o      ()
   );
 
   task automatic issue_read(input logic [31:0] address, input logic [1:0] length,

tests/rtl/soc_irq_topology_tb.sv

@@ -3,9 +3,9 @@
 `include "soc_irq_config.svh"
 
 module soc_irq_topology_tb;
-  logic [`SOC_IRQ_VECTOR_WIDTH-1:0] s_irq;
-  logic [  `SOC_IRQ_APB4_WIDTH-1:0] s_apb4_irq;
-  logic [   `SOC_IRQ_APB_WIDTH-1:0] s_apb_irq;
+  logic [     `SOC_IRQ_VECTOR_WIDTH-1:0] s_irq;
+  logic [`SOC_IRQ_APB4_PERIPH_WIDTH-1:0] s_apb4_periph_irq;
+  logic [`SOC_IRQ_APB4_SYSTEM_WIDTH-1:0] s_apb4_system_irq;
 
   `include "soc_irq_wiring.svh"
 
@@ -19,30 +19,30 @@ module soc_irq_topology_tb;
   endtask
 
   initial begin
-    s_apb4_irq = '0;
-    s_apb_irq  = '0;
+    s_apb4_periph_irq = '0;
+    s_apb4_system_irq = '0;
     expect_irq('0);
 
     for (int bit_index = 0; bit_index < 10; bit_index++) begin
-      s_apb4_irq            = '0;
-      s_apb4_irq[bit_index] = 1'b1;
-      s_apb_irq             = '0;
+      s_apb4_periph_irq            = '0;
+      s_apb4_periph_irq[bit_index] = 1'b1;
+      s_apb4_system_irq            = '0;
       expect_irq(32'd1 << bit_index);
     end
 
-    for (int bit_index = 10; bit_index < `SOC_IRQ_APB4_WIDTH; bit_index++) begin
-      s_apb4_irq            = '0;
-      s_apb4_irq[bit_index] = 1'b1;
+    for (int bit_index = 10; bit_index < `SOC_IRQ_APB4_PERIPH_WIDTH; bit_index++) begin
+      s_apb4_periph_irq            = '0;
+      s_apb4_periph_irq[bit_index] = 1'b1;
       case (bit_index)
         13:      expect_irq(32'd1 << 15);
         default: expect_irq(32'd1 << (bit_index + 7));
       endcase
     end
 
-    for (int bit_index = 0; bit_index < `SOC_IRQ_APB_WIDTH; bit_index++) begin
-      s_apb4_irq           = '0;
-      s_apb_irq            = '0;
-      s_apb_irq[bit_index] = 1'b1;
+    for (int bit_index = 0; bit_index < `SOC_IRQ_APB4_SYSTEM_WIDTH; bit_index++) begin
+      s_apb4_periph_irq            = '0;
+      s_apb4_system_irq            = '0;
+      s_apb4_system_irq[bit_index] = 1'b1;
       case (bit_index)
         0:       expect_irq(32'd1 << 11);
         1:       expect_irq(32'd1 << 12);
@@ -53,7 +53,7 @@ module soc_irq_topology_tb;
       endcase
     end
 
-    s_apb_irq = '0;
+    s_apb4_system_irq = '0;
     expect_irq('0);
     if (s_irq[10] !== 1'b0) begin
       $fatal(1, "removed core IRQ bit is not low: IRQ10=%b", s_irq[10]);

tests/rtl/sysctrl_tb.sv

@@ -73,31 +73,31 @@ module sysctrl_tb;
 
   logic [31:0] read_data;
   initial begin
-    apb4.psel                   = 1'b0;
-    apb4.paddr                  = '0;
-    apb4.pwdata                 = '0;
-    apb4.pstrb                  = '0;
-    sysctrl.user_bus_idle_i     = 1'b1;
-    sysctrl.fault_access_i      = 1'b0;
-    sysctrl.fault_master_i      = '0;
-    sysctrl.fault_code_i        = `RIB_RESP_RESERVED;
-    sysctrl.perf_mgmt_wait_i    = 64'd11;
-    sysctrl.perf_user_wait_i    = 64'd12;
-    sysctrl.perf_dma_wait_i     = 64'd13;
-    sysctrl.perf_apb4_wait_i    = 64'd14;
-    sysctrl.perf_apb_wait_i     = 64'd15;
-    sysctrl.perf_sdram_wait_i   = 64'd16;
-    sysctrl.perf_psram_wait_i   = 64'd17;
-    sysctrl.perf_flash_wait_i   = 64'd18;
-    sysctrl.rtc_wake_i          = 1'b0;
-    pll_ctrl.req_ready_i        = 1'b1;
-    pll_ctrl.rsp_active_sel_i   = '0;
-    pll_ctrl.rsp_active_valid_i = 1'b0;
-    pll_ctrl.rsp_safe_clk_i     = 1'b1;
-    pll_ctrl.rsp_pll_lock_i     = 1'b0;
-    pll_ctrl.rsp_error_i        = '0;
-    pll_ctrl.rsp_valid_i        = 1'b0;
-    pll_ctrl.capable_i          = 1'b0;
+    apb4.psel                       = 1'b0;
+    apb4.paddr                      = '0;
+    apb4.pwdata                     = '0;
+    apb4.pstrb                      = '0;
+    sysctrl.user_bus_idle_i         = 1'b1;
+    sysctrl.fault_access_i          = 1'b0;
+    sysctrl.fault_master_i          = '0;
+    sysctrl.fault_code_i            = `RIB_RESP_RESERVED;
+    sysctrl.perf_mgmt_wait_i        = 64'd11;
+    sysctrl.perf_user_wait_i        = 64'd12;
+    sysctrl.perf_dma_wait_i         = 64'd13;
+    sysctrl.perf_apb4_periph_wait_i = 64'd14;
+    sysctrl.perf_apb4_system_wait_i = 64'd15;
+    sysctrl.perf_sdram_wait_i       = 64'd16;
+    sysctrl.perf_psram_wait_i       = 64'd17;
+    sysctrl.perf_flash_wait_i       = 64'd18;
+    sysctrl.rtc_wake_i              = 1'b0;
+    pll_ctrl.req_ready_i            = 1'b1;
+    pll_ctrl.rsp_active_sel_i       = '0;
+    pll_ctrl.rsp_active_valid_i     = 1'b0;
+    pll_ctrl.rsp_safe_clk_i         = 1'b1;
+    pll_ctrl.rsp_pll_lock_i         = 1'b0;
+    pll_ctrl.rsp_error_i            = '0;
+    pll_ctrl.rsp_valid_i            = 1'b0;
+    pll_ctrl.capable_i              = 1'b0;
     repeat (2) @(posedge clk_i);
     rst_n_i = 1'b1;
 

tests/test_memory_map.py

@@ -68,7 +68,7 @@ def test_generated_artifacts_share_the_capacity_baseline(tmp_path: Path) -> None
     assert "SOC_SYSCTRL_PLL_STATUS_OFFSET   32'h0000001C" in rtl
     assert "SOC_SYSCTRL_TEST_STATUS_OFFSET  32'h00000084" in rtl
     assert "SOC_SYSCTRL_RTC_WAKE_STATUS_OFFSET 32'h00000088" in rtl
-    assert "SOC_ADDR_IS_APB4(addr)" in rtl
+    assert "SOC_ADDR_IS_APB4_PERIPH(addr)" in rtl
     assert "SOC_ADDR_IS_NMI" not in rtl
     user_policy = rtl.split("`define SOC_USER_ADDR_READABLE", 1)[1].split(
         "`define SOC_ADDR_INCR4_CAPABLE", 1
@@ -98,8 +98,8 @@ def test_user_ip_is_always_emitted_for_the_fixed_platform(tmp_path: Path) -> Non
         "USER_IP": "20007000",
     }
     for symbol, base in expected_apb_bases.items():
-        assert f"`define SOC_ADDR_APB_{symbol}_BASE 32'h{base}" in rtl
-        assert f"#define RS_SOC_APB_{symbol}_BASE UINT32_C(0x{base})" in header
+        assert f"`define SOC_ADDR_APB4_{symbol}_BASE 32'h{base}" in rtl
+        assert f"#define RS_SOC_APB4_{symbol}_BASE UINT32_C(0x{base})" in header
     assert "APB_UART1" not in rtl
     assert "APB_UART1" not in header
     assert "APB_TMR" not in rtl

tests/test_performance_log.py

@@ -9,7 +9,7 @@ from scripts.parse_performance_log import parse_log
 def test_parse_log_requires_terminal_marker_and_complete_samples() -> None:
     report = parse_log(
         "PERF region=sdram op=read words=1024 checksum=0x1234 cycles=123 mgmt_wait=10 "
-        "apb4_wait=9 sdram_wait=8 psram_wait=0 flash_wait=0 dma_wait=0\n"
+        "apb4_periph_wait=9 sdram_wait=8 psram_wait=0 flash_wait=0 dma_wait=0\n"
         "PERF_BENCHMARK_PASS\n"
     )
 
@@ -23,7 +23,7 @@ def test_parse_log_requires_terminal_marker_and_complete_samples() -> None:
             "dma_wait": 0,
             "flash_wait": 0,
             "mgmt_wait": 10,
-            "apb4_wait": 9,
+            "apb4_periph_wait": 9,
             "operation": "read",
             "psram_wait": 0,
             "region": "sdram",
@@ -35,7 +35,7 @@ def test_parse_log_requires_terminal_marker_and_complete_samples() -> None:
 
 def test_parse_log_rejects_missing_benchmark_marker() -> None:
     report = parse_log(
-        "PERF region=flash op=read words=1024 checksum=0 cycles=10 mgmt_wait=1 apb4_wait=1 "
+        "PERF region=flash op=read words=1024 checksum=0 cycles=10 mgmt_wait=1 apb4_periph_wait=1 "
         "sdram_wait=0 psram_wait=0 flash_wait=1 dma_wait=0\n"
     )
 
@@ -45,7 +45,7 @@ def test_parse_log_rejects_missing_benchmark_marker() -> None:
 def test_parse_log_rejects_report_with_performance_failure() -> None:
     report = parse_log(
         "PERF region=sdram op=read words=1024 checksum=0x1234 cycles=123 mgmt_wait=10 "
-        "apb4_wait=9 sdram_wait=8 psram_wait=0 flash_wait=0 dma_wait=0\n"
+        "apb4_periph_wait=9 sdram_wait=8 psram_wait=0 flash_wait=0 dma_wait=0\n"
         "PERF_FAIL region=sdram op=read reason=data expected=1234 actual=0\n"
         "PERF_BENCHMARK_PASS\n"
     )

tests/test_soc_topology.py

@@ -60,16 +60,16 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -
     interfaces = (tmp_path / "rtl/apb4_periph_interfaces.svh").read_text(encoding="utf-8")
     routes = (tmp_path / "rtl/apb4_periph_select_routes.svh").read_text(encoding="utf-8")
     gpio = (tmp_path / "rtl/soc_gpio_alt_bindings.svh").read_text(encoding="utf-8")
-    apb_interfaces = (tmp_path / "rtl/soc_apb_interfaces.svh").read_text(encoding="utf-8")
-    apb_declarations = (tmp_path / "rtl/soc_apb_declarations.svh").read_text(encoding="utf-8")
-    apb_routes = (tmp_path / "rtl/soc_apb_request_routes.svh").read_text(encoding="utf-8")
-    apb_response = (tmp_path / "rtl/soc_apb_response_mux.svh").read_text(encoding="utf-8")
+    apb_interfaces = (tmp_path / "rtl/apb4_system_interfaces.svh").read_text(encoding="utf-8")
+    apb_declarations = (tmp_path / "rtl/apb4_system_declarations.svh").read_text(encoding="utf-8")
+    apb_routes = (tmp_path / "rtl/apb4_system_request_routes.svh").read_text(encoding="utf-8")
+    apb_response = (tmp_path / "rtl/apb4_system_response_mux.svh").read_text(encoding="utf-8")
     fabric = (tmp_path / "rtl/soc_fabric_interfaces.svh").read_text(encoding="utf-8")
     bus_fabric = (tmp_path / "rtl/soc_bus_fabric.svh").read_text(encoding="utf-8")
-    apb_system_fabric = (tmp_path / "rtl/soc_apb4_system_fabric.svh").read_text(encoding="utf-8")
+    apb_system_fabric = (tmp_path / "rtl/apb4_system_fabric.svh").read_text(encoding="utf-8")
     irq_config = (tmp_path / "rtl/soc_irq_config.svh").read_text(encoding="utf-8")
-    rib_irq = (tmp_path / "rtl/soc_apb4_irq_bindings.svh").read_text(encoding="utf-8")
-    apb_irq = (tmp_path / "rtl/soc_apb_irq_bindings.svh").read_text(encoding="utf-8")
+    rib_irq = (tmp_path / "rtl/apb4_periph_irq_bindings.svh").read_text(encoding="utf-8")
+    apb_irq = (tmp_path / "rtl/apb4_system_irq_bindings.svh").read_text(encoding="utf-8")
     irq_wiring = (tmp_path / "rtl/soc_irq_wiring.svh").read_text(encoding="utf-8")
     irq_sva = (tmp_path / "rtl/soc_irq_sva.svh").read_text(encoding="utf-8")
     filelist = (tmp_path / "soc_topology.fl").read_text(encoding="utf-8")
@@ -102,7 +102,7 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -
     assert "assign u_gpio_if.alt1_do_i[22] = u_psram_if.nss_o[0];" in gpio
     assert "s_tmr_capch" not in gpio
     assert apb_interfaces.count("apb4_if u_") == 8
-    assert "apb4_pure_if u_archinfo_apb_pure_if ();" in apb_interfaces
+    assert "apb4_pure_if u_archinfo_apb4_pure_if ();" in apb_interfaces
     assert "assign user_ip.paddr = s_addr_q;" in apb_routes
     assert "({32{s_psel_q[7]}} & user_ip.prdata)" in apb_response
     assert "localparam int NSLV = 8;" in apb_declarations
@@ -111,12 +111,12 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -
     assert ".user_axi4(u_user_axi4_if)" in bus_fabric
     assert ".dma_axi4(u_dma_axi4_if)" in bus_fabric
     assert ".cfg_axi4(u_cfg_axi4_if)" in bus_fabric
-    assert ".apb_axi4(u_apb_axi4_if)" in bus_fabric
-    assert ".axi4(u_apb_axi4_if)" in apb_system_fabric
+    assert ".system_axi4(u_system_axi4_if)" in bus_fabric
+    assert ".axi4(u_system_axi4_if)" in apb_system_fabric
     assert "`define SOC_IRQ_VECTOR_WIDTH 32" in irq_config
     assert "`define SOC_USER_IRQ_MASK 32'h000EFBFC" in irq_config
-    assert "`define SOC_IRQ_APB4_WIDTH 14" in irq_config
-    assert "`define SOC_IRQ_APB_WIDTH 5" in irq_config
+    assert "`define SOC_IRQ_APB4_PERIPH_WIDTH 14" in irq_config
+    assert "`define SOC_IRQ_APB4_SYSTEM_WIDTH 5" in irq_config
     assert "assign irq_o[0] = u_clint_if.software_irq_o[0];" in rib_irq
     assert "assign irq_o[10] = ws2812.irq_o;" in rib_irq
     assert "assign irq_o[11] = gpio.irq_o;" in rib_irq
@@ -125,10 +125,10 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -
     assert "assign irq_o[0] = pwm.irq_o;" in apb_irq
     assert "assign irq_o[4] = s_rng_irq;" in apb_irq
     assert "s_irq[10]" not in irq_wiring
-    assert "s_irq[15] = s_apb4_irq[13];" in irq_wiring
-    assert "s_irq[16] = s_apb_irq[4];" in irq_wiring
+    assert "s_irq[15] = s_apb4_periph_irq[13];" in irq_wiring
+    assert "s_irq[16] = s_apb4_system_irq[4];" in irq_wiring
     assert "irq_i[10] == 1'b0" in irq_sva
-    assert "irq_i[15] == apb4_irq_i[13]" in irq_sva
+    assert "irq_i[15] == apb4_periph_irq_i[13]" in irq_sva
     assert "irq_i[31] == 1'b0" in irq_sva
     assert "bind retrosoc soc_irq_topology_sva" in irq_sva
     assert filelist.startswith("+incdir+")
@@ -148,40 +148,40 @@ def test_topology_preserves_default_irq_compatibility_mapping() -> None:
         for interrupt in document["interrupts"]
     ]
     assert mappings == [
-        ("clint_software", "apb4", 0, 0, "u_clint_if.software_irq_o[0]"),
-        ("clint_timer", "apb4", 1, 1, "u_clint_if.timer_irq_o[0]"),
-        ("uart0", "apb4", 2, 2, "uart.irq_o"),
-        ("timer0", "apb4", 3, 3, "s_tim0_irq"),
-        ("timer1", "apb4", 4, 4, "s_tim1_irq"),
-        ("psram", "apb4", 5, 5, "psram.irq_o"),
-        ("spisd", "apb4", 6, 6, "spisd.irq_o"),
-        ("i2c0", "apb4", 7, 7, "i2c0.irq_o"),
-        ("i2s", "apb4", 8, 8, "i2s.irq_o"),
-        ("xpi", "apb4", 9, 9, "xpi.irq_o"),
-        ("pwm", "apb", 0, 11, "pwm.irq_o"),
-        ("ps2", "apb", 1, 12, "ps2.irq_o"),
-        ("rtc", "apb", 2, 13, "u_rtc_if.irq_o"),
-        ("watchdog_early_warning", "apb", 3, 14, "u_wdg_if.irq_o"),
-        ("rng", "apb", 4, 16, "s_rng_irq"),
-        ("ws2812", "apb4", 10, 17, "ws2812.irq_o"),
-        ("gpio", "apb4", 11, 18, "gpio.irq_o"),
-        ("i2c1", "apb4", 12, 19, "i2c1.irq_o"),
-        ("dvp", "apb4", 13, 15, "s_dvp_irq"),
+        ("clint_software", "apb4_periph", 0, 0, "u_clint_if.software_irq_o[0]"),
+        ("clint_timer", "apb4_periph", 1, 1, "u_clint_if.timer_irq_o[0]"),
+        ("uart0", "apb4_periph", 2, 2, "uart.irq_o"),
+        ("timer0", "apb4_periph", 3, 3, "s_tim0_irq"),
+        ("timer1", "apb4_periph", 4, 4, "s_tim1_irq"),
+        ("psram", "apb4_periph", 5, 5, "psram.irq_o"),
+        ("spisd", "apb4_periph", 6, 6, "spisd.irq_o"),
+        ("i2c0", "apb4_periph", 7, 7, "i2c0.irq_o"),
+        ("i2s", "apb4_periph", 8, 8, "i2s.irq_o"),
+        ("xpi", "apb4_periph", 9, 9, "xpi.irq_o"),
+        ("pwm", "apb4_system", 0, 11, "pwm.irq_o"),
+        ("ps2", "apb4_system", 1, 12, "ps2.irq_o"),
+        ("rtc", "apb4_system", 2, 13, "u_rtc_if.irq_o"),
+        ("watchdog_early_warning", "apb4_system", 3, 14, "u_wdg_if.irq_o"),
+        ("rng", "apb4_system", 4, 16, "s_rng_irq"),
+        ("ws2812", "apb4_periph", 10, 17, "ws2812.irq_o"),
+        ("gpio", "apb4_periph", 11, 18, "gpio.irq_o"),
+        ("i2c1", "apb4_periph", 12, 19, "i2c1.irq_o"),
+        ("dvp", "apb4_periph", 13, 15, "s_dvp_irq"),
     ]
 
 
 def test_topology_always_adds_the_user_apb_target(tmp_path: Path) -> None:
     generate(tmp_path)
 
-    interfaces = (tmp_path / "rtl/soc_apb_interfaces.svh").read_text(encoding="utf-8")
-    declarations = (tmp_path / "rtl/soc_apb_declarations.svh").read_text(encoding="utf-8")
-    response = (tmp_path / "rtl/soc_apb_response_mux.svh").read_text(encoding="utf-8")
+    interfaces = (tmp_path / "rtl/apb4_system_interfaces.svh").read_text(encoding="utf-8")
+    declarations = (tmp_path / "rtl/apb4_system_declarations.svh").read_text(encoding="utf-8")
+    response = (tmp_path / "rtl/apb4_system_response_mux.svh").read_text(encoding="utf-8")
     formal_design = (ROOT / "rtl/mini/formal/rib2apb_formal.sv").read_text(encoding="utf-8")
     formal_properties = (ROOT / "rtl/mini/formal/rib2apb_formal_props.sv").read_text(
         encoding="utf-8"
     )
 
-    assert "apb4_if u_user_ip_apb_if (clk_i, rst_n_i);" in interfaces
+    assert "apb4_if u_user_ip_apb4_if (clk_i, rst_n_i);" in interfaces
     assert "localparam int NSLV = 8;" in declarations
     assert "s_psel_q[7]" in response
     assert "apb4_pure_if user_ip ();" in formal_design
@@ -192,27 +192,27 @@ def test_topology_always_adds_the_user_apb_target(tmp_path: Path) -> None:
 
 def test_topology_rejects_unknown_or_non_rib_regions(tmp_path: Path) -> None:
     document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
-    document["apb4_targets"][0]["regions"] = ["UNKNOWN"]
+    document["apb4_periph_targets"][0]["regions"] = ["UNKNOWN"]
     result = validate(write_invalid_topology(tmp_path, document))
     assert result.returncode != 0
     assert "unknown region" in result.stderr
 
     document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
-    document["apb4_targets"][0]["regions"] = ["SRAM"]
+    document["apb4_periph_targets"][0]["regions"] = ["SRAM"]
     result = validate(write_invalid_topology(tmp_path, document))
     assert result.returncode != 0
-    assert "not an active APB4 region" in result.stderr
+    assert "not an active apb4_periph region" in result.stderr
 
 
 def test_topology_rejects_duplicate_region_and_disabled_owner(tmp_path: Path) -> None:
     document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
-    document["apb4_targets"][1]["regions"] = ["APB4_UART0"]
+    document["apb4_periph_targets"][1]["regions"] = ["APB4_UART0"]
     result = validate(write_invalid_topology(tmp_path, document))
     assert result.returncode != 0
     assert "multiple targets" in result.stderr
 
     document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
-    document["apb4_targets"][15]["regions"] = ["APB4_SDIO"]
+    document["apb4_periph_targets"][15]["regions"] = ["APB4_SDIO"]
     result = validate(write_invalid_topology(tmp_path, document))
     assert result.returncode != 0
     assert "disabled but declares regions" in result.stderr
@@ -226,16 +226,16 @@ def test_topology_rejects_duplicate_region_and_disabled_owner(tmp_path: Path) ->
 
 def test_topology_rejects_invalid_apb_target_ownership(tmp_path: Path) -> None:
     document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
-    document["apb_targets"][0]["region"] = "SRAM"
+    document["apb4_system_targets"][0]["region"] = "SRAM"
     result = validate(write_invalid_topology(tmp_path, document))
     assert result.returncode != 0
-    assert "not an active APB region" in result.stderr
+    assert "not an active apb4_system region" in result.stderr
 
     document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
-    document["apb_targets"][7]["slot"] = 0
+    document["apb4_system_targets"][7]["slot"] = 0
     result = validate(write_invalid_topology(tmp_path, document))
     assert result.returncode != 0
-    assert "APB target slot 0 is duplicated" in result.stderr
+    assert "apb4_system_targets target slot 0 is duplicated" in result.stderr
 
 
 def test_topology_rejects_invalid_gpio_coverage_and_expression(tmp_path: Path) -> None:
@@ -260,16 +260,16 @@ def test_topology_rejects_invalid_gpio_coverage_and_expression(tmp_path: Path) -
 
 def test_topology_rejects_invalid_irq_groups_and_bindings(tmp_path: Path) -> None:
     document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
-    document["irq_groups"][1]["name"] = "apb4"
+    document["irq_groups"][1]["name"] = "apb4_periph"
     result = validate(write_invalid_topology(tmp_path, document))
     assert result.returncode != 0
-    assert "interrupt group apb4 is duplicated" in result.stderr
+    assert "interrupt group apb4_periph is duplicated" in result.stderr
 
     document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
     document["interrupts"][1]["group_bit"] = 0
     result = validate(write_invalid_topology(tmp_path, document))
     assert result.returncode != 0
-    assert "interrupt group apb4 bit 0 is duplicated" in result.stderr
+    assert "interrupt group apb4_periph bit 0 is duplicated" in result.stderr
 
     document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
     document["interrupts"][1]["core_bit"] = 0
@@ -286,7 +286,7 @@ def test_topology_rejects_invalid_irq_groups_and_bindings(tmp_path: Path) -> Non
     document["interrupts"].pop(rng_index)
     result = validate(write_invalid_topology(tmp_path, document))
     assert result.returncode != 0
-    assert "interrupt group apb does not cover every group bit" in result.stderr
+    assert "interrupt group apb4_system does not cover every group bit" in result.stderr
 
     document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
     document["interrupts"][0]["signal"] = "left | right"

tests/test_user_extensions.py

@@ -66,7 +66,7 @@ def test_extensions_generate_isolated_scalar_bindings(tmp_path: Path) -> None:
     assert ip.count("user_gpio_if #(`USER_GPIO_NUM)") == 2
     assert "gpio.do_o = '0;" in ip
     assert "8'd2: begin" in ip
-    assert "u_user_2_apb_if.psel = apb.psel;" in ip
+    assert "u_user_2_apb4_if.psel = apb.psel;" in ip
     assert filelist.startswith("+incdir+")
     assert "`define USER_CORE_COUNT 6" in config