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https://github.com/retroSoC/retroSoC.git
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feat: enhance test coverage and update system control interfaces
- Added interface to and implemented error handling for register writes. - Introduced a new test for AXI4 address gate functionality in . - Updated clock and reset domain assertions in to reflect new domain names. - Modified expected outputs in to include new clock domains. - Adjusted chip configuration assertions in to account for additional power pads. - Enhanced memory map tests in with new definitions and includes. - Updated pin mapping tests in to include new reference clock pads. - Improved script tools tests in to ensure correct validation of extension bindings. - Refined system control tests in to include new clock control interface. - Updated USB2 packet RAM tests in to include new SRAM definitions. - Enhanced user extensions tests in to validate new product extension configurations. - Adjusted user IP register parity tests to use legacy extensions. - Updated Yosys synthesis recipe tests to reflect changes in STA period calculations.
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+15
-8
@@ -2,9 +2,9 @@
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This directory contains committed Make configuration profiles. Each profile
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selects SoC, PDK, ISA, CSR support, application, linker layout, and the
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supported validation tier. The management core is fixed to Hazard3 with its
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JTAG Debug Module enabled. The user-extension fabric exposes C0-C3 slots for
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KianV RV32I, SERV, FemtoRV32, and DarkRISCV.
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supported validation tier. `MINI_MODE=PRODUCT` fixes Hazard3 and VexiiRiscv as
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LP/HP harts and exposes one fixed EXT-L plus one fixed EXT-H slot. The separate
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`cluster/mini-mpw.mk` profile retains C0-C3 and the selectable user-IP mux.
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`ci/` contains pull-request profiles, `cluster/` contains configurations
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requiring site tools or PDKs, and `benchmark/` contains fixed-workload baseline
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@@ -12,8 +12,9 @@ profiles. The `ihp130-hazard3-coremark.mk` profile is the automated SRAM
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CoreMark quick measurement; its `-standard` counterpart is reserved for a
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10-second hardware run. The nightly workflow reuses the IHP130 CI profile and
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runs the quick CoreMark profile.
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`ci/ihp130-hp.mk` is the experimental asymmetric Linux profile. It fixes both
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LP and HP at 72 MHz, runs `hp_boot` entirely from 32 KiB on-chip SRAM, and
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`ci/ihp130-hp.mk` is the asymmetric Linux application profile. It starts HP
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from the external 72 MHz safe clock and LP from REF24, runs `hp_boot` entirely
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from 32 KiB on-chip SRAM, and
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generates VexiiRiscv RTL only below the selected build variant. It is not part
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of the supported PR matrix until Linux boot, HP performance, synthesis, and
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timing evidence are qualified.
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@@ -25,9 +26,15 @@ variables on the command line.
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`SRAM_SIZE_KIB` selects 4, 16, 32, 64, or 128 KiB of on-chip SRAM and is part
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of the build variant key. IHP130, GF180, and SKY130 CI profiles select eight
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4 KiB banks for 32 KiB total and enable both the interface and technology
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macro. ICS55 profiles keep the memory absent. IHP130 benchmark and CoreMark
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profiles explicitly retain 128 KiB for their fixed workload placement and
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SRAM-resident image.
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macro. Committed ICS55 profiles keep the memory and PLL absent. All committed
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product and benchmark profiles use 32 KiB; larger capacities remain valid
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manual values but are not selected by the product profiles.
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`local/ics55.example.mk` is the only tracked local-profile artifact. Copy it to
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the ignored `local/ics55.mk`, set `HAVE_PLL`, `HAVE_SRAM_IF`, and
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`HAVE_SRAM_MACRO` to `YES`, and list the commercial SRAM model plus a local
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`PLL_TOP` simulation adapter in `LOCAL_RTL_FILES`. Both the copied profile and
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local `.sv` model are ignored so absolute commercial paths never enter Git.
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`HAVE_SRAM_MACRO=YES` requires `HAVE_SRAM_IF=YES`. The generic manual defaults
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enable 32 KiB for IHP130, GF180, and SKY130 and keep ICS55 disabled; committed
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@@ -1,9 +1,12 @@
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SOC := MINI
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MINI_MODE := PRODUCT
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PDK := IHP130
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HAVE_PLL := NO
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HAVE_SRAM_IF := YES
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HAVE_SRAM_MACRO := YES
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SRAM_SIZE_KIB := 128
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SRAM_SIZE_KIB := 32
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HAVE_HP := YES
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HP_CONFIG := rv32imafdc_max
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PDK_BEHAV := YES
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HAVE_SVA := NO
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EXT_CLK_HZ := 72000000
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@@ -1,9 +1,12 @@
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SOC := MINI
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MINI_MODE := PRODUCT
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PDK := IHP130
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HAVE_PLL := NO
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HAVE_SRAM_IF := YES
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HAVE_SRAM_MACRO := YES
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SRAM_SIZE_KIB := 128
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SRAM_SIZE_KIB := 32
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HAVE_HP := YES
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HP_CONFIG := rv32imafdc_max
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PDK_BEHAV := YES
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HAVE_SVA := NO
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EXT_CLK_HZ := 72000000
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@@ -1,9 +1,12 @@
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SOC := MINI
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MINI_MODE := PRODUCT
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PDK := IHP130
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HAVE_PLL := NO
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HAVE_SRAM_IF := YES
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HAVE_SRAM_MACRO := YES
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SRAM_SIZE_KIB := 128
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SRAM_SIZE_KIB := 32
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HAVE_HP := YES
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HP_CONFIG := rv32imafdc_max
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PDK_BEHAV := YES
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HAVE_SVA := NO
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EXT_CLK_HZ := 72000000
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@@ -1,9 +1,12 @@
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SOC := MINI
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MINI_MODE := PRODUCT
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PDK := GF180
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HAVE_PLL := NO
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HAVE_SRAM_IF := YES
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HAVE_SRAM_MACRO := YES
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SRAM_SIZE_KIB := 32
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HAVE_HP := YES
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HP_CONFIG := rv32imafdc_max
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HAVE_SVA := NO
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EXT_CLK_HZ := 72000000
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AUD_CLK_HZ := 18432000
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+4
-1
@@ -1,9 +1,12 @@
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SOC := MINI
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MINI_MODE := PRODUCT
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PDK := ICS55
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HAVE_PLL := NO
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HAVE_SRAM_IF := NO
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HAVE_SRAM_MACRO := NO
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SRAM_SIZE_KIB := 128
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SRAM_SIZE_KIB := 32
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HAVE_HP := YES
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HP_CONFIG := rv32imafdc_max
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HAVE_SVA := NO
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EXT_CLK_HZ := 72000000
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AUD_CLK_HZ := 18432000
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@@ -1,9 +1,12 @@
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SOC := MINI
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MINI_MODE := PRODUCT
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PDK := IHP130
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HAVE_PLL := NO
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HAVE_SRAM_IF := YES
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HAVE_SRAM_MACRO := YES
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SRAM_SIZE_KIB := 32
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HAVE_HP := YES
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HP_CONFIG := rv32imafdc_max
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PDK_BEHAV := YES
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HAVE_SVA := NO
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EXT_CLK_HZ := 72000000
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@@ -1,4 +1,5 @@
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SOC := MINI
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MINI_MODE := PRODUCT
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PDK := IHP130
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HAVE_PLL := NO
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HAVE_HP := YES
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@@ -1,9 +1,12 @@
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SOC := MINI
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MINI_MODE := PRODUCT
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PDK := IHP130
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HAVE_PLL := NO
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HAVE_SRAM_IF := YES
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HAVE_SRAM_MACRO := YES
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SRAM_SIZE_KIB := 32
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HAVE_HP := YES
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HP_CONFIG := rv32imafdc_max
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HAVE_SVA := NO
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EXT_CLK_HZ := 72000000
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AUD_CLK_HZ := 18432000
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@@ -1,9 +1,12 @@
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SOC := MINI
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MINI_MODE := PRODUCT
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PDK := IHP130
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HAVE_PLL := NO
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HAVE_SRAM_IF := YES
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HAVE_SRAM_MACRO := YES
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SRAM_SIZE_KIB := 32
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HAVE_HP := YES
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HP_CONFIG := rv32imafdc_max
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PDK_BEHAV := YES
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HAVE_SVA := NO
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EXT_CLK_HZ := 72000000
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@@ -1,9 +1,12 @@
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SOC := MINI
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MINI_MODE := PRODUCT
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PDK := IHP130
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HAVE_PLL := NO
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HAVE_SRAM_IF := YES
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HAVE_SRAM_MACRO := YES
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SRAM_SIZE_KIB := 32
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HAVE_HP := YES
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HP_CONFIG := rv32imafdc_max
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HAVE_SVA := NO
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EXT_CLK_HZ := 72000000
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AUD_CLK_HZ := 18432000
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@@ -1,9 +1,12 @@
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SOC := MINI
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MINI_MODE := PRODUCT
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PDK := SKY130
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HAVE_PLL := NO
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HAVE_SRAM_IF := YES
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HAVE_SRAM_MACRO := YES
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SRAM_SIZE_KIB := 32
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HAVE_HP := YES
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HP_CONFIG := rv32imafdc_max
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HAVE_SVA := NO
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EXT_CLK_HZ := 72000000
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AUD_CLK_HZ := 18432000
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@@ -1,9 +1,12 @@
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SOC := MINI
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MINI_MODE := PRODUCT
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PDK := ICS55
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HAVE_PLL := NO
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HAVE_SRAM_IF := NO
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HAVE_SRAM_MACRO := NO
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SRAM_SIZE_KIB := 128
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SRAM_SIZE_KIB := 32
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HAVE_HP := YES
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HP_CONFIG := rv32imafdc_max
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HAVE_SVA := NO
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EXT_CLK_HZ := 72000000
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AUD_CLK_HZ := 18432000
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@@ -0,0 +1,17 @@
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SOC := MINI
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MINI_MODE := MPW
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PDK := IHP130
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HAVE_PLL := NO
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HAVE_SRAM_IF := YES
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HAVE_SRAM_MACRO := YES
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SRAM_SIZE_KIB := 32
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PDK_BEHAV := YES
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HAVE_SVA := NO
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HAVE_HP := NO
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EXT_CLK_HZ := 72000000
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AUD_CLK_HZ := 18432000
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CLINT_TIMEBASE_HZ := 1000000
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ISA := RV32IM
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HAVE_CSR := NO
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APP := bringup
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LINK_TYPE := ld2_psram
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@@ -0,0 +1,15 @@
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# Copy this file to configs/local/ics55.mk. The local copy and every absolute
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# macro-model path remain ignored by Git.
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include configs/cluster/ics55.mk
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HAVE_PLL := YES
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HAVE_SRAM_IF := YES
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HAVE_SRAM_MACRO := YES
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SRAM_SIZE_KIB := 32
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AUD_CLK_HZ := 18432000
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# Populate both paths from the local ICS_LIB declared by
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# physical/commercial/local/ics55-production.mk. Keep the copied profile and
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# any local PLL_TOP simulation adapter ignored by Git.
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LOCAL_RTL_FILES := REQUIRED_SRAM_MODEL REQUIRED_PLL_MODEL
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