feat: enhance test coverage and update system control interfaces

- Added  interface to  and implemented error handling for register writes.
- Introduced a new test for AXI4 address gate functionality in .
- Updated clock and reset domain assertions in  to reflect new domain names.
- Modified expected outputs in  to include new clock domains.
- Adjusted chip configuration assertions in  to account for additional power pads.
- Enhanced memory map tests in  with new definitions and includes.
- Updated pin mapping tests in  to include new reference clock pads.
- Improved script tools tests in  to ensure correct validation of extension bindings.
- Refined system control tests in  to include new clock control interface.
- Updated USB2 packet RAM tests in  to include new SRAM definitions.
- Enhanced user extensions tests in  to validate new product extension configurations.
- Adjusted user IP register parity tests to use legacy extensions.
- Updated Yosys synthesis recipe tests to reflect changes in STA period calculations.
This commit is contained in:
maksyuki committed 2026-08-30 08:10:59 +08:00
1 parent 795b3a4b1d
commit 2b6819449c
131 files changed
+5983 -1790

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+15 -8
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@@ -2,9 +2,9 @@
This directory contains committed Make configuration profiles. Each profile
selects SoC, PDK, ISA, CSR support, application, linker layout, and the
supported validation tier. The management core is fixed to Hazard3 with its
JTAG Debug Module enabled. The user-extension fabric exposes C0-C3 slots for
KianV RV32I, SERV, FemtoRV32, and DarkRISCV.
supported validation tier. `MINI_MODE=PRODUCT` fixes Hazard3 and VexiiRiscv as
LP/HP harts and exposes one fixed EXT-L plus one fixed EXT-H slot. The separate
`cluster/mini-mpw.mk` profile retains C0-C3 and the selectable user-IP mux.
`ci/` contains pull-request profiles, `cluster/` contains configurations
requiring site tools or PDKs, and `benchmark/` contains fixed-workload baseline
@@ -12,8 +12,9 @@ profiles. The `ihp130-hazard3-coremark.mk` profile is the automated SRAM
CoreMark quick measurement; its `-standard` counterpart is reserved for a
10-second hardware run. The nightly workflow reuses the IHP130 CI profile and
runs the quick CoreMark profile.
`ci/ihp130-hp.mk` is the experimental asymmetric Linux profile. It fixes both
LP and HP at 72 MHz, runs `hp_boot` entirely from 32 KiB on-chip SRAM, and
`ci/ihp130-hp.mk` is the asymmetric Linux application profile. It starts HP
from the external 72 MHz safe clock and LP from REF24, runs `hp_boot` entirely
from 32 KiB on-chip SRAM, and
generates VexiiRiscv RTL only below the selected build variant. It is not part
of the supported PR matrix until Linux boot, HP performance, synthesis, and
timing evidence are qualified.
@@ -25,9 +26,15 @@ variables on the command line.
`SRAM_SIZE_KIB` selects 4, 16, 32, 64, or 128 KiB of on-chip SRAM and is part
of the build variant key. IHP130, GF180, and SKY130 CI profiles select eight
4 KiB banks for 32 KiB total and enable both the interface and technology
macro. ICS55 profiles keep the memory absent. IHP130 benchmark and CoreMark
profiles explicitly retain 128 KiB for their fixed workload placement and
SRAM-resident image.
macro. Committed ICS55 profiles keep the memory and PLL absent. All committed
product and benchmark profiles use 32 KiB; larger capacities remain valid
manual values but are not selected by the product profiles.
`local/ics55.example.mk` is the only tracked local-profile artifact. Copy it to
the ignored `local/ics55.mk`, set `HAVE_PLL`, `HAVE_SRAM_IF`, and
`HAVE_SRAM_MACRO` to `YES`, and list the commercial SRAM model plus a local
`PLL_TOP` simulation adapter in `LOCAL_RTL_FILES`. Both the copied profile and
local `.sv` model are ignored so absolute commercial paths never enter Git.
`HAVE_SRAM_MACRO=YES` requires `HAVE_SRAM_IF=YES`. The generic manual defaults
enable 32 KiB for IHP130, GF180, and SKY130 and keep ICS55 disabled; committed
@@ -1,9 +1,12 @@
SOC := MINI
MINI_MODE := PRODUCT
PDK := IHP130
HAVE_PLL := NO
HAVE_SRAM_IF := YES
HAVE_SRAM_MACRO := YES
SRAM_SIZE_KIB := 128
SRAM_SIZE_KIB := 32
HAVE_HP := YES
HP_CONFIG := rv32imafdc_max
PDK_BEHAV := YES
HAVE_SVA := NO
EXT_CLK_HZ := 72000000
+4 -1
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@@ -1,9 +1,12 @@
SOC := MINI
MINI_MODE := PRODUCT
PDK := IHP130
HAVE_PLL := NO
HAVE_SRAM_IF := YES
HAVE_SRAM_MACRO := YES
SRAM_SIZE_KIB := 128
SRAM_SIZE_KIB := 32
HAVE_HP := YES
HP_CONFIG := rv32imafdc_max
PDK_BEHAV := YES
HAVE_SVA := NO
EXT_CLK_HZ := 72000000
+4 -1
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@@ -1,9 +1,12 @@
SOC := MINI
MINI_MODE := PRODUCT
PDK := IHP130
HAVE_PLL := NO
HAVE_SRAM_IF := YES
HAVE_SRAM_MACRO := YES
SRAM_SIZE_KIB := 128
SRAM_SIZE_KIB := 32
HAVE_HP := YES
HP_CONFIG := rv32imafdc_max
PDK_BEHAV := YES
HAVE_SVA := NO
EXT_CLK_HZ := 72000000
+3
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@@ -1,9 +1,12 @@
SOC := MINI
MINI_MODE := PRODUCT
PDK := GF180
HAVE_PLL := NO
HAVE_SRAM_IF := YES
HAVE_SRAM_MACRO := YES
SRAM_SIZE_KIB := 32
HAVE_HP := YES
HP_CONFIG := rv32imafdc_max
HAVE_SVA := NO
EXT_CLK_HZ := 72000000
AUD_CLK_HZ := 18432000
+4 -1
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@@ -1,9 +1,12 @@
SOC := MINI
MINI_MODE := PRODUCT
PDK := ICS55
HAVE_PLL := NO
HAVE_SRAM_IF := NO
HAVE_SRAM_MACRO := NO
SRAM_SIZE_KIB := 128
SRAM_SIZE_KIB := 32
HAVE_HP := YES
HP_CONFIG := rv32imafdc_max
HAVE_SVA := NO
EXT_CLK_HZ := 72000000
AUD_CLK_HZ := 18432000
+3
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@@ -1,9 +1,12 @@
SOC := MINI
MINI_MODE := PRODUCT
PDK := IHP130
HAVE_PLL := NO
HAVE_SRAM_IF := YES
HAVE_SRAM_MACRO := YES
SRAM_SIZE_KIB := 32
HAVE_HP := YES
HP_CONFIG := rv32imafdc_max
PDK_BEHAV := YES
HAVE_SVA := NO
EXT_CLK_HZ := 72000000
+1
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@@ -1,4 +1,5 @@
SOC := MINI
MINI_MODE := PRODUCT
PDK := IHP130
HAVE_PLL := NO
HAVE_HP := YES
+3
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@@ -1,9 +1,12 @@
SOC := MINI
MINI_MODE := PRODUCT
PDK := IHP130
HAVE_PLL := NO
HAVE_SRAM_IF := YES
HAVE_SRAM_MACRO := YES
SRAM_SIZE_KIB := 32
HAVE_HP := YES
HP_CONFIG := rv32imafdc_max
HAVE_SVA := NO
EXT_CLK_HZ := 72000000
AUD_CLK_HZ := 18432000
+3
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@@ -1,9 +1,12 @@
SOC := MINI
MINI_MODE := PRODUCT
PDK := IHP130
HAVE_PLL := NO
HAVE_SRAM_IF := YES
HAVE_SRAM_MACRO := YES
SRAM_SIZE_KIB := 32
HAVE_HP := YES
HP_CONFIG := rv32imafdc_max
PDK_BEHAV := YES
HAVE_SVA := NO
EXT_CLK_HZ := 72000000
+3
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@@ -1,9 +1,12 @@
SOC := MINI
MINI_MODE := PRODUCT
PDK := IHP130
HAVE_PLL := NO
HAVE_SRAM_IF := YES
HAVE_SRAM_MACRO := YES
SRAM_SIZE_KIB := 32
HAVE_HP := YES
HP_CONFIG := rv32imafdc_max
HAVE_SVA := NO
EXT_CLK_HZ := 72000000
AUD_CLK_HZ := 18432000
+3
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@@ -1,9 +1,12 @@
SOC := MINI
MINI_MODE := PRODUCT
PDK := SKY130
HAVE_PLL := NO
HAVE_SRAM_IF := YES
HAVE_SRAM_MACRO := YES
SRAM_SIZE_KIB := 32
HAVE_HP := YES
HP_CONFIG := rv32imafdc_max
HAVE_SVA := NO
EXT_CLK_HZ := 72000000
AUD_CLK_HZ := 18432000
+4 -1
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@@ -1,9 +1,12 @@
SOC := MINI
MINI_MODE := PRODUCT
PDK := ICS55
HAVE_PLL := NO
HAVE_SRAM_IF := NO
HAVE_SRAM_MACRO := NO
SRAM_SIZE_KIB := 128
SRAM_SIZE_KIB := 32
HAVE_HP := YES
HP_CONFIG := rv32imafdc_max
HAVE_SVA := NO
EXT_CLK_HZ := 72000000
AUD_CLK_HZ := 18432000
+17
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@@ -0,0 +1,17 @@
SOC := MINI
MINI_MODE := MPW
PDK := IHP130
HAVE_PLL := NO
HAVE_SRAM_IF := YES
HAVE_SRAM_MACRO := YES
SRAM_SIZE_KIB := 32
PDK_BEHAV := YES
HAVE_SVA := NO
HAVE_HP := NO
EXT_CLK_HZ := 72000000
AUD_CLK_HZ := 18432000
CLINT_TIMEBASE_HZ := 1000000
ISA := RV32IM
HAVE_CSR := NO
APP := bringup
LINK_TYPE := ld2_psram
+15
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@@ -0,0 +1,15 @@
# Copy this file to configs/local/ics55.mk. The local copy and every absolute
# macro-model path remain ignored by Git.
include configs/cluster/ics55.mk
HAVE_PLL := YES
HAVE_SRAM_IF := YES
HAVE_SRAM_MACRO := YES
SRAM_SIZE_KIB := 32
AUD_CLK_HZ := 18432000
# Populate both paths from the local ICS_LIB declared by
# physical/commercial/local/ics55-production.mk. Keep the copied profile and
# any local PLL_TOP simulation adapter ignored by Git.
LOCAL_RTL_FILES := REQUIRED_SRAM_MODEL REQUIRED_PLL_MODEL