feat: enhance test coverage and update system control interfaces

- Added  interface to  and implemented error handling for register writes.
- Introduced a new test for AXI4 address gate functionality in .
- Updated clock and reset domain assertions in  to reflect new domain names.
- Modified expected outputs in  to include new clock domains.
- Adjusted chip configuration assertions in  to account for additional power pads.
- Enhanced memory map tests in  with new definitions and includes.
- Updated pin mapping tests in  to include new reference clock pads.
- Improved script tools tests in  to ensure correct validation of extension bindings.
- Refined system control tests in  to include new clock control interface.
- Updated USB2 packet RAM tests in  to include new SRAM definitions.
- Enhanced user extensions tests in  to validate new product extension configurations.
- Adjusted user IP register parity tests to use legacy extensions.
- Updated Yosys synthesis recipe tests to reflect changes in STA period calculations.
This commit is contained in:
maksyuki committed 2026-08-30 08:10:59 +08:00
1 parent 795b3a4b1d
commit 2b6819449c
131 files changed
+5983 -1790

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@@ -45,8 +45,9 @@ def test_sysctrl_registers_lifecycle_faults_and_wake(tmp_path: Path) -> None:
source_list = tmp_path / "sysctrl.fl"
source_list.write_text(
"\n".join(
[
"+define+SV_ASSRT_DISABLE",
[
"+define+SV_ASSRT_DISABLE",
"+define+MINI_PRODUCT",
f"+incdir+{generated / 'rtl'}",
f"+incdir+{generated / 'user_extensions' / 'rtl'}",
f"+incdir+{ROOT / 'rtl/mini/top'}",
@@ -58,7 +59,8 @@ def test_sysctrl_registers_lifecycle_faults_and_wake(tmp_path: Path) -> None:
str(common / "interface/apb4_if.sv"),
str(common / "utils/register.sv"),
str(common / "cdc/cdc_sync.sv"),
str(PERIPHERAL / "pll_ctrl_if.sv"),
str(PERIPHERAL / "pll_ctrl_if.sv"),
str(PERIPHERAL / "clock_ctrl_if.sv"),
str(PERIPHERAL / "sysctrl_if.sv"),
str(PERIPHERAL / "sysctrl_define.svh"),
str(PERIPHERAL / "sysctrl_reg.sv"),