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feat: enhance test coverage and update system control interfaces
- Added interface to and implemented error handling for register writes. - Introduced a new test for AXI4 address gate functionality in . - Updated clock and reset domain assertions in to reflect new domain names. - Modified expected outputs in to include new clock domains. - Adjusted chip configuration assertions in to account for additional power pads. - Enhanced memory map tests in with new definitions and includes. - Updated pin mapping tests in to include new reference clock pads. - Improved script tools tests in to ensure correct validation of extension bindings. - Refined system control tests in to include new clock control interface. - Updated USB2 packet RAM tests in to include new SRAM definitions. - Enhanced user extensions tests in to validate new product extension configurations. - Adjusted user IP register parity tests to use legacy extensions. - Updated Yosys synthesis recipe tests to reflect changes in STA period calculations.
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@@ -45,8 +45,9 @@ def test_sysctrl_registers_lifecycle_faults_and_wake(tmp_path: Path) -> None:
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source_list = tmp_path / "sysctrl.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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[
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"+define+SV_ASSRT_DISABLE",
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"+define+MINI_PRODUCT",
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f"+incdir+{generated / 'rtl'}",
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f"+incdir+{generated / 'user_extensions' / 'rtl'}",
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f"+incdir+{ROOT / 'rtl/mini/top'}",
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@@ -58,7 +59,8 @@ def test_sysctrl_registers_lifecycle_faults_and_wake(tmp_path: Path) -> None:
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str(common / "interface/apb4_if.sv"),
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str(common / "utils/register.sv"),
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str(common / "cdc/cdc_sync.sv"),
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str(PERIPHERAL / "pll_ctrl_if.sv"),
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str(PERIPHERAL / "pll_ctrl_if.sv"),
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str(PERIPHERAL / "clock_ctrl_if.sv"),
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str(PERIPHERAL / "sysctrl_if.sv"),
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str(PERIPHERAL / "sysctrl_define.svh"),
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str(PERIPHERAL / "sysctrl_reg.sv"),
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