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fix: fix wrong byte order issue

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maksyuki committed 2025-02-17 12:00:33 +08:00
1 parent bcff2ac78b
commit 2d0256c2f0
2 files changed
+5 -5
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rtl/ip/cust/psram.v
+2 -2
View File
@@ -57,8 +57,8 @@ module psram_top (
r_mem_wdata <= s_disp_wdata;
end else if (mem_valid_i && (~(|mem_wstrb_i))) begin
r_fsm_state <= FSM_RD_ST;
r_xfer_data_bit_cnt <= s_disp_xfer_bit_cnt;
r_mem_addr <= mem_addr_i + s_disp_addr_ofst;
r_xfer_data_bit_cnt <= 8'd32;
r_mem_addr <= mem_addr_i;
r_mem_wdata <= mem_wdata_i; // TODO: no used
end
end
rtl/ip/cust/psram_core.v
+3 -3
View File
@@ -65,9 +65,9 @@ module psram_core (
assign idle_o = r_fsm_state == FSM_IDLE;
assign psram_sio_oen_o = (r_fsm_state == FSM_RD_PRE_QPI) | (r_fsm_state == FSM_RD_QPI);
assign mem_rdata_o = ({32{xfer_data_bit_cnt_i == 8'd32}} & (r_xfer_data & 32'hFFFF_FFFF)) |
({32{xfer_data_bit_cnt_i == 8'd16}} & (r_xfer_data & 32'h0000_FFFF)) |
({32{xfer_data_bit_cnt_i == 8'd8 }} & (r_xfer_data & 32'h0000_00FF));
assign mem_rdata_o = {
r_xfer_data[7:0], r_xfer_data[15:8], r_xfer_data[23:16], r_xfer_data[31:24]
};
always @(*) begin
if (r_fsm_state == FSM_INIT) begin