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chore: add rng to the make script

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maksyuki committed 2025-02-02 00:00:35 +08:00
1 parent 2fe3e97822
commit 3378f04e90
2 files changed
+8 -5
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.gitignore
+1
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@@ -9,3 +9,4 @@
retrosoc_sections.lds
retrosoc_syn*
IHP-Open-PDK
AXI4Lite_To_APB_Bridge
rtl/Makefile
+7 -5
View File
@@ -17,12 +17,14 @@ RTL_IP := ./ip/spram_model.v \
./ip/ravenna_spi.v \
./ip/spiflash.v \
./ip/cust/register.v \
./ip/cust/lfsr.v \
./ip/cust/archinfo.v \
./ip/cust/AXI4Lite_To_APB_Bridge/RTL/flop.v \
./ip/cust/AXI4Lite_To_APB_Bridge/RTL/address_decoder.v \
./ip/cust/AXI4Lite_To_APB_Bridge/RTL/read_data_mux.v \
./ip/cust/AXI4Lite_To_APB_Bridge/RTL/apb_master.v \
./ip/cust/AXI4Lite_To_APB_Bridge/RTL/axi_apb_bridge.v \
./ip/cust/rng.v \
./ip/cust/axil2apb/flop.v \
./ip/cust/axil2apb/address_decoder.v \
./ip/cust/axil2apb/read_data_mux.v \
./ip/cust/axil2apb/apb_master.v \
./ip/cust/axil2apb/axi_apb_bridge.v \
./ip/axil_ip_wrapper.v
RTL_TECH := ../tech/tc_io.v \