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chore: mv sim model to single new dir

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maksyuki committed 2026-03-26 21:59:31 +08:00
1 parent d10b1e1a29
commit 3afed0e614
4 files changed
+3 -3
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rtl/ip/native/DVP_CAMERA.sv → rtl/ip/tb/DVP_CAMERA.sv
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File renamed without changes.
rtl/ip/native/ESP_PSRAM64H.sv → rtl/ip/tb/ESP_PSRAM64H.sv
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File renamed without changes.
rtl/mini/filelist/tb.fl
+2 -2
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@@ -3,7 +3,7 @@
/clusterip/uart/model/rs232.sv
/clusterip/i2s/model/mic.sv
/clusterip/spi/model/w25q128jvxim.sv
/ip/native/ESP_PSRAM64H.sv
/ip/native/DVP_CAMERA.sv
/ip/tb/ESP_PSRAM64H.sv
/ip/tb/DVP_CAMERA.sv
/ip/3rd-party/model/sdram/sdr.v
/tb/retrosoc_tb.sv
rtl/mini/lint.msg
+1 -1
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@@ -1,5 +1,5 @@
{
+lint=all;
-file=/mpw/core/username3/Hazard3/arith/hazard3_muldiv_seq.v,/mpw/core/username3/Hazard3/hazard3_frontend.v,/mpw/core/username3/Hazard3/arith/hazard3_onehot_encode.v,/mpw/core/username3/Hazard3/hazard3_instr_decompress.v,/pdk/icsprout55-pdk/IP/IO/ICsprout_55LLULP1233_IO_251013/verilog/icsIOA_N55_3P3.v,/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/verilog/ics55_LLSC_H7CR.v,/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/verilog/ics55_LLSC_H7CL.v,/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CH/verilog/ics55_LLSC_H7CH.v,/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v,/clusterip/i2c/model/at24cxxx.sv,/clusterip/spi/model/w25q128jvxim.sv,/core/picorv32_ver.v,/core/picorv32.v,/clusterip/common/rtl/cdc/cdc_2phase.sv,/clusterip/common/rtl/utils/register.sv,/clusterip/uart/model/rs232.sv,/tb/retrosoc_tb.sv,/clusterip/i2s/model/mic.sv,/ip/native/ESP_PSRAM64H.sv,/ip/3rd-party/model/sdram/sdr.v;
-file=/mpw/core/username3/Hazard3/arith/hazard3_muldiv_seq.v,/mpw/core/username3/Hazard3/hazard3_frontend.v,/mpw/core/username3/Hazard3/arith/hazard3_onehot_encode.v,/mpw/core/username3/Hazard3/hazard3_instr_decompress.v,/pdk/icsprout55-pdk/IP/IO/ICsprout_55LLULP1233_IO_251013/verilog/icsIOA_N55_3P3.v,/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/verilog/ics55_LLSC_H7CR.v,/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/verilog/ics55_LLSC_H7CL.v,/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CH/verilog/ics55_LLSC_H7CH.v,/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v,/clusterip/i2c/model/at24cxxx.sv,/clusterip/spi/model/w25q128jvxim.sv,/core/picorv32_ver.v,/core/picorv32.v,/clusterip/common/rtl/cdc/cdc_2phase.sv,/clusterip/common/rtl/utils/register.sv,/clusterip/uart/model/rs232.sv,/tb/retrosoc_tb.sv,/clusterip/i2s/model/mic.sv,/ip/tb/ESP_PSRAM64H.sv,/ip/3rd-party/model/sdram/sdr.v;
}
{ +warn=all; }