docs: record the GF180 SRAM macro path and its evidence

Extend the chapter 3 memory-swap documentation to GF180: hp-platform.md
adds the tiling table (8-bit macro stacking with registered read muxes),
notes the repo-owned functional models versus the vendor collateral in the
locked PDK, and documents the SKY130 byte-mask blocker as the reason that
PDK stays behavioral; hp-rv64-validation.md records the directed-TB,
MEM_INTF, boot-testbench, and SoC macro-sim evidence; the two READMEs
generalize the override wording to IHP130/ICS55/GF180. Physical
qualification (Liberty registration, STA, LEC) stays explicitly deferred.

scripts/README.md

@@ -132,8 +132,10 @@ upstream `C906_RTL_FACTORY/gen_rtl` filelists from that checkout, substitutes
 the reviewed overrides from `rtl/mini/ip_overrides/` (the hart-1
 `aq_sysio_kid.v`, the strong-order MMIO-window `sysmap.h`, the eight
 `aq_spsram_*.v` SRAM wrappers whose PDK-selectable macro path — stacked
-IHP130 `RM_IHPSG13_1P_*` or exact-geometry ICS55 `ics55_ecos_sram_*` — is
-gated on `PDK_IHP130`/`PDK_ICS55`+`HAVE_SRAM_MACRO` without `PDK_BEHAV`, and
+IHP130 `RM_IHPSG13_1P_*`, exact-geometry ICS55 `ics55_ecos_sram_*`, or tiled
+GF180 `gf180mcu_fd_ip_sram__sram*x8m8wm1` — is
+gated on `PDK_IHP130`/`PDK_ICS55`/`PDK_GF180`+`HAVE_SRAM_MACRO` without
+`PDK_BEHAV`, and
 the `gated_clk_cell.v`/`tdt_gated_clk_cell.v`/`BUFGCE.v` clock-gate overrides
 that select the process ICG cell under a `PDK_*` define without `PDK_BEHAV`),
 each pinned to