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feat: add archinfo test code

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maksyuki committed 2025-02-01 21:35:29 +08:00
1 parent 982b613974
commit 5c5f639c3b
4 files changed
+28 -10
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rtl/Makefile
+10 -2
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@@ -15,7 +15,15 @@ RTL_IP := ./ip/spram_model.v \
./ip/counter_timer.v \
./ip/spi_slave.v \
./ip/ravenna_spi.v \
./ip/spiflash.v
./ip/spiflash.v \
./ip/cust/register.v \
./ip/cust/archinfo.v \
./ip/cust/AXI4Lite_To_APB_Bridge/RTL/flop.v \
./ip/cust/AXI4Lite_To_APB_Bridge/RTL/address_decoder.v \
./ip/cust/AXI4Lite_To_APB_Bridge/RTL/read_data_mux.v \
./ip/cust/AXI4Lite_To_APB_Bridge/RTL/apb_master.v \
./ip/cust/AXI4Lite_To_APB_Bridge/RTL/axi_apb_bridge.v \
./ip/axil_ip_wrapper.v
RTL_TECH := ../tech/tc_io.v \
../tech/tc_clk.v \
@@ -36,7 +44,7 @@ retrosynsim: retrosoc_syn_tb.vvp retrosoc_fw.hex
vvp -N $< +firmware=retrosoc_fw.hex +syn_$(WAVE) -fst
retrosoc_tb.vvp: retrosoc_tb.v retrosoc_asic.v retrosoc.v picorv32.v $(RTL_IP) $(RTL_TECH) $(RTL_PDK)
retrosoc_tb.vvp: retrosoc_tb.v retrosoc_asic.v retrosoc.v picorv32.v $(RTL_TECH) $(RTL_PDK) $(RTL_IP)
iverilog $(RTL_INC) -s retrosoc_tb -o $@ $^
retrosoc_syn_tb.vvp: retrosoc_tb.v ../syn/yosys/out/retrosoc_asic_yosys.v ./ip/spiflash.v $(RTL_PDK)
rtl/firmware.c
+12 -3
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@@ -664,6 +664,14 @@ void ip_i2c_test()
i2c_send(0x6, 0xfa);
}
void ip_archinfo_test() {
print("[IP] archinfo test\n");
print_reg("[ARCHINFO SYS]", reg_archinfo_sys, 8);
print_reg("[ARCHINFO IDL]", reg_archinfo_idl, 8);
print_reg("[ARCHINFO IDH]", reg_archinfo_idh, 8);
}
void main()
{
// reg_uart_clkdiv = 104; // for 100M
@@ -694,12 +702,13 @@ void main()
// cmd_print_spi_state();
// ip_counter_timer_test();
ip_gpio_test();
ip_i2c_test();
// ip_gpio_test();
// ip_i2c_test();
ip_archinfo_test();
// cmd_benchmark(true, 0);
// cmd_benchmark_all();
// cmd_memtest();
cmd_echo();
// cmd_echo();
while (1)
;
// while (1) {
rtl/firmware.h
+6 -3
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@@ -49,9 +49,12 @@
#define reg_timer1_value (*(volatile uint32_t*)0x0300006c)
#define reg_timer1_data (*(volatile uint32_t*)0x03000070)
// archinfo
// rng
//
#define reg_archinfo_sys (*(volatile uint32_t*)0x03000100)
#define reg_archinfo_idl (*(volatile uint32_t*)0x03000104)
#define reg_archinfo_idh (*(volatile uint32_t*)0x03000108)
// command register bits
// bit 7 = start
rtl/ip/apb_wrapper.v
-2
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@@ -1,2 +0,0 @@
module apb_wrapper ();
endmodule