refactor: refactor RTL paths and update test descriptions

- Updated RTL paths in various files to remove the 'ribp' prefix, reflecting the new directory structure.
- Modified test descriptions to remove version indicators (e.g., V2, V3) for clarity and consistency.
- Adjusted file references in scripts and tests to align with the new peripheral and multimedia directory structure.
- Added a new test to ensure repository layout invariants, confirming the absence of deprecated paths.

tests/rtl/dvp_tb.sv

@@ -128,7 +128,7 @@ module dvp_tb;
     write(32'h0000_0048, 32'h0000_0004);
     read(32'h0000_003c, value);
     if (ribp.resp_err) $fatal(1, "DVP interrupt read failed");
-    $display("RIBP DVP V2 capture test passed");
+    $display("RIBP DVP capture test passed");
     $finish;
   end
 endmodule

tests/rtl/gpio_tb.sv

@@ -168,7 +168,7 @@ module gpio_tb;
     write_register(ADMIN_BASE + `RIBP_GPIO_ADMIN_OE_CLEAR, 32'h1, 1'b1);
     if (gpio.oe_o[0] !== 1'b1) $fatal(1, "configuration lock did not protect OE");
 
-    $display("GPIO V2 directed test passed");
+    $display("GPIO directed test passed");
     $finish;
   end
 endmodule

tests/rtl/i2c_tb.sv

@@ -302,7 +302,7 @@ module i2c_tb;
     if (i2c.scl_o !== 1'b0 || i2c.sda_o !== 1'b0) begin
       $fatal(1, "I2C pads are not open-drain constants");
     end
-    $display("I2C V2 transfer, error, stretch, arbitration, and recovery test passed");
+    $display("I2C transfer, error, stretch, arbitration, and recovery test passed");
     $finish;
   end
 

tests/rtl/timer_tb.sv

@@ -169,7 +169,7 @@ module timer_tb;
     if ((intr_state[2:1] != 2'b11) || !irq_o) $fatal(1, "interrupt test failed");
     ribp_write(32'h0000_0020, 32'h0000_0007, 4'h1, 1'b0);
 
-    $display("RIBP Timer V2 register, mode, interrupt, and error test passed");
+    $display("RIBP Timer register, mode, interrupt, and error test passed");
     $finish;
   end
 endmodule

tests/rtl/uart_tb.sv

@@ -234,7 +234,7 @@ module uart_tb;
     write_ok(`RIBP_UART_DMA_CTRL, 3);
     if (!dma_tx_stall || !dma_rx_stall) $fatal(1, "Disabled UART asserted a DMA request");
 
-    $display("UART V3 register, FIFO, loopback, flow-control, interrupt, and DMA test passed");
+    $display("UART register, FIFO, loopback, flow-control, interrupt, and DMA test passed");
     $finish;
   end
 

tests/test_clint.py

@@ -9,7 +9,7 @@ from pathlib import Path
 
 
 ROOT = Path(__file__).resolve().parents[1]
-PERIPHERAL = ROOT / "rtl/ip/ribp/peripheral"
+PERIPHERAL = ROOT / "rtl/ip/peripheral"
 
 
 def test_clint_standard_map_multi_hart_and_timebase(tmp_path: Path) -> None:

tests/test_dma.py

@@ -44,8 +44,8 @@ def test_dma_reports_bus_errors_and_transfers_exact_word_count(tmp_path: Path) -
                 str(ROOT / "rtl/mini/top/rib_if.sv"),
                 str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
                 str(ROOT / "rtl/managed/clusterip/common/rtl/utils/fifo.sv"),
-                str(ROOT / "rtl/ip/ribp/peripheral/dma.sv"),
-                str(ROOT / "rtl/ip/ribp/peripheral/dma_core.sv"),
+                str(ROOT / "rtl/ip/peripheral/dma.sv"),
+                str(ROOT / "rtl/ip/peripheral/dma_core.sv"),
                 str(ROOT / "tests/rtl/dma_error_tb.sv"),
                 "",
             ]

tests/test_dvp.py

@@ -1,4 +1,4 @@
-"""RIBP DVP V2 register, CDC, framing, and packing regression."""
+"""RIBP DVP register, CDC, framing, and packing regression."""
 
 from __future__ import annotations
 
@@ -17,7 +17,7 @@ def test_dvp_capture_framing(tmp_path: Path) -> None:
     if iverilog is None or vvp is None:
         return
     common = ROOT / "rtl/managed/clusterip/common/rtl"
-    ip = ROOT / "rtl/ip/ribp/multimedia"
+    ip = ROOT / "rtl/ip/multimedia"
     defines = [
         "+define+PDK_BEHAV",
         "+define+SV_ASSRT_DISABLE",
@@ -60,4 +60,4 @@ def test_dvp_capture_framing(tmp_path: Path) -> None:
     simulation = tmp_path / "dvp_tb"
     subprocess.run([iverilog, "-g2012", "-s", "dvp_tb", "-o", str(simulation), str(converted)], check=True)
     result = subprocess.run([vvp, str(simulation)], check=True, capture_output=True, text=True)
-    assert "RIBP DVP V2 capture test passed" in result.stdout
+    assert "RIBP DVP capture test passed" in result.stdout

tests/test_gpio.py

@@ -1,4 +1,4 @@
-"""Directed RTL tests for the GPIO V2 register and pad-control contract."""
+"""Directed RTL tests for the GPIO register and pad-control contract."""
 
 from __future__ import annotations
 
@@ -11,14 +11,14 @@ from pathlib import Path
 ROOT = Path(__file__).resolve().parents[1]
 
 
-def test_gpio_v2_register_pad_interrupt_and_filter_contract(tmp_path: Path) -> None:
+def test_gpio_register_pad_interrupt_and_filter_contract(tmp_path: Path) -> None:
     iverilog = shutil.which("iverilog")
     sv2v = shutil.which("sv2v")
     vvp = shutil.which("vvp")
     if iverilog is None or sv2v is None or vvp is None:
         return
 
-    peripheral = ROOT / "rtl/ip/ribp/peripheral"
+    peripheral = ROOT / "rtl/ip/peripheral"
     common = ROOT / "rtl/managed/clusterip/common/rtl"
     source_list = tmp_path / "gpio.fl"
     source_list.write_text(
@@ -62,4 +62,4 @@ def test_gpio_v2_register_pad_interrupt_and_filter_contract(tmp_path: Path) -> N
     )
     result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
 
-    assert "GPIO V2 directed test passed" in result.stdout
+    assert "GPIO directed test passed" in result.stdout

tests/test_i2c.py

@@ -1,4 +1,4 @@
-"""Directed I2C V2 controller, FIFO, error, timeout, and recovery tests."""
+"""Directed I2C controller, FIFO, error, timeout, and recovery tests."""
 
 from __future__ import annotations
 
@@ -11,14 +11,14 @@ from pathlib import Path
 ROOT = Path(__file__).resolve().parents[1]
 
 
-def test_i2c_v2_controller_and_recovery_contract(tmp_path: Path) -> None:
+def test_i2c_controller_and_recovery_contract(tmp_path: Path) -> None:
     iverilog = shutil.which("iverilog")
     vvp = shutil.which("vvp")
     if iverilog is None or vvp is None:
         return
 
     common = ROOT / "rtl/managed/clusterip/common/rtl"
-    serial = ROOT / "rtl/ip/ribp/serial"
+    serial = ROOT / "rtl/ip/serial"
     cluster_i2c = ROOT / "rtl/managed/clusterip/i2c/rtl"
     source_list = tmp_path / "i2c.fl"
     source_list.write_text(
@@ -63,4 +63,4 @@ def test_i2c_v2_controller_and_recovery_contract(tmp_path: Path) -> None:
         check=True,
     )
     result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
-    assert "I2C V2 transfer, error, stretch, arbitration, and recovery test passed" in result.stdout
+    assert "I2C transfer, error, stretch, arbitration, and recovery test passed" in result.stdout

tests/test_memory_map.py

@@ -211,8 +211,8 @@ def test_sysctrl_fault_registers_record_and_clear_pending(tmp_path: Path) -> Non
                 str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
                 str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
                 str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv"),
-                str(ROOT / "rtl/ip/ribp/peripheral/pll_ctrl_if.sv"),
-                str(ROOT / "rtl/ip/ribp/peripheral/sysctrl.sv"),
+                str(ROOT / "rtl/ip/peripheral/pll_ctrl_if.sv"),
+                str(ROOT / "rtl/ip/peripheral/sysctrl.sv"),
                 str(ROOT / "tests/rtl/sysctrl_fault_tb.sv"),
                 "",
             ]
@@ -265,9 +265,9 @@ def test_pll_controller_reconfigures_and_falls_back_to_the_safe_clock(tmp_path:
                 str(ROOT / "rtl/managed/clusterip/common/rtl/clkrst/rst_sync.sv"),
                 str(ROOT / "rtl/managed/clusterip/common/rtl/clkrst/counter.sv"),
                 str(ROOT / "rtl/managed/clusterip/common/rtl/utils/edge_det.sv"),
-                str(ROOT / "rtl/ip/ribp/peripheral/pll_ctrl_if.sv"),
-                str(ROOT / "rtl/ip/ribp/peripheral/clint_timebase.sv"),
-                str(ROOT / "rtl/ip/ribp/peripheral/sysctrl.sv"),
+                str(ROOT / "rtl/ip/peripheral/pll_ctrl_if.sv"),
+                str(ROOT / "rtl/ip/peripheral/clint_timebase.sv"),
+                str(ROOT / "rtl/ip/peripheral/sysctrl.sv"),
                 str(ROOT / "rtl/tech/tc_clk.sv"),
                 str(ROOT / "rtl/tech/tc_pll.sv"),
                 str(ROOT / "rtl/mini/top/rcu.sv"),
@@ -338,7 +338,7 @@ def test_pll_controller_reconfigures_and_falls_back_to_the_safe_clock(tmp_path:
 
 
 def test_sysctrl_does_not_expose_unused_i2c_or_qspi_select_registers() -> None:
-    rtl = (ROOT / "rtl/ip/ribp/peripheral/sysctrl.sv").read_text(encoding="utf-8")
+    rtl = (ROOT / "rtl/ip/peripheral/sysctrl.sv").read_text(encoding="utf-8")
     header = (ROOT / "crt/include/retrosoc/core/soc.h").read_text(encoding="utf-8")
 
     for symbol in (

tests/test_repository_layout.py

@@ -0,0 +1,32 @@
+"""Repository layout invariants for self-owned IP and dependency inputs."""
+
+from pathlib import Path
+
+
+ROOT = Path(__file__).resolve().parents[1]
+
+
+def test_self_owned_ip_is_flattened_and_dependency_lock_is_distinct() -> None:
+    assert not (ROOT / "rtl/ip/ribp").exists()
+    assert (ROOT / "rtl/ip/peripheral").is_dir()
+    assert (ROOT / "rtl/ip/serial").is_dir()
+    assert not (ROOT / "config").exists()
+    assert (ROOT / "dependencies/dependencies.lock.json").is_file()
+    assert (ROOT / "configs/ci/ihp130.mk").is_file()
+
+
+def test_active_sources_do_not_reference_removed_paths() -> None:
+    roots = (ROOT / "rtl/mini", ROOT / "scripts", ROOT / "tests", ROOT / "docs")
+    removed_ip_path = "rtl/ip/" + "ribp"
+    removed_filelist_path = "/ip/" + "ribp"
+    removed_lock_path = "config/" + "dependencies.lock.json"
+    for search_root in roots:
+        for path in search_root.rglob("*"):
+            if path == Path(__file__):
+                continue
+            if not path.is_file() or path.suffix not in {".fl", ".mk", ".json", ".md", ".py"}:
+                continue
+            text = path.read_text(encoding="utf-8")
+            assert removed_ip_path not in text
+            assert removed_filelist_path not in text
+            assert removed_lock_path not in text

tests/test_script_tools.py

@@ -254,25 +254,25 @@ def test_formal_filelists_are_scoped_to_the_protocol_duts(tmp_path: Path) -> Non
     assert ROOT / "rtl/mini/top/rib2apb.sv" in rib2apb.files
     assert ROOT / "rtl/mini/formal/rib2apb_formal.sv" in rib2apb.files
     assert ROOT / "rtl/managed/clusterip/common/rtl/interface/apb4_pure_if.sv" in rib2apb.files
-    assert ROOT / "rtl/ip/ribp/peripheral/sysctrl.sv" in sysctrl.files
+    assert ROOT / "rtl/ip/peripheral/sysctrl.sv" in sysctrl.files
     assert ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv" in sysctrl.files
     assert ROOT / "rtl/mini/formal/sysctrl_formal.sv" in sysctrl.files
     assert ROOT / "rtl/mini/top/rcu.sv" in pll_rcu.files
     assert ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv" in pll_rcu.files
     assert ROOT / "rtl/managed/clusterip/common/rtl/clkrst/rst_sync.sv" in pll_rcu.files
-    assert ROOT / "rtl/ip/ribp/peripheral/gpio_core.sv" in gpio.files
-    assert ROOT / "rtl/ip/ribp/peripheral/gpio_reg.sv" in gpio.files
-    assert ROOT / "rtl/ip/ribp/peripheral/ribp_gpio.sv" in gpio.files
-    assert ROOT / "rtl/ip/ribp/peripheral/user_gpio_if.sv" in gpio.files
+    assert ROOT / "rtl/ip/peripheral/gpio_core.sv" in gpio.files
+    assert ROOT / "rtl/ip/peripheral/gpio_reg.sv" in gpio.files
+    assert ROOT / "rtl/ip/peripheral/ribp_gpio.sv" in gpio.files
+    assert ROOT / "rtl/ip/peripheral/user_gpio_if.sv" in gpio.files
     assert ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv" in gpio.files
     assert ROOT / "rtl/mini/formal/gpio_formal.sv" in gpio.files
-    assert ROOT / "rtl/ip/ribp/serial/ribp_ws2812.sv" in ws2812.files
+    assert ROOT / "rtl/ip/serial/ribp_ws2812.sv" in ws2812.files
     assert ROOT / "rtl/managed/clusterip/common/rtl/utils/fifo.sv" in ws2812.files
     assert ROOT / "rtl/mini/formal/ws2812_formal.sv" in ws2812.files
-    assert ROOT / "rtl/ip/ribp/serial/ribp_i2c.sv" in i2c.files
-    assert ROOT / "rtl/ip/ribp/serial/i2c_filter.sv" in i2c.files
+    assert ROOT / "rtl/ip/serial/ribp_i2c.sv" in i2c.files
+    assert ROOT / "rtl/ip/serial/i2c_filter.sv" in i2c.files
     assert ROOT / "rtl/mini/formal/i2c_formal.sv" in i2c.files
-    assert ROOT / "rtl/ip/ribp/peripheral/ribp_clint.sv" in clint.files
+    assert ROOT / "rtl/ip/peripheral/ribp_clint.sv" in clint.files
     assert ROOT / "rtl/mini/formal/clint_formal.sv" in clint.files
 
 
@@ -584,7 +584,7 @@ def test_format_file_scope_is_tracked_and_self_owned() -> None:
         Path("Makefile"),
         Path("configs/ci/example.mk"),
         Path("rtl/mini/top/retrosoc.sv"),
-        Path("rtl/ip/ribp/peripheral/sysctrl.sv"),
+        Path("rtl/ip/peripheral/sysctrl.sv"),
         Path("rtl/tech/tc_clk.sv"),
         Path("rtl/demo/reference.v"),
         Path("tests/rtl/bus_fault_tb.sv"),
@@ -599,7 +599,7 @@ def test_format_file_scope_is_tracked_and_self_owned() -> None:
     ]
     assert format_files(paths, "rtl") == [
         Path("rtl/demo/reference.v"),
-        Path("rtl/ip/ribp/peripheral/sysctrl.sv"),
+        Path("rtl/ip/peripheral/sysctrl.sv"),
         Path("rtl/mini/top/retrosoc.sv"),
         Path("rtl/tech/tc_clk.sv"),
         Path("tests/rtl/bus_fault_tb.sv"),
@@ -607,7 +607,7 @@ def test_format_file_scope_is_tracked_and_self_owned() -> None:
 
 
 def test_dependency_lock_and_config_key_include_a_fixed_timestamp(tmp_path: Path) -> None:
-    lock = load_lock(ROOT / "config/dependencies.lock.json")
+    lock = load_lock(ROOT / "dependencies/dependencies.lock.json")
     assert lock["schema_version"] == 1
     assert len(lock["sources"]["mpw"]["revision"]) == 40
     assert lock["sources"]["hazard3"]["destination"] == "rtl/managed/hazard3"
@@ -620,7 +620,7 @@ def test_dependency_lock_and_config_key_include_a_fixed_timestamp(tmp_path: Path
         sys.executable,
         str(ROOT / "scripts/config_key.py"),
         "--lock",
-        str(ROOT / "config/dependencies.lock.json"),
+        str(ROOT / "dependencies/dependencies.lock.json"),
         "--profile",
         "unit",
         "--timestamp",
@@ -664,7 +664,7 @@ def test_dependency_lock_and_config_key_include_a_fixed_timestamp(tmp_path: Path
 
 
 def test_development_environment_contract_is_lock_pinned(tmp_path: Path) -> None:
-    lock_path = ROOT / "config/dependencies.lock.json"
+    lock_path = ROOT / "dependencies/dependencies.lock.json"
     lock = load_lock(lock_path)
     cache = tmp_path / "development"
     stamp = stamp_data(ROOT, cache, DEFAULT_TOOLS, lock, lock_path)
@@ -678,7 +678,7 @@ def test_development_environment_contract_is_lock_pinned(tmp_path: Path) -> None
 
 
 def test_container_and_nix_environment_files_use_locked_inputs() -> None:
-    lock = load_lock(ROOT / "config/dependencies.lock.json")
+    lock = load_lock(ROOT / "dependencies/dependencies.lock.json")
     dockerfile = (ROOT / "docker/Dockerfile").read_text(encoding="utf-8")
     flake = (ROOT / "flake.nix").read_text(encoding="utf-8")
     sbom = make_sbom(lock)
@@ -743,7 +743,7 @@ def test_management_core_is_fixed_to_hazard3_with_debug() -> None:
 
 
 def test_hazard3_debug_flow_is_locked_and_uses_remote_bitbang() -> None:
-    lock = load_lock(ROOT / "config/dependencies.lock.json")
+    lock = load_lock(ROOT / "dependencies/dependencies.lock.json")
     makefile = (ROOT / "Makefile").read_text(encoding="utf-8")
     wrapper = (ROOT / "rtl/mini/top/mgmt_core_wrapper.sv").read_text(encoding="utf-8")
     debug_wrapper = (ROOT / "rtl/mini/top/mgmt_debug_wrapper.sv").read_text(encoding="utf-8")

tests/test_sdram.py

@@ -38,10 +38,10 @@ def test_sdram_controller_preserves_full_and_masked_writes(tmp_path: Path) -> No
                 f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
                 str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
                 str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
-                str(ROOT / "rtl/ip/ribp/memory/sdram.sv"),
-                str(ROOT / "rtl/ip/ribp/memory/sdram_clkgen.sv"),
-                str(ROOT / "rtl/ip/ribp/memory/sdram_reg.sv"),
-                str(ROOT / "rtl/ip/ribp/memory/sdram_core.sv"),
+                str(ROOT / "rtl/ip/memory/sdram.sv"),
+                str(ROOT / "rtl/ip/memory/sdram_clkgen.sv"),
+                str(ROOT / "rtl/ip/memory/sdram_reg.sv"),
+                str(ROOT / "rtl/ip/memory/sdram_core.sv"),
                 str(ROOT / "rtl/mini/dv/verilator/rtl/sdram_verilator_model.sv"),
                 str(ROOT / "tests/rtl/sdram_data_tb.sv"),
                 "",
@@ -99,10 +99,10 @@ def test_sdram_controller_preserves_data_with_micron_timing_model(tmp_path: Path
                 f"+incdir+{ROOT / 'rtl/managed/third_party/model/sdram'}",
                 str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
                 str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
-                str(ROOT / "rtl/ip/ribp/memory/sdram.sv"),
-                str(ROOT / "rtl/ip/ribp/memory/sdram_clkgen.sv"),
-                str(ROOT / "rtl/ip/ribp/memory/sdram_reg.sv"),
-                str(ROOT / "rtl/ip/ribp/memory/sdram_core.sv"),
+                str(ROOT / "rtl/ip/memory/sdram.sv"),
+                str(ROOT / "rtl/ip/memory/sdram_clkgen.sv"),
+                str(ROOT / "rtl/ip/memory/sdram_reg.sv"),
+                str(ROOT / "rtl/ip/memory/sdram_core.sv"),
                 str(ROOT / "tests/rtl/sdram_data_tb.sv"),
                 "",
             ]

tests/test_timer.py

@@ -1,4 +1,4 @@
-"""RIBP Timer V2 RTL regression tests."""
+"""RIBP Timer RTL regression tests."""
 
 from __future__ import annotations
 
@@ -9,7 +9,7 @@ from pathlib import Path
 
 
 ROOT = Path(__file__).resolve().parents[1]
-PERIPHERAL = ROOT / "rtl/ip/ribp/peripheral"
+PERIPHERAL = ROOT / "rtl/ip/peripheral"
 def test_timer_modes_interrupts_and_errors(tmp_path: Path) -> None:
     iverilog = shutil.which("iverilog")
     vvp = shutil.which("vvp")
@@ -57,4 +57,4 @@ def test_timer_modes_interrupts_and_errors(tmp_path: Path) -> None:
         check=True,
     )
     result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
-    assert "RIBP Timer V2 register, mode, interrupt, and error test passed" in result.stdout
+    assert "RIBP Timer register, mode, interrupt, and error test passed" in result.stdout

tests/test_uart.py

@@ -1,4 +1,4 @@
-"""UART V3 register, FIFO, framing, flow-control, interrupt, and DMA tests."""
+"""UART register, FIFO, framing, flow-control, interrupt, and DMA tests."""
 
 from __future__ import annotations
 
@@ -11,14 +11,14 @@ from pathlib import Path
 ROOT = Path(__file__).resolve().parents[1]
 
 
-def test_uart_v3_register_fifo_loopback_flow_control_and_errors(tmp_path: Path) -> None:
+def test_uart_register_fifo_loopback_flow_control_and_errors(tmp_path: Path) -> None:
     iverilog = shutil.which("iverilog")
     vvp = shutil.which("vvp")
     if iverilog is None or vvp is None:
         return
 
     common = ROOT / "rtl/managed/clusterip/common/rtl"
-    serial = ROOT / "rtl/ip/ribp/serial"
+    serial = ROOT / "rtl/ip/serial"
     source_list = tmp_path / "uart.fl"
     source_list.write_text(
         "\n".join(
@@ -66,4 +66,4 @@ def test_uart_v3_register_fifo_loopback_flow_control_and_errors(tmp_path: Path)
         check=True,
     )
     result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
-    assert "UART V3 register, FIFO, loopback, flow-control, interrupt, and DMA test passed" in result.stdout
+    assert "UART register, FIFO, loopback, flow-control, interrupt, and DMA test passed" in result.stdout

tests/test_ws2812.py

@@ -18,7 +18,7 @@ def test_ws2812_register_waveform_streaming_and_errors(tmp_path: Path) -> None:
         return
 
     common = ROOT / "rtl/managed/clusterip/common/rtl"
-    serial = ROOT / "rtl/ip/ribp/serial"
+    serial = ROOT / "rtl/ip/serial"
     source_list = tmp_path / "ws2812.fl"
     source_list.write_text(
         "\n".join(
@@ -83,7 +83,7 @@ def test_ws2812_accepts_dma_fixed_destination_backpressure(tmp_path: Path) -> No
         check=True,
     )
     common = ROOT / "rtl/managed/clusterip/common/rtl"
-    serial = ROOT / "rtl/ip/ribp/serial"
+    serial = ROOT / "rtl/ip/serial"
     source_list = tmp_path / "ws2812_dma.fl"
     source_list.write_text(
         "\n".join(
@@ -100,8 +100,8 @@ def test_ws2812_accepts_dma_fixed_destination_backpressure(tmp_path: Path) -> No
                 str(ROOT / "rtl/mini/top/rib_if.sv"),
                 str(common / "utils/register.sv"),
                 str(common / "utils/fifo.sv"),
-                str(ROOT / "rtl/ip/ribp/peripheral/dma.sv"),
-                str(ROOT / "rtl/ip/ribp/peripheral/dma_core.sv"),
+                str(ROOT / "rtl/ip/peripheral/dma.sv"),
+                str(ROOT / "rtl/ip/peripheral/dma_core.sv"),
                 str(serial / "ws2812_if.sv"),
                 str(serial / "ws2812_reg.sv"),
                 str(serial / "ws2812_core.sv"),

tests/test_xpi_io.py

@@ -35,13 +35,13 @@ def test_xpi_releases_data_pads_while_receiving(tmp_path: Path) -> None:
             [
                 "+define+SV_ASSRT_DISABLE",
                 f"+incdir+{generated / 'rtl'}",
-                f"+incdir+{ROOT / 'rtl/ip/ribp/storage'}",
+                f"+incdir+{ROOT / 'rtl/ip/storage'}",
                 f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
                 str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
                 str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
-                str(ROOT / "rtl/ip/ribp/storage/xpi.sv"),
-                str(ROOT / "rtl/ip/ribp/storage/xpi_clkgen.sv"),
-                str(ROOT / "rtl/ip/ribp/storage/xpi_core.sv"),
+                str(ROOT / "rtl/ip/storage/xpi.sv"),
+                str(ROOT / "rtl/ip/storage/xpi_clkgen.sv"),
+                str(ROOT / "rtl/ip/storage/xpi_core.sv"),
                 str(ROOT / "tests/rtl/xpi_io_tb.sv"),
                 "",
             ]