feat(hp): add the ICS55 macro path to the OpenC906 SRAM wrappers

Extend each of the eight aq_spsram_* overrides with a
PDK_ICS55+HAVE_SRAM_MACRO (without PDK_BEHAV) branch that instantiates
the matching exact-geometry ics55_ecos_sram_* macro. The ICS55 interface
polarity (CEB/GWEB/WEB active-low, per-bit WEB) matches the wrappers
exactly, so the branch is a single direct instantiation with MARE/MAR
tied off; no inversion, stacking, or padding is needed. Priority order is
PDK_BEHAV behavioral, then IHP130 macros, then ICS55 macros, else the
upstream behavioral model; the behavioral and IHP130 paths are
bit-identical.

The committed ICS55 CI/cluster profiles (HAVE_HP=YES, HAVE_SRAM_MACRO=YES,
PDK_BEHAV unset) now compile the macro path automatically.

Evidence: directed 8-wrapper equivalence TB and the manual section 3.2
MEM_INTF adaptation (Icarus) pass on the ICS55 path; the CI-flavored
ics55 profile simulation passes with SIM_TEST_PASS code=0.

rtl/mini/ip_overrides/aq_spsram_1024x16.v

@@ -9,9 +9,11 @@
 // PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 1024x16 BHT RAM is
 // built from one RM_IHPSG13_1P_1024x32_c2_bm_bist macro; only the low 16
 // bits are used and the upper mask bits are tied off so they are never
-// written. Every other configuration keeps the upstream behavioral
-// aq_f_spsram_1024x16 instance byte-identical. Keep in sync when the lock
-// revision changes.
+// written. With PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, the
+// exact-geometry ics55_ecos_sram_1024x16_m8 macro replaces it directly
+// (identical active-low polarity, no stacking or padding). Every other
+// configuration keeps the upstream behavioral aq_f_spsram_1024x16 instance
+// byte-identical. Keep in sync when the lock revision changes.
 
 /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
 
@@ -80,6 +82,14 @@ parameter WE_WIDTH   = 16;
 `endif
 `endif
 
+`ifdef PDK_ICS55
+`ifdef HAVE_SRAM_MACRO
+`ifndef PDK_BEHAV
+`define _AQ_SPSRAM_1024X16_ICS55_
+`endif
+`endif
+`endif
+
 `ifdef _AQ_SPSRAM_1024X16_IHP130_
   //********************************************************
   //*                IHP130 SRAM macro                     *
@@ -111,6 +121,22 @@ RM_IHPSG13_1P_1024x32_c2_bm_bist  u_mem (
   .A_BIST_DIN (32'b0         ),
   .A_BIST_BM  (32'b0         )
 );
+`elsif _AQ_SPSRAM_1024X16_ICS55_
+  //********************************************************
+  //*                ICS55 SRAM macro                      *
+  //********************************************************
+// Exact-geometry macro; polarities match the wrapper, direct connection.
+ics55_ecos_sram_1024x16_m8  u_mem (
+  .A    (A   ),
+  .CEB  (CEN ),
+  .CLK  (CLK ),
+  .D    (D   ),
+  .GWEB (GWEN),
+  .MARE (1'b0),
+  .MAR  (4'b0),
+  .WEB  (WEN ),
+  .Q    (Q   )
+);
 `else
   //********************************************************
   //*                        FPGA memory                   *
@@ -131,6 +157,10 @@ aq_f_spsram_1024x16  x_aq_f_spsram_1024x16 (
 `undef _AQ_SPSRAM_1024X16_IHP130_
 `endif
 
+`ifdef _AQ_SPSRAM_1024X16_ICS55_
+`undef _AQ_SPSRAM_1024X16_ICS55_
+`endif
+
 //   &Instance("aq_tsmc_spsram_1024x16"); @49
 //   &Instance("aq_umc_spsram_1024x16"); @61
 

rtl/mini/ip_overrides/aq_spsram_1024x64.v

@@ -9,9 +9,11 @@
 // PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 1024x64 DCache data
 // RAM is built from two RM_IHPSG13_1P_1024x32_c2_bm_bist macros in a width
 // stack: one macro holds the low 32 bits, the other the high 32 bits (manual
-// section 3.1.5 stacking). Every other configuration keeps the upstream
-// behavioral aq_f_spsram_1024x64 instance byte-identical. Keep in sync when
-// the lock revision changes.
+// section 3.1.5 stacking). With PDK_ICS55+HAVE_SRAM_MACRO and without
+// PDK_BEHAV, the exact-geometry ics55_ecos_sram_1024x64_m8 macro replaces it
+// directly (identical active-low polarity, no stacking or padding). Every
+// other configuration keeps the upstream behavioral aq_f_spsram_1024x64
+// instance byte-identical. Keep in sync when the lock revision changes.
 
 /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
 
@@ -80,6 +82,14 @@ parameter WE_WIDTH   = 64;
 `endif
 `endif
 
+`ifdef PDK_ICS55
+`ifdef HAVE_SRAM_MACRO
+`ifndef PDK_BEHAV
+`define _AQ_SPSRAM_1024X64_ICS55_
+`endif
+`endif
+`endif
+
 `ifdef _AQ_SPSRAM_1024X64_IHP130_
   //********************************************************
   //*                IHP130 SRAM macro                     *
@@ -130,6 +140,22 @@ RM_IHPSG13_1P_1024x32_c2_bm_bist  u_mem_hi (
   .A_BIST_DIN (32'b0       ),
   .A_BIST_BM  (32'b0       )
 );
+`elsif _AQ_SPSRAM_1024X64_ICS55_
+  //********************************************************
+  //*                ICS55 SRAM macro                      *
+  //********************************************************
+// Exact-geometry macro; polarities match the wrapper, direct connection.
+ics55_ecos_sram_1024x64_m8  u_mem (
+  .A    (A   ),
+  .CEB  (CEN ),
+  .CLK  (CLK ),
+  .D    (D   ),
+  .GWEB (GWEN),
+  .MARE (1'b0),
+  .MAR  (4'b0),
+  .WEB  (WEN ),
+  .Q    (Q   )
+);
 `else
 //  //********************************************************
 //  //*                        FPGA memory                   *
@@ -150,6 +176,10 @@ aq_f_spsram_1024x64  x_aq_f_spsram_1024x64 (
 `undef _AQ_SPSRAM_1024X64_IHP130_
 `endif
 
+`ifdef _AQ_SPSRAM_1024X64_ICS55_
+`undef _AQ_SPSRAM_1024X64_ICS55_
+`endif
+
 //   &Instance("aq_umc_spsram_1024x64"); @49
 //   &Instance("aq_tsmc_spsram_1024x64"); @55
 // &ModuleEnd; @58

rtl/mini/ip_overrides/aq_spsram_128x8.v

@@ -11,9 +11,11 @@
 // stack: A[6] selects the bank, only the low 8 bits of each macro are used
 // (upper mask bits tied off so they are never written), and the read-data
 // mux uses the bank select registered on read transactions (manual section
-// 3.1.5 stacking). Every other configuration keeps the upstream behavioral
-// aq_f_spsram_128x8 instance byte-identical. Keep in sync when the lock
-// revision changes.
+// 3.1.5 stacking). With PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV,
+// the exact-geometry ics55_ecos_sram_128x8_m8 macro replaces it directly
+// (identical active-low polarity, no stacking or padding). Every other
+// configuration keeps the upstream behavioral aq_f_spsram_128x8 instance
+// byte-identical. Keep in sync when the lock revision changes.
 
 /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
 
@@ -82,6 +84,14 @@ parameter WE_WIDTH   = 8;
 `endif
 `endif
 
+`ifdef PDK_ICS55
+`ifdef HAVE_SRAM_MACRO
+`ifndef PDK_BEHAV
+`define _AQ_SPSRAM_128X8_ICS55_
+`endif
+`endif
+`endif
+
 `ifdef _AQ_SPSRAM_128X8_IHP130_
   //********************************************************
   //*                IHP130 SRAM macro                     *
@@ -149,6 +159,22 @@ RM_IHPSG13_1P_64x64_c2_bm_bist  u_mem_hi (
   .A_BIST_DIN (64'b0         ),
   .A_BIST_BM  (64'b0         )
 );
+`elsif _AQ_SPSRAM_128X8_ICS55_
+  //********************************************************
+  //*                ICS55 SRAM macro                      *
+  //********************************************************
+// Exact-geometry macro; polarities match the wrapper, direct connection.
+ics55_ecos_sram_128x8_m8  u_mem (
+  .A    (A   ),
+  .CEB  (CEN ),
+  .CLK  (CLK ),
+  .D    (D   ),
+  .GWEB (GWEN),
+  .MARE (1'b0),
+  .MAR  (4'b0),
+  .WEB  (WEN ),
+  .Q    (Q   )
+);
 `else
 //  //********************************************************
 //  //*                        FPGA memory                   *
@@ -169,6 +195,10 @@ aq_f_spsram_128x8  x_aq_f_spsram_128x8 (
 `undef _AQ_SPSRAM_128X8_IHP130_
 `endif
 
+`ifdef _AQ_SPSRAM_128X8_ICS55_
+`undef _AQ_SPSRAM_128X8_ICS55_
+`endif
+
 //   &Instance("aq_umc_spsram_128x8"); @49
 //   &Instance("aq_tsmc_spsram_128x8"); @55
 // &ModuleEnd; @58

rtl/mini/ip_overrides/aq_spsram_2048x32.v

@@ -9,9 +9,12 @@
 // PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 2048x32 ICache data
 // RAM is built from two RM_IHPSG13_1P_1024x32_c2_bm_bist macros in a depth
 // stack: A[10] selects the bank and the read-data mux uses the bank select
-// registered on read transactions (manual section 3.1.5 stacking). Every
-// other configuration keeps the upstream behavioral aq_f_spsram_2048x32
-// instance byte-identical. Keep in sync when the lock revision changes.
+// registered on read transactions (manual section 3.1.5 stacking). With
+// PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, the exact-geometry
+// ics55_ecos_sram_2048x32_m8 macro replaces it directly (identical
+// active-low polarity, no stacking or padding). Every other configuration
+// keeps the upstream behavioral aq_f_spsram_2048x32 instance byte-identical.
+// Keep in sync when the lock revision changes.
 
 /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
 
@@ -80,6 +83,14 @@ parameter WE_WIDTH   = 32;
 `endif
 `endif
 
+`ifdef PDK_ICS55
+`ifdef HAVE_SRAM_MACRO
+`ifndef PDK_BEHAV
+`define _AQ_SPSRAM_2048X32_ICS55_
+`endif
+`endif
+`endif
+
 `ifdef _AQ_SPSRAM_2048X32_IHP130_
   //********************************************************
   //*                IHP130 SRAM macro                     *
@@ -142,6 +153,22 @@ RM_IHPSG13_1P_1024x32_c2_bm_bist  u_mem_hi (
   .A_BIST_DIN (32'b0   ),
   .A_BIST_BM  (32'b0   )
 );
+`elsif _AQ_SPSRAM_2048X32_ICS55_
+  //********************************************************
+  //*                ICS55 SRAM macro                      *
+  //********************************************************
+// Exact-geometry macro; polarities match the wrapper, direct connection.
+ics55_ecos_sram_2048x32_m8  u_mem (
+  .A    (A   ),
+  .CEB  (CEN ),
+  .CLK  (CLK ),
+  .D    (D   ),
+  .GWEB (GWEN),
+  .MARE (1'b0),
+  .MAR  (4'b0),
+  .WEB  (WEN ),
+  .Q    (Q   )
+);
 `else
   //********************************************************
   //*                        FPGA memory                   *
@@ -162,6 +189,10 @@ aq_f_spsram_2048x32  x_aq_f_spsram_2048x32 (
 `undef _AQ_SPSRAM_2048X32_IHP130_
 `endif
 
+`ifdef _AQ_SPSRAM_2048X32_ICS55_
+`undef _AQ_SPSRAM_2048X32_ICS55_
+`endif
+
 //   &Instance("aq_tsmc_spsram_2048x32"); @49
 //   &Instance("aq_umc_spsram_2048x32"); @61
 

rtl/mini/ip_overrides/aq_spsram_256x59.v

@@ -11,9 +11,12 @@
 // stack: A[7:6] selects the bank, only the low 59 bits of each macro are
 // used (upper mask bits tied off so they are never written), and the
 // read-data mux uses the bank select registered on read transactions
-// (manual section 3.1.5 stacking). Every other configuration keeps the
-// upstream behavioral aq_f_spsram_256x59 instance byte-identical. Keep in
-// sync when the lock revision changes.
+// (manual section 3.1.5 stacking). With PDK_ICS55+HAVE_SRAM_MACRO and
+// without PDK_BEHAV, the exact-geometry ics55_ecos_sram_256x59_m4 macro
+// replaces it directly (identical active-low polarity, no stacking or
+// padding). Every other configuration keeps the upstream behavioral
+// aq_f_spsram_256x59 instance byte-identical. Keep in sync when the lock
+// revision changes.
 
 /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
 
@@ -82,6 +85,14 @@ parameter WE_WIDTH   = 59;
 `endif
 `endif
 
+`ifdef PDK_ICS55
+`ifdef HAVE_SRAM_MACRO
+`ifndef PDK_BEHAV
+`define _AQ_SPSRAM_256X59_ICS55_
+`endif
+`endif
+`endif
+
 `ifdef _AQ_SPSRAM_256X59_IHP130_
   //********************************************************
   //*                IHP130 SRAM macro                     *
@@ -130,6 +141,22 @@ generate
     );
   end
 endgenerate
+`elsif _AQ_SPSRAM_256X59_ICS55_
+  //********************************************************
+  //*                ICS55 SRAM macro                      *
+  //********************************************************
+// Exact-geometry macro; polarities match the wrapper, direct connection.
+ics55_ecos_sram_256x59_m4  u_mem (
+  .A    (A   ),
+  .CEB  (CEN ),
+  .CLK  (CLK ),
+  .D    (D   ),
+  .GWEB (GWEN),
+  .MARE (1'b0),
+  .MAR  (4'b0),
+  .WEB  (WEN ),
+  .Q    (Q   )
+);
 `else
   //********************************************************
   //*                        FPGA memory                   *
@@ -150,6 +177,10 @@ aq_f_spsram_256x59  x_aq_f_spsram_256x59 (
 `undef _AQ_SPSRAM_256X59_IHP130_
 `endif
 
+`ifdef _AQ_SPSRAM_256X59_ICS55_
+`undef _AQ_SPSRAM_256X59_ICS55_
+`endif
+
 //   &Instance("aq_tsmc_spsram_256x59"); @49
 //   &Instance("aq_umc_spsram_256x59"); @61
 

rtl/mini/ip_overrides/aq_spsram_64x58.v

@@ -9,9 +9,11 @@
 // PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 64x58 DCache tag RAM
 // is built from one RM_IHPSG13_1P_64x64_c2_bm_bist macro; only the low 58
 // bits are used and the upper mask bits are tied off so they are never
-// written. Every other configuration keeps the upstream behavioral
-// aq_f_spsram_64x58 instance byte-identical. Keep in sync when the lock
-// revision changes.
+// written. With PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, the
+// exact-geometry ics55_ecos_sram_64x58_m4 macro replaces it directly
+// (identical active-low polarity, no stacking or padding). Every other
+// configuration keeps the upstream behavioral aq_f_spsram_64x58 instance
+// byte-identical. Keep in sync when the lock revision changes.
 
 /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
 
@@ -80,6 +82,14 @@ parameter WE_WIDTH   = 58;
 `endif
 `endif
 
+`ifdef PDK_ICS55
+`ifdef HAVE_SRAM_MACRO
+`ifndef PDK_BEHAV
+`define _AQ_SPSRAM_64X58_ICS55_
+`endif
+`endif
+`endif
+
 `ifdef _AQ_SPSRAM_64X58_IHP130_
   //********************************************************
   //*                IHP130 SRAM macro                     *
@@ -111,6 +121,22 @@ RM_IHPSG13_1P_64x64_c2_bm_bist  u_mem (
   .A_BIST_DIN (64'b0        ),
   .A_BIST_BM  (64'b0        )
 );
+`elsif _AQ_SPSRAM_64X58_ICS55_
+  //********************************************************
+  //*                ICS55 SRAM macro                      *
+  //********************************************************
+// Exact-geometry macro; polarities match the wrapper, direct connection.
+ics55_ecos_sram_64x58_m4  u_mem (
+  .A    (A   ),
+  .CEB  (CEN ),
+  .CLK  (CLK ),
+  .D    (D   ),
+  .GWEB (GWEN),
+  .MARE (1'b0),
+  .MAR  (4'b0),
+  .WEB  (WEN ),
+  .Q    (Q   )
+);
 `else
 //  //********************************************************
 //  //*                        FPGA memory                   *
@@ -131,6 +157,10 @@ aq_f_spsram_64x58  x_aq_f_spsram_64x58 (
 `undef _AQ_SPSRAM_64X58_IHP130_
 `endif
 
+`ifdef _AQ_SPSRAM_64X58_ICS55_
+`undef _AQ_SPSRAM_64X58_ICS55_
+`endif
+
 //   &Instance("aq_umc_spsram_64x58"); @49
 //   &Instance("aq_tsmc_spsram_64x58"); @55
 // &ModuleEnd; @58

rtl/mini/ip_overrides/aq_spsram_64x88.v

@@ -10,9 +10,11 @@
 // is built from two RM_IHPSG13_1P_64x64_c2_bm_bist macros in a width stack:
 // one macro holds the low 64 bits, the other the high 24 bits with its upper
 // mask bits tied off so they are never written (manual section 3.1.5
-// stacking). Every other configuration keeps the upstream behavioral
-// aq_f_spsram_64x88 instance byte-identical. Keep in sync when the lock
-// revision changes.
+// stacking). With PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, the
+// exact-geometry ics55_ecos_sram_64x88_m4 macro replaces it directly
+// (identical active-low polarity, no stacking or padding). Every other
+// configuration keeps the upstream behavioral aq_f_spsram_64x88 instance
+// byte-identical. Keep in sync when the lock revision changes.
 
 /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
 
@@ -81,6 +83,14 @@ parameter WE_WIDTH   = 88;
 `endif
 `endif
 
+`ifdef PDK_ICS55
+`ifdef HAVE_SRAM_MACRO
+`ifndef PDK_BEHAV
+`define _AQ_SPSRAM_64X88_ICS55_
+`endif
+`endif
+`endif
+
 `ifdef _AQ_SPSRAM_64X88_IHP130_
   //********************************************************
   //*                IHP130 SRAM macro                     *
@@ -134,6 +144,22 @@ RM_IHPSG13_1P_64x64_c2_bm_bist  u_mem_hi (
   .A_BIST_DIN (64'b0               ),
   .A_BIST_BM  (64'b0               )
 );
+`elsif _AQ_SPSRAM_64X88_ICS55_
+  //********************************************************
+  //*                ICS55 SRAM macro                      *
+  //********************************************************
+// Exact-geometry macro; polarities match the wrapper, direct connection.
+ics55_ecos_sram_64x88_m4  u_mem (
+  .A    (A   ),
+  .CEB  (CEN ),
+  .CLK  (CLK ),
+  .D    (D   ),
+  .GWEB (GWEN),
+  .MARE (1'b0),
+  .MAR  (4'b0),
+  .WEB  (WEN ),
+  .Q    (Q   )
+);
 `else
   //********************************************************
   //*                        FPGA memory                   *
@@ -155,6 +181,10 @@ aq_f_spsram_64x88  x_aq_f_spsram_64x88 (
 `undef _AQ_SPSRAM_64X88_IHP130_
 `endif
 
+`ifdef _AQ_SPSRAM_64X88_ICS55_
+`undef _AQ_SPSRAM_64X88_ICS55_
+`endif
+
 //   &Instance("aq_tsmc_spsram_64x88"); @50
 //   &Instance("aq_umc_spsram_64x88"); @62
 

rtl/mini/ip_overrides/aq_spsram_64x98.v

@@ -10,9 +10,11 @@
 // is built from two RM_IHPSG13_1P_64x64_c2_bm_bist macros in a width stack:
 // one macro holds the low 64 bits, the other the high 34 bits with its upper
 // mask bits tied off so they are never written (manual section 3.1.5
-// stacking). Every other configuration keeps the upstream behavioral
-// aq_f_spsram_64x98 instance byte-identical. Keep in sync when the lock
-// revision changes.
+// stacking). With PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, the
+// exact-geometry ics55_ecos_sram_64x98_m4 macro replaces it directly
+// (identical active-low polarity, no stacking or padding). Every other
+// configuration keeps the upstream behavioral aq_f_spsram_64x98 instance
+// byte-identical. Keep in sync when the lock revision changes.
 
 /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
 
@@ -81,6 +83,14 @@ parameter WE_WIDTH   = 98;
 `endif
 `endif
 
+`ifdef PDK_ICS55
+`ifdef HAVE_SRAM_MACRO
+`ifndef PDK_BEHAV
+`define _AQ_SPSRAM_64X98_ICS55_
+`endif
+`endif
+`endif
+
 `ifdef _AQ_SPSRAM_64X98_IHP130_
   //********************************************************
   //*                IHP130 SRAM macro                     *
@@ -134,6 +144,22 @@ RM_IHPSG13_1P_64x64_c2_bm_bist  u_mem_hi (
   .A_BIST_DIN (64'b0               ),
   .A_BIST_BM  (64'b0               )
 );
+`elsif _AQ_SPSRAM_64X98_ICS55_
+  //********************************************************
+  //*                ICS55 SRAM macro                      *
+  //********************************************************
+// Exact-geometry macro; polarities match the wrapper, direct connection.
+ics55_ecos_sram_64x98_m4  u_mem (
+  .A    (A   ),
+  .CEB  (CEN ),
+  .CLK  (CLK ),
+  .D    (D   ),
+  .GWEB (GWEN),
+  .MARE (1'b0),
+  .MAR  (4'b0),
+  .WEB  (WEN ),
+  .Q    (Q   )
+);
 `else
   //********************************************************
   //*                        FPGA memory                   *
@@ -155,6 +181,10 @@ aq_f_spsram_64x98  x_aq_f_spsram_64x98 (
 `undef _AQ_SPSRAM_64X98_IHP130_
 `endif
 
+`ifdef _AQ_SPSRAM_64X98_ICS55_
+`undef _AQ_SPSRAM_64X98_ICS55_
+`endif
+
 //   &Instance("aq_tsmc_spsram_64x98"); @50
 //   &Instance("aq_umc_spsram_64x98"); @62