refactor: refactor APB4 and AXI4 references in RTL and test files

- Updated RTL style audit to reflect new APB4 naming conventions.
- Changed performance log parsing to accommodate new APB4 wait signals.
- Modified AXI4 interconnect and rib bus testbenches to use updated performance wait signals.
- Adjusted IRQ topology testbench to use new APB4 peripheral and system IRQ widths.
- Updated sysctrl testbench to reflect changes in APB4 performance wait signals.
- Refined memory map tests to check for new APB4 definitions.
- Enhanced performance log tests to validate new APB4 wait signal parsing.
- Revised SOC topology tests to ensure correct APB4 peripheral and system bindings.
- Updated user extensions tests to align with new APB4 interface naming.

scripts/parse_performance_log.py

@@ -20,7 +20,7 @@ REQUIRED_FIELDS = {
     "checksum",
     "cycles",
     "mgmt_wait",
-    "apb4_wait",
+    "apb4_periph_wait",
     "sdram_wait",
     "psram_wait",
     "flash_wait",