refactor: refactor Makefiles and related scripts for improved readability and consistency

- Adjusted variable alignment in Makefiles for better readability.
- Ensured consistent formatting across various Makefiles and scripts.
- Added a new .bake.toml file to define project formatting policies for mbake.
- Updated paths and variable definitions in multiple configuration files to enhance clarity.
- Removed unnecessary comments and whitespace for cleaner code.

.bake.toml

@@ -0,0 +1,5 @@
+# Project formatting policy for mbake.
+[formatter]
+# Align adjacent assignments, but start a new alignment group at comments.
+align_variable_assignments = true
+align_across_comments = false

Makefile

@@ -57,7 +57,7 @@ HOST_CC        ?= cc
 CLANG_FORMAT    ?= clang-format-14
 JOBS            ?= $(shell count=$$(nproc 2>/dev/null || printf '1'); \
                        if [ "$$count" -gt "$(MAX_JOBS)" ]; then printf '%s' '$(MAX_JOBS)'; \
-                       else printf '%s' "$$count"; fi)
+else printf '%s' "$$count"; fi)
 CONFIG_KEY_VARS := SOC CORE IP PDK HAVE_PLL HAVE_SRAM_IF HAVE_SRAM_MACRO HAVE_SVA \
                    ISA HAVE_CSR APP LINK_TYPE RTL_TOP FIRMWARE_NAME
 VARIANT_ID      := $(strip $(shell python3 $(ROOT_PATH)/scripts/config_key.py \

rtl/mini/mk/vcs.mk

@@ -86,7 +86,6 @@ wave:     DIR   := $(SIM_BUILD_ROOT)/behv
 netwave:  DIR   := $(SIM_BUILD_ROOT)/netl
 postwave: DIR   := $(SIM_BUILD_ROOT)/post
 
-
 comp: $(VCS_BEHV_SIMV)
 netcomp: $(VCS_NETL_SIMV)
 postcomp: $(VCS_POST_SIMV)

rtl/mini/mk/verilator.mk

@@ -9,8 +9,6 @@ SOC_VSRC_TOP      := retrosoc_top
 SOC_VSRC_HOME    += $(RTL_PATH)/dv/verilator/rtl
 SOC_COMPILE_HOME := $(BUILD_DIR)/emu_compile
 
-
-
 SOC_VXXFILES      := $(RTL_FLIST)
 SOC_VXXFILES      += $(RTL_PATH)/dv/model/ESP_PSRAM64H.sv
 SOC_VXXFILES      += $(RTL_PATH)/dv/verilator/rtl/flash_read_binder.sv