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refactor: refactor Makefiles and related scripts for improved readability and consistency

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- Adjusted variable alignment in Makefiles for better readability.
- Ensured consistent formatting across various Makefiles and scripts.
- Added a new .bake.toml file to define project formatting policies for mbake.
- Updated paths and variable definitions in multiple configuration files to enhance clarity.
- Removed unnecessary comments and whitespace for cleaner code.
This commit is contained in:
maksyuki committed 2026-07-21 11:21:39 +08:00
1 parent f5b373fd65
commit 7418acfe42
17 files changed
+211 -209
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.bake.toml
+5
View File
@@ -0,0 +1,5 @@
# Project formatting policy for mbake.
[formatter]
# Align adjacent assignments, but start a new alignment group at comments.
align_variable_assignments = true
align_across_comments = false
Makefile
+39 -39
View File
@@ -2,9 +2,9 @@ SHELL := /bin/bash
.DEFAULT_GOAL := help
.DELETE_ON_ERROR:
ROOT_PATH ?= $(abspath $(dir $(firstword $(MAKEFILE_LIST))))
CONFIG ?=
LOCK_FILE ?= $(ROOT_PATH)/config/dependencies.lock.json
ROOT_PATH ?= $(abspath $(dir $(firstword $(MAKEFILE_LIST))))
CONFIG ?=
LOCK_FILE ?= $(ROOT_PATH)/config/dependencies.lock.json
ifneq ($(strip $(CONFIG)),)
CONFIG_PATH := $(if $(filter /%,$(CONFIG)),$(CONFIG),$(ROOT_PATH)/$(CONFIG))
@@ -14,14 +14,14 @@ endif
include $(CONFIG_PATH)
PROFILE_NAME := $(basename $(notdir $(CONFIG_PATH)))
else
CONFIG_PATH :=
CONFIG_PATH :=
PROFILE_NAME := manual
endif
SOC ?= MINI
SIMU ?= VCS
SYNTH ?= NONE
STA ?= NONE
SOC ?= MINI
SIMU ?= VCS
SYNTH ?= NONE
STA ?= NONE
# HW
PDK ?= IHP130
@@ -31,36 +31,36 @@ HAVE_SRAM_MACRO ?= NO
HAVE_SVA ?= NO
WAVE ?= NO
RTL_SIM_CORESEL ?= 0
RTL_SIM_TIMEOUT ?= -1
SIM_FIRMWARE_NAME ?= $(FIRMWARE_NAME)
RTL_SIM_CORESEL ?= 0
RTL_SIM_TIMEOUT ?= -1
SIM_FIRMWARE_NAME ?= $(FIRMWARE_NAME)
SIM_SUCCESS_MARKER ?= retroSoC: A Customized ASIC for Retro Stuff
RTL_PATH := $(ROOT_PATH)/rtl/mini
RTL_PATH := $(ROOT_PATH)/rtl/mini
CORE ?= HAZARD3
IP ?= NONE
RTL_TOP ?= retrosoc_tb
CORE ?= HAZARD3
IP ?= NONE
RTL_TOP ?= retrosoc_tb
# SW
ISA ?= RV32IM
HAVE_CSR ?= NO
FIRMWARE_NAME ?= retrosoc_fw
APP ?= shell
LINK_TYPE ?= ld2_sram
ISA ?= RV32IM
HAVE_CSR ?= NO
FIRMWARE_NAME ?= retrosoc_fw
APP ?= shell
LINK_TYPE ?= ld2_sram
BUILD_ROOT ?= $(ROOT_PATH)/build
CACHE_ROOT ?= $(ROOT_PATH)/.cache/retrosoc
BUILD_ROOT ?= $(ROOT_PATH)/build
CACHE_ROOT ?= $(ROOT_PATH)/.cache/retrosoc
BUILD_TIMESTAMP ?= $(shell date '+%Y-%m-%d-%H-%M')
MAX_JOBS ?= 16
HOST_CC ?= cc
CLANG_FORMAT ?= clang-format-14
JOBS ?= $(shell count=$$(nproc 2>/dev/null || printf '1'); \
MAX_JOBS ?= 16
HOST_CC ?= cc
CLANG_FORMAT ?= clang-format-14
JOBS ?= $(shell count=$$(nproc 2>/dev/null || printf '1'); \
if [ "$$count" -gt "$(MAX_JOBS)" ]; then printf '%s' '$(MAX_JOBS)'; \
else printf '%s' "$$count"; fi)
else printf '%s' "$$count"; fi)
CONFIG_KEY_VARS := SOC CORE IP PDK HAVE_PLL HAVE_SRAM_IF HAVE_SRAM_MACRO HAVE_SVA \
ISA HAVE_CSR APP LINK_TYPE RTL_TOP FIRMWARE_NAME
VARIANT_ID := $(strip $(shell python3 $(ROOT_PATH)/scripts/config_key.py \
VARIANT_ID := $(strip $(shell python3 $(ROOT_PATH)/scripts/config_key.py \
--lock $(LOCK_FILE) --profile $(PROFILE_NAME) --timestamp $(BUILD_TIMESTAMP) \
$(foreach var,$(CONFIG_KEY_VARS),--value $(var)=$($(var)))))
ifeq ($(VARIANT_ID),)
@@ -68,13 +68,13 @@ $(error Failed to calculate build variant ID)
endif
LOCK_DIGEST := $(strip $(shell python3 $(ROOT_PATH)/scripts/dependency_lock.py --lock $(LOCK_FILE) --digest))
export BUILD_TIMESTAMP
VARIANT_ROOT := $(abspath $(BUILD_ROOT))/$(VARIANT_ID)
SW_BUILD_DIR := $(VARIANT_ROOT)/sw
SIM_TOOL_NAME := $(shell printf '%s' '$(SIMU)' | tr '[:upper:]' '[:lower:]')
VARIANT_ROOT := $(abspath $(BUILD_ROOT))/$(VARIANT_ID)
SW_BUILD_DIR := $(VARIANT_ROOT)/sw
SIM_TOOL_NAME := $(shell printf '%s' '$(SIMU)' | tr '[:upper:]' '[:lower:]')
SIM_BUILD_ROOT := $(VARIANT_ROOT)/sim/$(SIM_TOOL_NAME)
SYN_BUILD_ROOT := $(VARIANT_ROOT)/syn/yosys
STA_BUILD_ROOT := $(VARIANT_ROOT)/sta/opensta
META_DIR := $(VARIANT_ROOT)/meta
META_DIR := $(VARIANT_ROOT)/meta
ifeq ($(SYNTH),YOSYS)
FLOW_FILELIST_DIR := $(SYN_BUILD_ROOT)/filelists
else
@@ -126,10 +126,10 @@ $(error OpenSTA currently supports PDK=IHP130 only)
endif
endif
DEF_LIST ?= +define+PDK_$(PDK)
DEF_LIST += +define+CORE_$(CORE)
DEF_LIST += +define+IP_$(IP)
DEF_LIST += +define+SIMU_$(SIMU)
DEF_LIST ?= +define+PDK_$(PDK)
DEF_LIST += +define+CORE_$(CORE)
DEF_LIST += +define+IP_$(IP)
DEF_LIST += +define+SIMU_$(SIMU)
ifeq ($(HAVE_PLL), YES)
DEF_LIST += +define+HAVE_PLL
@@ -162,9 +162,9 @@ ifeq ($(STA), OPENSTA)
endif
.PHONY: help config doctor setup setup-mpw setup-core setup-clusterip setup-ip setup-pdk setup-app \
clean-all purge-cache manifest check-warnings metrics check-metrics package \
regress-pr regress-nightly sim-asm sw-format sw-format-check sw-policy-check sw-host-test \
pin-map check-pin-map
clean-all purge-cache manifest check-warnings metrics check-metrics package \
regress-pr regress-nightly sim-asm sw-format sw-format-check sw-policy-check sw-host-test \
pin-map check-pin-map
.NOTPARALLEL: setup
help:
app/asm/Makefile
+7 -7
View File
@@ -2,15 +2,15 @@
GCC = riscv32-unknown-elf-
AS = $(GCC)as
LD = $(GCC)ld
OBJDUMP = $(GCC)objdump
OBJCOPY = $(GCC)objcopy
AS = $(GCC)as
LD = $(GCC)ld
OBJDUMP = $(GCC)objdump
OBJCOPY = $(GCC)objcopy
AS_FLAGS = -fno-pic -march=rv32im -mabi=ilp32
LDFLAGS = -T flash.ld -melf32lriscv
APP ?= hello
OUT_DIR ?= .
APP_ALL = $(OUT_DIR)/$(APP)-asm
APP ?= hello
OUT_DIR ?= .
APP_ALL = $(OUT_DIR)/$(APP)-asm
all: $(APP).s
@mkdir -p $(OUT_DIR)
app/network/userip/userip.mk
+1 -1
View File
@@ -1,5 +1,5 @@
# User IP is optional and is linked only for MDD configurations.
ifeq ($(IP), MDD)
APP_SRCS += $(ROOT_PATH)/app/network/userip/userip.c
APP_SRCS += $(ROOT_PATH)/app/network/userip/userip.c
APP_INC_DIRS += $(ROOT_PATH)/app/network/userip
endif
configs/ci/hazard3-rv32im-ihp130-shell.mk
+11 -11
View File
@@ -1,12 +1,12 @@
SOC := MINI
CORE := HAZARD3
IP := NONE
PDK := IHP130
HAVE_PLL := NO
HAVE_SRAM_IF := NO
SOC := MINI
CORE := HAZARD3
IP := NONE
PDK := IHP130
HAVE_PLL := NO
HAVE_SRAM_IF := NO
HAVE_SRAM_MACRO := NO
HAVE_SVA := NO
ISA := RV32IM
HAVE_CSR := YES
APP := shell
LINK_TYPE := ld2_psram
HAVE_SVA := NO
ISA := RV32IM
HAVE_CSR := YES
APP := shell
LINK_TYPE := ld2_psram
configs/ci/hazard3-rv32im-ihp130.mk
+11 -11
View File
@@ -1,12 +1,12 @@
SOC := MINI
CORE := HAZARD3
IP := NONE
PDK := IHP130
HAVE_PLL := NO
HAVE_SRAM_IF := NO
SOC := MINI
CORE := HAZARD3
IP := NONE
PDK := IHP130
HAVE_PLL := NO
HAVE_SRAM_IF := NO
HAVE_SRAM_MACRO := NO
HAVE_SVA := NO
ISA := RV32IM
HAVE_CSR := NO
APP := bringup
LINK_TYPE := ld2_psram
HAVE_SVA := NO
ISA := RV32IM
HAVE_CSR := NO
APP := bringup
LINK_TYPE := ld2_psram
configs/ci/mdd-rv32im-ihp130.mk
+11 -11
View File
@@ -1,12 +1,12 @@
SOC := MINI
CORE := MDD
IP := NONE
PDK := IHP130
HAVE_PLL := NO
HAVE_SRAM_IF := NO
SOC := MINI
CORE := MDD
IP := NONE
PDK := IHP130
HAVE_PLL := NO
HAVE_SRAM_IF := NO
HAVE_SRAM_MACRO := NO
HAVE_SVA := NO
ISA := RV32IM
HAVE_CSR := NO
APP := bringup
LINK_TYPE := ld2_psram
HAVE_SVA := NO
ISA := RV32IM
HAVE_CSR := NO
APP := bringup
LINK_TYPE := ld2_psram
configs/cluster/hazard3-ics55.mk
+11 -11
View File
@@ -1,12 +1,12 @@
SOC := MINI
CORE := HAZARD3
IP := NONE
PDK := ICS55
HAVE_PLL := NO
HAVE_SRAM_IF := NO
SOC := MINI
CORE := HAZARD3
IP := NONE
PDK := ICS55
HAVE_PLL := NO
HAVE_SRAM_IF := NO
HAVE_SRAM_MACRO := NO
HAVE_SVA := NO
ISA := RV32IM
HAVE_CSR := NO
APP := bringup
LINK_TYPE := ld2_psram
HAVE_SVA := NO
ISA := RV32IM
HAVE_CSR := NO
APP := bringup
LINK_TYPE := ld2_psram
configs/nightly/picorv32-rv32im-ihp130.mk
+11 -11
View File
@@ -1,12 +1,12 @@
SOC := MINI
CORE := PICORV32
IP := NONE
PDK := IHP130
HAVE_PLL := NO
HAVE_SRAM_IF := NO
SOC := MINI
CORE := PICORV32
IP := NONE
PDK := IHP130
HAVE_PLL := NO
HAVE_SRAM_IF := NO
HAVE_SRAM_MACRO := NO
HAVE_SVA := NO
ISA := RV32IM
HAVE_CSR := NO
APP := bringup
LINK_TYPE := ld2_psram
HAVE_SVA := NO
ISA := RV32IM
HAVE_CSR := NO
APP := bringup
LINK_TYPE := ld2_psram
rtl/mini/Makefile
+28 -28
View File
@@ -1,29 +1,29 @@
GENERATED_FL_DIR := $(FLOW_FILELIST_DIR)
MEMORY_MAP_SOURCE := $(RTL_PATH)/address_map/memory_map.json
MEMORY_MAP_SCRIPT := $(RTL_PATH)/address_map/generate_memory_map.py
MEMORY_MAP_DIR := $(VARIANT_ROOT)/generated/memory_map
MEMORY_MAP_STAMP := $(MEMORY_MAP_DIR)/.stamp
MEMORY_MAP_RTL_DIR := $(MEMORY_MAP_DIR)/rtl
MEMORY_MAP_C_DIR := $(MEMORY_MAP_DIR)/include
GENERATED_FL_DIR := $(FLOW_FILELIST_DIR)
MEMORY_MAP_SOURCE := $(RTL_PATH)/address_map/memory_map.json
MEMORY_MAP_SCRIPT := $(RTL_PATH)/address_map/generate_memory_map.py
MEMORY_MAP_DIR := $(VARIANT_ROOT)/generated/memory_map
MEMORY_MAP_STAMP := $(MEMORY_MAP_DIR)/.stamp
MEMORY_MAP_RTL_DIR := $(MEMORY_MAP_DIR)/rtl
MEMORY_MAP_C_DIR := $(MEMORY_MAP_DIR)/include
MEMORY_MAP_LINKER_DIR := $(MEMORY_MAP_DIR)/linker
MEMORY_MAP_FILELIST := $(MEMORY_MAP_DIR)/memory_map.fl
PIN_MAP_SOURCE := $(RTL_PATH)/pin_map/pin_map.json
PIN_MAP_SCRIPT := $(RTL_PATH)/pin_map/generate_pin_map.py
PIN_MAP_DIR := $(VARIANT_ROOT)/generated/pin_map
PIN_MAP_STAMP := $(PIN_MAP_DIR)/.stamp
PIN_MAP_FILELIST := $(PIN_MAP_DIR)/pin_map.fl
MPW_STAMP := $(CACHE_ROOT)/stamps/mpw-$(LOCK_DIGEST).prepared
MPW_OUTPUT_DIR := $(VARIANT_ROOT)/generated/mpw/$(SIM_TOOL_NAME)
MPW_VARIANT_STAMP := $(MPW_OUTPUT_DIR)/.stamp
FILELIST_STAMP := $(GENERATED_FL_DIR)/.stamp
FILELIST_TEMPLATES := $(sort $(wildcard $(ROOT_PATH)/rtl/filelist/pdk_*.fl) \
MEMORY_MAP_FILELIST := $(MEMORY_MAP_DIR)/memory_map.fl
PIN_MAP_SOURCE := $(RTL_PATH)/pin_map/pin_map.json
PIN_MAP_SCRIPT := $(RTL_PATH)/pin_map/generate_pin_map.py
PIN_MAP_DIR := $(VARIANT_ROOT)/generated/pin_map
PIN_MAP_STAMP := $(PIN_MAP_DIR)/.stamp
PIN_MAP_FILELIST := $(PIN_MAP_DIR)/pin_map.fl
MPW_STAMP := $(CACHE_ROOT)/stamps/mpw-$(LOCK_DIGEST).prepared
MPW_OUTPUT_DIR := $(VARIANT_ROOT)/generated/mpw/$(SIM_TOOL_NAME)
MPW_VARIANT_STAMP := $(MPW_OUTPUT_DIR)/.stamp
FILELIST_STAMP := $(GENERATED_FL_DIR)/.stamp
FILELIST_TEMPLATES := $(sort $(wildcard $(ROOT_PATH)/rtl/filelist/pdk_*.fl) \
$(wildcard $(RTL_PATH)/filelist/*.fl) $(RTL_PATH)/lint.msg)
$(MPW_STAMP):
@test -d $(ROOT_PATH)/rtl/managed/mpw/.git || { \
echo "missing $(ROOT_PATH)/rtl/managed/mpw; run 'make setup-mpw' first" >&2; \
exit 1; \
}
}
python3 $(ROOT_PATH)/scripts/prepare_mpw.py \
--lock-file $(CACHE_ROOT)/locks/mpw-prepare.lock
@mkdir -p $(@D)
@@ -58,7 +58,7 @@ check-pin-map:
python3 $(PIN_MAP_SCRIPT) --map $(PIN_MAP_SOURCE) --check
$(FILELIST_STAMP): $(FILELIST_TEMPLATES) $(RTL_PATH)/script/generate_filelist.py \
$(RTL_PATH)/script/filelist.py $(MEMORY_MAP_STAMP) $(PIN_MAP_STAMP)
$(RTL_PATH)/script/filelist.py $(MEMORY_MAP_STAMP) $(PIN_MAP_STAMP)
python3 $(RTL_PATH)/script/generate_filelist.py \
--output-dir $(GENERATED_FL_DIR) \
$(foreach define,$(DEF_LIST),--define $(define))
@@ -80,15 +80,15 @@ else ifeq ($(PDK), GF180)
NET_FLIST := -f $(GENERATED_FL_DIR)/pdk_gf180.fl
endif
NET_FLIST += -f $(GENERATED_FL_DIR)/def.fl
NET_FLIST += -f $(GENERATED_FL_DIR)/sys_def.fl
NET_FLIST += -f $(GENERATED_FL_DIR)/commonip.fl
NET_FLIST += -f $(GENERATED_FL_DIR)/inc.fl
NET_FLIST += -f $(GENERATED_FL_DIR)/def.fl
NET_FLIST += -f $(GENERATED_FL_DIR)/sys_def.fl
NET_FLIST += -f $(GENERATED_FL_DIR)/commonip.fl
NET_FLIST += -f $(GENERATED_FL_DIR)/inc.fl
RTL_FLIST := -f $(MEMORY_MAP_FILELIST) -f $(PIN_MAP_FILELIST) $(NET_FLIST)
RTL_FLIST += -f $(GENERATED_FL_DIR)/clusterip.fl
RTL_FLIST += -f $(GENERATED_FL_DIR)/ip.fl
RTL_FLIST += -f $(GENERATED_FL_DIR)/tech.fl
RTL_FLIST := -f $(MEMORY_MAP_FILELIST) -f $(PIN_MAP_FILELIST) $(NET_FLIST)
RTL_FLIST += -f $(GENERATED_FL_DIR)/clusterip.fl
RTL_FLIST += -f $(GENERATED_FL_DIR)/ip.fl
RTL_FLIST += -f $(GENERATED_FL_DIR)/tech.fl
ifeq ($(CORE), PICORV32)
RTL_FLIST += -f $(GENERATED_FL_DIR)/core_picorv32.fl
rtl/mini/mk/iverilog.mk
+19 -19
View File
@@ -1,24 +1,24 @@
IVERILOG ?= iverilog
VVP ?= vvp
GTKWAVE ?= gtkwave
IVERILOG ?= iverilog
VVP ?= vvp
GTKWAVE ?= gtkwave
NETLIST_PATH ?= $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.v
POST_PATH ?= $(ROOT_PATH)/pd/sdf/retrosoc_asic.v
SDF_PATH ?= $(ROOT_PATH)/pd/sdf/retrosoc_asic_CTS_MIN.sdf.gz
SDF_SCOPE ?= $(RTL_TOP).u_retrosoc_asic
NETLIST_PATH ?= $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.v
POST_PATH ?= $(ROOT_PATH)/pd/sdf/retrosoc_asic.v
SDF_PATH ?= $(ROOT_PATH)/pd/sdf/retrosoc_asic_CTS_MIN.sdf.gz
SDF_SCOPE ?= $(RTL_TOP).u_retrosoc_asic
IVERILOG_ROOT := $(SIM_BUILD_ROOT)
IVERILOG_BEHV_DIR := $(IVERILOG_ROOT)/behv
IVERILOG_NETL_DIR := $(IVERILOG_ROOT)/netl
IVERILOG_POST_DIR := $(IVERILOG_ROOT)/post
IVERILOG_BEHV_FLIST := $(IVERILOG_BEHV_DIR)/iverilog.fl
IVERILOG_NETL_FLIST := $(IVERILOG_NETL_DIR)/iverilog.fl
IVERILOG_POST_FLIST := $(IVERILOG_POST_DIR)/iverilog.fl
CONVERTED_SOC := $(IVERILOG_BEHV_DIR)/converted_soc.v
CONVERTED_DEPFILE := $(IVERILOG_BEHV_DIR)/converted_soc.d
IVERILOG_BEHV_SIMV := $(IVERILOG_BEHV_DIR)/simv
IVERILOG_NETL_SIMV := $(IVERILOG_NETL_DIR)/simv
IVERILOG_POST_SIMV := $(IVERILOG_POST_DIR)/simv
IVERILOG_ROOT := $(SIM_BUILD_ROOT)
IVERILOG_BEHV_DIR := $(IVERILOG_ROOT)/behv
IVERILOG_NETL_DIR := $(IVERILOG_ROOT)/netl
IVERILOG_POST_DIR := $(IVERILOG_ROOT)/post
IVERILOG_BEHV_FLIST := $(IVERILOG_BEHV_DIR)/iverilog.fl
IVERILOG_NETL_FLIST := $(IVERILOG_NETL_DIR)/iverilog.fl
IVERILOG_POST_FLIST := $(IVERILOG_POST_DIR)/iverilog.fl
CONVERTED_SOC := $(IVERILOG_BEHV_DIR)/converted_soc.v
CONVERTED_DEPFILE := $(IVERILOG_BEHV_DIR)/converted_soc.d
IVERILOG_BEHV_SIMV := $(IVERILOG_BEHV_DIR)/simv
IVERILOG_NETL_SIMV := $(IVERILOG_NETL_DIR)/simv
IVERILOG_POST_SIMV := $(IVERILOG_POST_DIR)/simv
IVERILOG_BEHV_DEPFILE := $(IVERILOG_BEHV_DIR)/simv.d
IVERILOG_NETL_DEPFILE := $(IVERILOG_NETL_DIR)/simv.d
IVERILOG_POST_DEPFILE := $(IVERILOG_POST_DIR)/simv.d
rtl/mini/mk/software.mk
+12 -12
View File
@@ -1,12 +1,12 @@
# Software SDK and application build
CROSS ?= riscv32-unknown-elf-
CP = $(CROSS)cpp
CC = $(CROSS)gcc
CP = $(CROSS)cpp
CC = $(CROSS)gcc
OBJC = $(CROSS)objcopy
DUMP = $(CROSS)objdump
GCC_FLAGS := -std=gnu11 -Wall -Wextra \
GCC_FLAGS := -std=gnu11 -Wall -Wextra \
-Wl,-Bstatic,-T,$(LINK_TYPE).lds,--strip-debug -O3 \
-ffreestanding -nostdlib
SW_WARN_FLAGS := -Wformat=2 -Wshadow -Wstrict-prototypes -Wmissing-prototypes \
@@ -91,9 +91,9 @@ CRT_SRCS += $(ROOT_PATH)/crt/src/core/system_irq_handler.c
CRT_SRCS += $(ROOT_PATH)/crt/src/core/irq.c
endif
APP_SRCS :=
APP_SRCS :=
APP_INC_DIRS :=
APP_MK := $(ROOT_PATH)/app/apps/$(APP)/app.mk
APP_MK := $(ROOT_PATH)/app/apps/$(APP)/app.mk
ifeq ($(wildcard $(APP_MK)),)
$(error Application profile not found: $(APP_MK))
@@ -110,17 +110,17 @@ CRT_SRCS += $(ROOT_PATH)/crt/arch/riscv/libgcc/muldi3.S
CRT_SRCS += $(ROOT_PATH)/crt/arch/riscv/libgcc/mulsi3.c
endif
INC_PATH := -I$(SW_BUILD_DIR)/include \
INC_PATH := -I$(SW_BUILD_DIR)/include \
-I$(MEMORY_MAP_C_DIR) \
-I$(ROOT_PATH)/crt/include \
$(addprefix -I,$(APP_INC_DIRS))
SRC_PATH := $(CRT_SRCS) $(APP_SRCS)
LDS_PATH := $(ROOT_PATH)/crt/linker/$(LINK_TYPE).lds
SRC_PATH := $(CRT_SRCS) $(APP_SRCS)
LDS_PATH := $(ROOT_PATH)/crt/linker/$(LINK_TYPE).lds
MEMORY_REGIONS_LD := $(MEMORY_MAP_LINKER_DIR)/memory_regions.ld
VERSION_HEADER := $(SW_BUILD_DIR)/include/socver.h
FIRMWARE_ELF := $(SW_BUILD_DIR)/firmware
VERSION_HEADER := $(SW_BUILD_DIR)/include/socver.h
FIRMWARE_ELF := $(SW_BUILD_DIR)/firmware
ASM_FIRMWARE_NAME ?= retrosoc_asm
SW_HEADERS := $(shell find $(ROOT_PATH)/crt/include $(ROOT_PATH)/app -type f \
SW_HEADERS := $(shell find $(ROOT_PATH)/crt/include $(ROOT_PATH)/app -type f \
\( -name '*.h' -o -name '*.hpp' \) 2>/dev/null)
$(VERSION_HEADER): FORCE_VERSION $(ROOT_PATH)/crt/ver.py $(ROOT_PATH)/crt/ver.tmpl
@@ -139,7 +139,7 @@ asm: $(MPW_VARIANT_STAMP)
cp $(SW_BUILD_DIR)/asm/hello-asm.txt $(SW_BUILD_DIR)/$(ASM_FIRMWARE_NAME)_all.txt
$(FIRMWARE_ELF): $(MPW_VARIANT_STAMP) $(MEMORY_MAP_STAMP) $(VERSION_HEADER) $(SRC_PATH) $(SW_HEADERS) $(LDS_PATH) \
$(ROOT_PATH)/rtl/mini/mk/software.mk
$(ROOT_PATH)/rtl/mini/mk/software.mk
@mkdir -p $(SW_BUILD_DIR)
cd $(SW_BUILD_DIR) && $(CP) -P -o $(LINK_TYPE).lds $(LDS_PATH)
cp $(MEMORY_REGIONS_LD) $(SW_BUILD_DIR)/memory_regions.ld
rtl/mini/mk/vcs.mk
+19 -20
View File
@@ -1,20 +1,20 @@
# tools & paths
NOVAS ?= /nfs/tools/synopsys/verdi/V-2023.12-SP1-1/share/PLI/VCS/LINUX64
VCS_RUNNER ?= bsub -Is
VCS ?= vcs
VERDI ?= verdi
EXTRA ?= -P $(NOVAS)/novas.tab $(NOVAS)/pli.a
SIM_TOOL := $(VCS_RUNNER) $(VCS)
SIM_BINY := $(VCS_RUNNER) ./simv
VERDI_TOOL := $(VCS_RUNNER) $(VERDI)
COMP_LOG := -l compile.log
SIM_LOG := -l sim.log
NOVAS ?= /nfs/tools/synopsys/verdi/V-2023.12-SP1-1/share/PLI/VCS/LINUX64
VCS_RUNNER ?= bsub -Is
VCS ?= vcs
VERDI ?= verdi
EXTRA ?= -P $(NOVAS)/novas.tab $(NOVAS)/pli.a
SIM_TOOL := $(VCS_RUNNER) $(VCS)
SIM_BINY := $(VCS_RUNNER) ./simv
VERDI_TOOL := $(VCS_RUNNER) $(VERDI)
COMP_LOG := -l compile.log
SIM_LOG := -l sim.log
# netlist file path
NETLIST_PATH := -v $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.v
POST_PATH := -v $(ROOT_PATH)/pd/sdf/retrosoc_asic.v
SDF_PATH := "$(ROOT_PATH)/pd/sdf/retrosoc_asic_CTS_MIN.sdf.gz"
# testbench filelist
TB_FLIST := -f $(GENERATED_FL_DIR)/tb.fl
TB_FLIST := -f $(GENERATED_FL_DIR)/tb.fl
## vcs option
# -debug_region=cell+lib
@@ -23,7 +23,7 @@ TB_FLIST := -f $(GENERATED_FL_DIR)/tb.fl
# -error=all(turn all warning into error)
# +vcs+loopreport+100000 \
# --- Compilation Flags ---
COMMON_OPTS := -full64 +v2k -sverilog -timescale=1ns/10ps \
COMMON_OPTS := -full64 +v2k -sverilog -timescale=1ns/10ps \
$(EXTRA) \
-kdb \
-debug_access+all \
@@ -35,7 +35,7 @@ COMMON_OPTS := -full64 +v2k -sverilog -timescale=1ns/10ps \
-reportstats \
-work DEFAULT
POST_OPTS := -sdf min:retrosoc_tb.u_retrosoc_asic:$(SDF_PATH) \
POST_OPTS := -sdf min:retrosoc_tb.u_retrosoc_asic:$(SDF_PATH) \
+delay_mode_path \
+sdfverbose \
+neg_tchk \
@@ -48,12 +48,12 @@ TIME_OPTION := +notimingcheck +nospecify
SIM_OPTS := +vcs+loopreport+1000 -suppress=ASLR_DETECTED_INFO \
+core_sel=$(RTL_SIM_CORESEL) +sim_timeout=$(RTL_SIM_TIMEOUT) +wave_$(WAVE)
VCS_BEHV_DIR := $(SIM_BUILD_ROOT)/behv
VCS_NETL_DIR := $(SIM_BUILD_ROOT)/netl
VCS_POST_DIR := $(SIM_BUILD_ROOT)/post
VCS_BEHV_SIMV := $(VCS_BEHV_DIR)/simv
VCS_NETL_SIMV := $(VCS_NETL_DIR)/simv
VCS_POST_SIMV := $(VCS_POST_DIR)/simv
VCS_BEHV_DIR := $(SIM_BUILD_ROOT)/behv
VCS_NETL_DIR := $(SIM_BUILD_ROOT)/netl
VCS_POST_DIR := $(SIM_BUILD_ROOT)/post
VCS_BEHV_SIMV := $(VCS_BEHV_DIR)/simv
VCS_NETL_SIMV := $(VCS_NETL_DIR)/simv
VCS_POST_SIMV := $(VCS_POST_DIR)/simv
VCS_BEHV_DEPFILE := $(VCS_BEHV_DIR)/simv.d
VCS_NETL_DEPFILE := $(VCS_NETL_DIR)/simv.d
VCS_POST_DEPFILE := $(VCS_POST_DIR)/simv.d
@@ -86,7 +86,6 @@ wave: DIR := $(SIM_BUILD_ROOT)/behv
netwave: DIR := $(SIM_BUILD_ROOT)/netl
postwave: DIR := $(SIM_BUILD_ROOT)/post
comp: $(VCS_BEHV_SIMV)
netcomp: $(VCS_NETL_SIMV)
postcomp: $(VCS_POST_SIMV)
rtl/mini/mk/verilator.mk
+7 -9
View File
@@ -5,11 +5,9 @@ SOC_CXXFILES += $(sort $(wildcard $(SOC_CSRC_HOME)/*.cpp))
SOC_CSRC_INCLPATH += -I$(SOC_CSRC_HOME)
SOC_CSRC_INCLPATH += $(foreach val, $(SOC_CSRC_LIB_HOME), -I$(val))
SOC_VSRC_TOP := retrosoc_top
SOC_VSRC_HOME += $(RTL_PATH)/dv/verilator/rtl
SOC_COMPILE_HOME := $(BUILD_DIR)/emu_compile
SOC_VSRC_TOP := retrosoc_top
SOC_VSRC_HOME += $(RTL_PATH)/dv/verilator/rtl
SOC_COMPILE_HOME := $(BUILD_DIR)/emu_compile
SOC_VXXFILES := $(RTL_FLIST)
SOC_VXXFILES += $(RTL_PATH)/dv/model/ESP_PSRAM64H.sv
@@ -29,10 +27,10 @@ VERILATOR_FLAGS += -o $(BUILD_DIR)/emu
VERILATOR_FLAGS += -Mdir $(SOC_COMPILE_HOME)
VERILATOR_FLAGS += $(SOC_VSRC_INCLPATH) $(SOC_CXXFILES) $(SOC_VXXFILES)
SOC_SIM_TIME ?= 40
VERILATOR_STAMP := $(BUILD_DIR)/verilate.stamp
VERILATOR_DEPFILE := $(BUILD_DIR)/verilate.d
VERILATOR_EMU := $(BUILD_DIR)/emu
SOC_SIM_TIME ?= 40
VERILATOR_STAMP := $(BUILD_DIR)/verilate.stamp
VERILATOR_DEPFILE := $(BUILD_DIR)/verilate.d
VERILATOR_EMU := $(BUILD_DIR)/emu
VERILATOR_EXTRA_SOURCES := $(RTL_PATH)/dv/model/ESP_PSRAM64H.sv \
$(RTL_PATH)/dv/verilator/rtl/flash_read_binder.sv \
$(RTL_PATH)/dv/verilator/rtl/QSPIFlash.sv \
sta/opensta/opensta.mk
+11 -11
View File
@@ -1,15 +1,15 @@
OPENSTA ?= sta
OPENSTA_THREADS ?= $(JOBS)
OPENSTA_NETLIST ?= $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.v
OPENSTA_LIBERTY ?= $(ROOT_PATH)/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_typ_1p20V_25C.lib
OPENSTA_IO_LIB ?= $(ROOT_PATH)/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib
OPENSTA ?= sta
OPENSTA_THREADS ?= $(JOBS)
OPENSTA_NETLIST ?= $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.v
OPENSTA_LIBERTY ?= $(ROOT_PATH)/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_typ_1p20V_25C.lib
OPENSTA_IO_LIB ?= $(ROOT_PATH)/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib
OPENSTA_SRAM_LIBS ?= $(wildcard $(ROOT_PATH)/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/lib/*_typ_1p20V_25C.lib)
OPENSTA_SDC ?= $(ROOT_PATH)/sta/opensta/gen2.sdc
OPENSTA_REPORT ?= $(STA_BUILD_ROOT)/retrosoc_sta.log
OPENSTA_LOG ?= $(STA_BUILD_ROOT)/opensta.log
OPENSTA_METRICS ?= $(STA_BUILD_ROOT)/timing_metrics.rpt
OPENSTA_CONFIG ?= $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.config
OPENSTA_SDC ?= $(ROOT_PATH)/sta/opensta/gen2.sdc
OPENSTA_REPORT ?= $(STA_BUILD_ROOT)/retrosoc_sta.log
OPENSTA_LOG ?= $(STA_BUILD_ROOT)/opensta.log
OPENSTA_METRICS ?= $(STA_BUILD_ROOT)/timing_metrics.rpt
OPENSTA_CONFIG ?= $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.config
sta:
@mkdir -p $(STA_BUILD_ROOT)
@@ -19,7 +19,7 @@ sta:
@grep -qx 'PDK=$(PDK)' $(OPENSTA_CONFIG) || { \
echo "OpenSTA netlist configuration does not match PDK=$(PDK); rerun synthesis" >&2; \
exit 1; \
}
}
python3 $(ROOT_PATH)/scripts/run_flow.py --tool opensta --log $(OPENSTA_LOG) \
--result $(STA_BUILD_ROOT)/result-sta.json \
--env OPENSTA_NETLIST=$(OPENSTA_NETLIST) --env OPENSTA_LIBERTY=$(OPENSTA_LIBERTY) \
syn/yosys/synth_config.mk
+1 -1
View File
@@ -24,7 +24,7 @@ export YOSYS_KEEP_HIER_INST := "t:tc_clk*$$*" \
"t:ip_natv_wrapper*$$*" \
"t:ip_apb_wrapper*$$*" \
"t:apb_spi_master*$$*" \
"t:spi_flash*$$*" \
"t:spi_flash*$$*" \
"t:mem2apb*$$*" \
"t:apb4_archinfo*$$*" \
"t:apb4_rng*$$*" \
syn/yosys/yosys.mk
+7 -7
View File
@@ -27,15 +27,15 @@ YOSYS_RPT := $(YOSYS_BUILD)/rpt
include $(YOSYS_DIR)/synth_config.mk
TOP_DESIGN ?= retrosoc_asic
RTL_NAME ?= retrosoc_asic
SV_FLIST := $(GENERATED_FL_DIR)/yosys.fl
TOP_DESIGN ?= retrosoc_asic
RTL_NAME ?= retrosoc_asic
SV_FLIST := $(GENERATED_FL_DIR)/yosys.fl
NETLIST := $(YOSYS_OUT)/$(RTL_NAME)_yosys.v
NETLIST_DEBUG := $(YOSYS_OUT)/$(RTL_NAME)_yosys_debug.v
NETLIST := $(YOSYS_OUT)/$(RTL_NAME)_yosys.v
NETLIST_DEBUG := $(YOSYS_OUT)/$(RTL_NAME)_yosys_debug.v
NETLIST_CONFIG := $(YOSYS_OUT)/$(RTL_NAME)_yosys.config
YOSYS_DEPFILE := $(YOSYS_BUILD)/yosys.d
YOSYS_SCRIPTS := $(wildcard $(YOSYS_DIR)/script/*) $(YOSYS_DIR)/synth_config.mk $(YOSYS_DIR)/yosys.mk
YOSYS_DEPFILE := $(YOSYS_BUILD)/yosys.d
YOSYS_SCRIPTS := $(wildcard $(YOSYS_DIR)/script/*) $(YOSYS_DIR)/synth_config.mk $(YOSYS_DIR)/yosys.mk
-include $(YOSYS_DEPFILE)