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feat: adjust the extern chd cycles to max 3

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maksyuki committed 2025-02-18 10:43:26 +08:00
1 parent 4984f352b5
commit 76276088b4
3 files changed
+39 -22
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rtl/ip/cust/psram.v
+2 -2
View File
@@ -32,8 +32,8 @@ module psram_top (
input [ 3:0] cfg_wait_i,
output [ 3:0] cfg_wait_o,
input cfg_chd_wr_en_i,
input cfg_chd_i,
output cfg_chd_o,
input [ 1:0] cfg_chd_i,
output [ 1:0] cfg_chd_o,
input mem_valid_i,
output mem_ready_o,
input [23:0] mem_addr_i,
rtl/ip/cust/psram_core.v
+33 -16
View File
@@ -5,8 +5,8 @@ module psram_core (
input [ 3:0] cfg_wait_i,
output reg [ 3:0] cfg_wait_o,
input cfg_chd_wr_en_i,
input cfg_chd_i,
output reg cfg_chd_o,
input [ 1:0] cfg_chd_i,
output reg [ 1:0] cfg_chd_o,
output reg mem_ready_o,
input [23:0] mem_addr_i,
input [31:0] mem_wdata_i,
@@ -27,7 +27,8 @@ module psram_core (
output reg psram_sio3_o,
output psram_sio_oen_o
);
// sclk(max: 84MHz ~ 11.9ns)
// 11.9 * 40000 = 476us / 2 = 238us > 150us
`define BOOT_COUNTER 18'd40_000
localparam FSM_INIT = 0;
@@ -57,7 +58,7 @@ module psram_core (
reg [ 7:0] r_xfer_byte_data;
reg [ 3:0] r_ce_cnt;
reg [ 3:0] r_rd_wait_cnt;
reg r_cfg_chd;
reg [ 1:0] r_cfg_chd;
reg r_dev_rst;
reg r_wr_st;
reg r_rd_st;
@@ -72,7 +73,7 @@ module psram_core (
end
// extra cycle for tCHD(mmio)
always @(posedge clk_i or negedge rst_n_i) begin
if (~rst_n_i) cfg_chd_o <= 1'b0;
if (~rst_n_i) cfg_chd_o <= 2'd2;
else if (cfg_chd_wr_en_i) cfg_chd_o <= cfg_chd_i;
end
@@ -122,6 +123,7 @@ module psram_core (
r_xfer_byte_data <= 8'd0;
r_ce_cnt <= 4'd0;
r_rd_wait_cnt <= 4'd0;
r_cfg_chd <= 2'd0;
r_dev_rst <= 1'b1;
mem_ready_o <= 1'b0;
psram_sclk_o <= 1'b0;
@@ -136,41 +138,56 @@ module psram_core (
FSM_RSTEN: begin
r_xfer_ca <= {8'h66, 24'd0};
r_xfer_ca_bit_cnt <= 8'd8;
r_cfg_chd <= 2'd0;
psram_ce_o <= 1'b0;
r_ce_cnt <= cfg_wait_o;
r_fsm_state <= FSM_SEND;
r_fsm_state_tgt <= FSM_RSTEN2RST;
end
FSM_RSTEN2RST: begin // tCPH >= 50ns, when 192MHz, ce need keep high(>=10 cycles)
if (r_ce_cnt != cfg_wait_o) psram_ce_o <= 1'b1;
if (r_ce_cnt == 4'd0) r_fsm_state <= FSM_RST;
r_ce_cnt <= r_ce_cnt - 1'b1;
if (r_cfg_chd == cfg_chd_o) begin
if (r_ce_cnt != cfg_wait_o) psram_ce_o <= 1'b1;
if (r_ce_cnt == 4'd0) r_fsm_state <= FSM_RST;
r_ce_cnt <= r_ce_cnt - 1'b1;
end else begin
r_cfg_chd <= r_cfg_chd + 1'b1;
end
end
FSM_RST: begin
r_xfer_ca <= {8'h99, 24'd0};
r_xfer_ca_bit_cnt <= 8'd8;
r_cfg_chd <= 2'd0;
psram_ce_o <= 1'b0;
r_ce_cnt <= cfg_wait_o;
r_fsm_state <= FSM_SEND;
r_fsm_state_tgt <= FSM_RST2QE;
end
FSM_RST2QE: begin
if (r_ce_cnt != cfg_wait_o) psram_ce_o <= 1'b1;
if (r_ce_cnt == 4'd0) r_fsm_state <= FSM_QE;
r_ce_cnt <= r_ce_cnt - 1'b1;
if (r_cfg_chd == cfg_chd_o) begin
if (r_ce_cnt != cfg_wait_o) psram_ce_o <= 1'b1;
if (r_ce_cnt == 4'd0) r_fsm_state <= FSM_QE;
r_ce_cnt <= r_ce_cnt - 1'b1;
end else begin
r_cfg_chd <= r_cfg_chd + 1'b1;
end
end
FSM_QE: begin
r_xfer_ca <= {8'h35, 24'd0};
r_xfer_ca_bit_cnt <= 8'd8;
r_cfg_chd <= 2'd0;
psram_ce_o <= 1'b0;
r_ce_cnt <= cfg_wait_o;
r_fsm_state <= FSM_SEND;
r_fsm_state_tgt <= FSM_QE2IDLE;
end
FSM_QE2IDLE: begin
if (r_ce_cnt != cfg_wait_o) psram_ce_o <= 1'b1;
if (r_ce_cnt == 4'd0) r_fsm_state <= FSM_IDLE;
r_ce_cnt <= r_ce_cnt - 1'b1;
if (r_cfg_chd == cfg_chd_o) begin
if (r_ce_cnt != cfg_wait_o) psram_ce_o <= 1'b1;
if (r_ce_cnt == 4'd0) r_fsm_state <= FSM_IDLE;
r_ce_cnt <= r_ce_cnt - 1'b1;
end else begin
r_cfg_chd <= r_cfg_chd + 1'b1;
end
end
FSM_IDLE: begin
psram_sclk_o <= 1'b0;
@@ -184,7 +201,7 @@ module psram_core (
r_fsm_state <= FSM_SEND_QPI;
r_fsm_state_tgt <= FSM_WR_QPI;
r_xfer_data_bit_cnt <= 8'd0;
r_cfg_chd <= 1'b0;
r_cfg_chd <= 2'd0;
psram_ce_o <= 1'b0;
end else if (r_rd_st) begin
r_xfer_ca <= {8'hEB, mem_addr_i[23:0]};
@@ -193,7 +210,7 @@ module psram_core (
r_fsm_state_tgt <= FSM_RD_PRE_QPI;
r_rd_wait_cnt <= 4'd12; // wait 6 cycle afer cmd+addr accrondig to TRM
r_xfer_data_bit_cnt <= 8'd0;
r_cfg_chd <= 1'b0;
r_cfg_chd <= 2'd0;
psram_ce_o <= 1'b0;
end else begin
psram_ce_o <= 1'b1;
rtl/retrosoc.v
+4 -4
View File
@@ -365,8 +365,8 @@ module retrosoc #(
wire s_psram_cfg_chd_sel = s_iomem_valid && (s_iomem_addr == 32'h0300_0084);
reg [ 3:0] r_psram_cfg_wait_din;
wire [ 3:0] s_psram_cfg_wait_dout;
reg r_psram_cfg_chd_din;
wire s_psram_cfg_chd_dout;
reg [ 1:0] r_psram_cfg_chd_din;
wire [ 1:0] s_psram_cfg_chd_dout;
spimemio u_spimemio (
.clk (clk_i),
@@ -640,8 +640,8 @@ module retrosoc #(
if (s_iomem_wstrb[0]) r_psram_cfg_wait_din <= s_iomem_wdata[3:0];
end
8'h84: begin
r_iomem_rdata <= {31'd0, s_psram_cfg_chd_dout};
if (s_iomem_wstrb[0]) r_psram_cfg_chd_din <= s_iomem_wdata[0];
r_iomem_rdata <= {30'd0, s_psram_cfg_chd_dout};
if (s_iomem_wstrb[0]) r_psram_cfg_chd_din <= s_iomem_wdata[1:0];
end
endcase
end else if (s_iomem_valid && !r_iomem_ready && s_aximem_range) begin