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feat: add user ip design and wrapper components

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maksyuki committed 2025-08-11 12:15:55 +08:00
1 parent 7e513b2e2f
commit 76f8732787
4 files changed
+298 -11
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rtl/mini/top/ip_mdd_wrapper.sv
+95
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@@ -0,0 +1,95 @@
module ip_mdd_wrapper (
(* keep *) input logic clk_i,
(* keep *) input logic rst_n_i,
(* keep *) input logic [ 4:0] sel_i,
// gpio
(* keep *) output logic [15:0] gpio_out_o,
(* keep *) input logic [15:0] gpio_in_i,
(* keep *) output logic [15:0] gpio_oeb_o,
// apb if
(* keep *) input logic [31:0] slv_apb_paddr_i,
(* keep *) input logic [ 2:0] slv_apb_pprot_i,
(* keep *) input logic slv_apb_psel_i,
(* keep *) input logic slv_apb_penable_i,
(* keep *) input logic slv_apb_pwrite_i,
(* keep *) input logic [31:0] slv_apb_pwdata_i,
(* keep *) input logic [ 3:0] slv_apb_pstrb_i,
(* keep *) output logic slv_apb_pready_o,
(* keep *) output logic [31:0] slv_apb_prdata_o
);
logic [31:0] s_slv_0_apb_paddr;
logic [ 2:0] s_slv_0_apb_pprot;
logic s_slv_0_apb_psel;
logic s_slv_0_apb_penable;
logic s_slv_0_apb_pwrite;
logic [31:0] s_slv_0_apb_pwdata;
logic [ 3:0] s_slv_0_apb_pstrb;
logic s_slv_0_apb_pready;
logic [31:0] s_slv_0_apb_prdata;
logic [31:0] s_slv_user_apb_paddr;
logic [ 2:0] s_slv_user_apb_pprot;
logic s_slv_user_apb_psel;
logic s_slv_user_apb_penable;
logic s_slv_user_apb_pwrite;
logic [31:0] s_slv_user_apb_pwdata;
logic [ 3:0] s_slv_user_apb_pstrb;
logic s_slv_user_apb_pready;
logic [31:0] s_slv_user_apb_prdata;
// verilog_format: off
apb4_if u_archinfo_ip_mdd_apb4_if(clk_i, rst_n_i);
apb4_archinfo u_apb4_archinfo_ip_mdd(u_archinfo_ip_mdd_apb4_if);
assign u_archinfo_ip_mdd_apb4_if.paddr = s_slv_0_apb_paddr;
assign u_archinfo_ip_mdd_apb4_if.pprot = s_slv_0_apb_pprot;
assign u_archinfo_ip_mdd_apb4_if.psel = s_slv_0_apb_psel;
assign u_archinfo_ip_mdd_apb4_if.penable = s_slv_0_apb_penable;
assign u_archinfo_ip_mdd_apb4_if.pwrite = s_slv_0_apb_pwrite;
assign u_archinfo_ip_mdd_apb4_if.pwdata = s_slv_0_apb_pwdata;
assign u_archinfo_ip_mdd_apb4_if.pstrb = s_slv_0_apb_pstrb;
assign s_slv_0_apb_pready = u_archinfo_ip_mdd_apb4_if.pready;
assign s_slv_0_apb_pslverr = u_archinfo_ip_mdd_apb4_if.pslverr;
assign s_slv_0_apb_prdata = u_archinfo_ip_mdd_apb4_if.prdata;
// verilog_format: on
assign slv_apb_pready_o = sel_i == '0 ? s_slv_0_apb_pready : s_slv_user_apb_pready;
assign slv_apb_prdata_o = sel_i == '0 ? s_slv_0_apb_prdata : s_slv_user_apb_prdata;
assign s_slv_0_apb_paddr = sel_i == '0 ? slv_apb_paddr_i : '0;
assign s_slv_0_apb_pprot = sel_i == '0 ? slv_apb_pprot_i : '0;
assign s_slv_0_apb_psel = sel_i == '0 ? slv_apb_psel_i : '0;
assign s_slv_0_apb_penable = sel_i == '0 ? slv_apb_penable_i : '0;
assign s_slv_0_apb_pwrite = sel_i == '0 ? slv_apb_pwrite_i : '0;
assign s_slv_0_apb_pwdata = sel_i == '0 ? slv_apb_pwdata_i : '0;
assign s_slv_0_apb_pstrb = sel_i == '0 ? slv_apb_pstrb_i : '0;
assign s_slv_user_apb_paddr = sel_i != '0 ? slv_apb_paddr_i : '0;
assign s_slv_user_apb_pprot = sel_i != '0 ? slv_apb_pprot_i : '0;
assign s_slv_user_apb_psel = sel_i != '0 ? slv_apb_psel_i : '0;
assign s_slv_user_apb_penable = sel_i != '0 ? slv_apb_penable_i : '0;
assign s_slv_user_apb_pwrite = sel_i != '0 ? slv_apb_pwrite_i : '0;
assign s_slv_user_apb_pwdata = sel_i != '0 ? slv_apb_pwdata_i : '0;
assign s_slv_user_apb_pstrb = sel_i != '0 ? slv_apb_pstrb_i : '0;
user_ip_wrapper u_user_ip_wrapper (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.sel_i (sel_i),
.gpio_out_o (gpio_out_o),
.gpio_in_i (gpio_in_i),
.gpio_oeb_o (gpio_oeb_o),
.slv_apb_paddr_i (s_slv_user_apb_paddr),
.slv_apb_pprot_i (s_slv_user_apb_pprot),
.slv_apb_psel_i (s_slv_user_apb_psel),
.slv_apb_penable_i(s_slv_user_apb_penable),
.slv_apb_pwrite_i (s_slv_user_apb_pwrite),
.slv_apb_pwdata_i (s_slv_user_apb_pwdata),
.slv_apb_pstrb_i (s_slv_user_apb_pstrb),
.slv_apb_pready_o (s_slv_user_apb_pready),
.slv_apb_prdata_o (s_slv_user_apb_prdata)
);
endmodule
rtl/mini/top/retrosoc.sv
+25 -11
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@@ -158,18 +158,18 @@ module retrosoc (
// 1 x SPFS(HP)
// 2 x I2C
core_wrapper u_core_wrapper (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.clk_i (clk_i),
.rst_n_i (rst_n_i),
`ifdef CORE_MDD
.core_mdd_sel_i (core_mdd_sel_i),
.core_mdd_sel_i(core_mdd_sel_i),
`endif
.core_valid_o(s_core_valid),
.core_addr_o (s_core_addr),
.core_wdata_o(s_core_wdata),
.core_wstrb_o(s_core_wstrb),
.core_rdata_i(s_core_rdata),
.core_ready_i(s_core_ready),
.irq_i (s_irq)
.core_valid_o (s_core_valid),
.core_addr_o (s_core_addr),
.core_wdata_o (s_core_wdata),
.core_wstrb_o (s_core_wstrb),
.core_rdata_i (s_core_rdata),
.core_ready_i (s_core_ready),
.irq_i (s_irq)
);
bus u_bus (
@@ -282,7 +282,21 @@ module retrosoc (
`ifdef IP_MDD
ip_mdd_wrapper u_ip_mdd_wrapper (
.
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.sel_i (ip_mdd_sel_i),
.gpio_out_o (ip_mdd_gpio_out_o),
.gpio_in_i (ip_mdd_gpio_in_i),
.gpio_oeb_o (ip_mdd_gpio_oeb_o),
.slv_apb_paddr_i (s_ip_mdd_apb_paddr),
.slv_apb_pprot_i (s_ip_mdd_apb_pprot),
.slv_apb_psel_i (s_ip_mdd_apb_psel),
.slv_apb_penable_i(s_ip_mdd_apb_penable),
.slv_apb_pwrite_i (s_ip_mdd_apb_pwrite),
.slv_apb_pwdata_i (s_ip_mdd_apb_pwdata),
.slv_apb_pstrb_i (s_ip_mdd_apb_pstrb),
.slv_apb_pready_o (s_ip_mdd_apb_pready),
.slv_apb_prdata_o (s_ip_mdd_apb_prdata)
);
`endif
rtl/mini/top/user_ip_design.sv
+23
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@@ -0,0 +1,23 @@
module user_ip_design (
input logic clk_i,
input logic rst_n_i,
output logic [15:0] gpio_out_o,
input logic [15:0] gpio_in_i,
output logic [15:0] gpio_oeb_o,
input logic [31:0] apb_paddr_i,
input logic [ 2:0] apb_pprot_i,
input logic apb_psel_i,
input logic apb_penable_i,
input logic apb_pwrite_i,
input logic [31:0] apb_pwdata_i,
input logic [ 3:0] apb_pstrb_i,
output logic apb_pready_o,
output logic [31:0] apb_prdata_o
);
assign gpio_out_o = '0;
assign gpio_oeb_o = '0;
assign apb_pready_o = '0;
assign apb_prdata_o = '0;
endmodule
rtl/mini/top/user_ip_wrapper.sv
+155
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@@ -0,0 +1,155 @@
module user_ip_wrapper (
input logic clk_i,
input logic rst_n_i,
input logic [ 4:0] sel_i,
output logic [15:0] gpio_out_o,
input logic [15:0] gpio_in_i,
output logic [15:0] gpio_oeb_o,
input logic [31:0] slv_apb_paddr_i,
input logic [ 2:0] slv_apb_pprot_i,
input logic slv_apb_psel_i,
input logic slv_apb_penable_i,
input logic slv_apb_pwrite_i,
input logic [31:0] slv_apb_pwdata_i,
input logic [ 3:0] slv_apb_pstrb_i,
output logic slv_apb_pready_o,
output logic [31:0] slv_apb_prdata_o
);
logic [15:0] s_user_1_gpio_out;
logic [15:0] s_user_1_gpio_in;
logic [15:0] s_user_1_gpio_oeb;
logic [31:0] s_user_1_apb_paddr;
logic [ 2:0] s_user_1_apb_pprot;
logic s_user_1_apb_psel;
logic s_user_1_apb_penable;
logic s_user_1_apb_pwrite;
logic [31:0] s_user_1_apb_pwdata;
logic [ 3:0] s_user_1_apb_pstrb;
logic s_user_1_apb_pready;
logic [31:0] s_user_1_apb_prdata;
logic [15:0] s_user_2_gpio_out;
logic [15:0] s_user_2_gpio_in;
logic [15:0] s_user_2_gpio_oeb;
logic [31:0] s_user_2_apb_paddr;
logic [ 2:0] s_user_2_apb_pprot;
logic s_user_2_apb_psel;
logic s_user_2_apb_penable;
logic s_user_2_apb_pwrite;
logic [31:0] s_user_2_apb_pwdata;
logic [ 3:0] s_user_2_apb_pstrb;
logic s_user_2_apb_pready;
logic [31:0] s_user_2_apb_prdata;
always_comb begin
gpio_out_o = '0;
gpio_oeb_o = '1;
slv_apb_pready_o = '0;
slv_apb_prdata_o = '0;
s_user_1_gpio_in = '0;
s_user_1_apb_paddr = '0;
s_user_1_apb_pprot = '0;
s_user_1_apb_psel = '0;
s_user_1_apb_penable = '0;
s_user_1_apb_pwrite = '0;
s_user_1_apb_pwdata = '0;
s_user_1_apb_pstrb = '0;
s_user_2_gpio_in = '0;
s_user_2_apb_paddr = '0;
s_user_2_apb_pprot = '0;
s_user_2_apb_psel = '0;
s_user_2_apb_penable = '0;
s_user_2_apb_pwrite = '0;
s_user_2_apb_pwdata = '0;
s_user_2_apb_pstrb = '0;
unique case (sel_i)
5'd1: begin
gpio_out_o = s_user_1_gpio_out;
gpio_oeb_o = s_user_1_gpio_oeb;
slv_apb_pready_o = s_user_1_apb_pready;
slv_apb_prdata_o = s_user_1_apb_prdata;
s_user_1_gpio_in = gpio_in_i;
s_user_1_apb_paddr = slv_apb_paddr_i;
s_user_1_apb_pprot = slv_apb_pprot_i;
s_user_1_apb_psel = slv_apb_psel_i;
s_user_1_apb_penable = slv_apb_penable_i;
s_user_1_apb_pwrite = slv_apb_pwrite_i;
s_user_1_apb_pwdata = slv_apb_pwdata_i;
s_user_1_apb_pstrb = slv_apb_pstrb_i;
end
5'd2: begin
gpio_out_o = s_user_2_gpio_out;
gpio_oeb_o = s_user_2_gpio_oeb;
slv_apb_pready_o = s_user_2_apb_pready;
slv_apb_prdata_o = s_user_2_apb_prdata;
s_user_2_gpio_in = gpio_in_i;
s_user_2_apb_paddr = slv_apb_paddr_i;
s_user_2_apb_pprot = slv_apb_pprot_i;
s_user_2_apb_psel = slv_apb_psel_i;
s_user_2_apb_penable = slv_apb_penable_i;
s_user_2_apb_pwrite = slv_apb_pwrite_i;
s_user_2_apb_pwdata = slv_apb_pwdata_i;
s_user_2_apb_pstrb = slv_apb_pstrb_i;
end
default: begin
gpio_out_o = '0;
gpio_oeb_o = '1;
slv_apb_pready_o = '0;
slv_apb_prdata_o = '0;
s_user_1_gpio_in = '0;
s_user_1_apb_paddr = '0;
s_user_1_apb_pprot = '0;
s_user_1_apb_psel = '0;
s_user_1_apb_penable = '0;
s_user_1_apb_pwrite = '0;
s_user_1_apb_pwdata = '0;
s_user_1_apb_pstrb = '0;
s_user_2_gpio_in = '0;
s_user_2_apb_paddr = '0;
s_user_2_apb_pprot = '0;
s_user_2_apb_psel = '0;
s_user_2_apb_penable = '0;
s_user_2_apb_pwrite = '0;
s_user_2_apb_pwdata = '0;
s_user_2_apb_pstrb = '0;
end
endcase
end
user_ip_design_1 u_user_ip_design_1 (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.gpio_out_o (s_user_1_gpio_out),
.gpio_in_i (s_user_1_gpio_in),
.gpio_oeb_o (s_user_1_gpio_oeb),
.apb_paddr_i (s_user_1_apb_paddr),
.apb_pprot_i (s_user_1_apb_pprot),
.apb_psel_i (s_user_1_apb_psel),
.apb_penable_i(s_user_1_apb_penable),
.apb_pwrite_i (s_user_1_apb_pwrite),
.apb_pwdata_i (s_user_1_apb_pwdata),
.apb_pstrb_i (s_user_1_apb_pstrb),
.apb_pready_o (s_user_1_apb_pready),
.apb_prdata_o (s_user_1_apb_prdata)
);
user_ip_design_2 u_user_ip_design_2 (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.gpio_out_o (s_user_2_gpio_out),
.gpio_in_i (s_user_2_gpio_in),
.gpio_oeb_o (s_user_2_gpio_oeb),
.apb_paddr_i (s_user_2_apb_paddr),
.apb_pprot_i (s_user_2_apb_pprot),
.apb_psel_i (s_user_2_apb_psel),
.apb_penable_i(s_user_2_apb_penable),
.apb_pwrite_i (s_user_2_apb_pwrite),
.apb_pwdata_i (s_user_2_apb_pwdata),
.apb_pstrb_i (s_user_2_apb_pstrb),
.apb_pready_o (s_user_2_apb_pready),
.apb_prdata_o (s_user_2_apb_prdata)
);
endmodule