Merge pull request #9 from retroSoC/dev

fix: add ICS55 support for yosys

rtl/tech/tc_pll.sv

@@ -16,6 +16,9 @@ module tc_pll (
 `elsif PDK_IHP130
   assign pll_lock_o = 1'b1;
   assign pll_clk_o  = fref_i;
+`elsif PDK_ICS55
+  assign pll_lock_o = 1'b1;
+  assign pll_clk_o  = fref_i;
 `elsif PDK_S110
 
 `ifndef HAVE_PLL

rtl/tiny/filelist/ip.fl

@@ -22,6 +22,7 @@
 ../../clusterip/i2c/rtl/i2c_master_bit_ctrl.sv
 ../../clusterip/i2c/rtl/i2c_master_byte_ctrl.sv
 ../../clusterip/i2c/rtl/apb4_i2c.sv
+../../clusterip/spi/rtl/spi_if.sv
 ../../clusterip/spi/rtl/apb4_spi.sv
 ../../clusterip/spi/rtl/spi_clkgen.sv
 ../../clusterip/spi/rtl/spi_apb_if.sv
@@ -41,4 +42,4 @@
 ../../ip/3rd_party/spfs/spi_clgen.v
 ../../ip/3rd_party/spfs/spi_shift.v
 ../../ip/3rd_party/spfs/spi_top.v
-../../ip/3rd_party/spfs/spi_flash.v
+../../ip/3rd_party/spfs/spi_flash.v

syn/yosys/yosys.mk

@@ -29,7 +29,7 @@ include $(YOSYS_DIR)/synth_config.mk
 
 TOP_DESIGN    ?= retrosoc_asic
 RTL_NAME      ?= retrosoc_asic
-SV_FLIST      := $(YOSYS_DIR)/../../rtl/$(shell echo $(SOC) | tr A-Z a-z )/filelist/yosys_syn.fl
+SV_FLIST      := $(YOSYS_DIR)/../../rtl/$(shell echo $(SOC) | tr A-Z a-z )/filelist/yosys.fl
 
 $(info SV_FLIST: $(SV_FLIST))