refactor: refactor RTL style checker and update test cases

- Enhanced the RTL style checker script to include new diagnostic rules for function declarations, primary design units, and synthesis exclusions.
- Added functions to handle audit issues, ensuring that the audit records match the current inventory of RTL files.
- Updated test cases to reflect changes in RTL file names and paths, ensuring consistency with the new naming conventions.
- Introduced additional tests for style violations, including mismatched primary design units and synthesizable initial blocks.
- Adjusted file paths in various test files to align with the new RTL structure and naming conventions.

tests/test_sdram.py

@@ -43,7 +43,7 @@ def test_sdram_controller_preserves_full_and_masked_writes(tmp_path: Path) -> No
                 str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
                 str(ROOT / "rtl/mini/top/axi42ribp_burst.sv"),
                 str(ROOT / "rtl/mini/top/ribp_arbiter2.sv"),
-                str(ROOT / "rtl/ip/memory/sdram.sv"),
+                str(ROOT / "rtl/ip/memory/axi4_sdram.sv"),
                 str(ROOT / "rtl/ip/memory/sdram_clkgen.sv"),
                 str(ROOT / "rtl/ip/memory/sdram_reg.sv"),
                 str(ROOT / "rtl/ip/memory/sdram_core.sv"),
@@ -109,7 +109,7 @@ def test_sdram_controller_preserves_data_with_micron_timing_model(tmp_path: Path
                 str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
                 str(ROOT / "rtl/mini/top/axi42ribp_burst.sv"),
                 str(ROOT / "rtl/mini/top/ribp_arbiter2.sv"),
-                str(ROOT / "rtl/ip/memory/sdram.sv"),
+                str(ROOT / "rtl/ip/memory/axi4_sdram.sv"),
                 str(ROOT / "rtl/ip/memory/sdram_clkgen.sv"),
                 str(ROOT / "rtl/ip/memory/sdram_reg.sv"),
                 str(ROOT / "rtl/ip/memory/sdram_core.sv"),