chore: mv the rtl to the right place

This commit is contained in:
maksyuki committed 2025-03-18 15:14:00 +08:00
1 parent 54ae4cf833
commit 9347a5a165
13 files changed
+12 -9

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+1
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@@ -0,0 +1 @@
../core/picorv32.v
+5 -3
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@@ -1,8 +1,7 @@
../ip/onchip_ram.v
../ip/simpleuart.v
../ip/counter_timer.v
../ip/rs232.v
../ip/rcu.v
../ip/cust/register.v
../ip/cust/lfsr.v
../ip/cust/fifo.v
@@ -10,6 +9,7 @@
../ip/cust/clk_int_div.v
../ip/cust/edge_det.v
../ip/cust/rst_sync.v
../ip/cust/archinfo.v
../ip/cust/rng.v
../ip/cust/uart.v
@@ -29,7 +29,9 @@
../ip/cust/apb_spi_master/spi_master_rx.v
../ip/cust/apb_spi_master/spi_master_tx.v
../ip/cust/apb_spi_master/apb_spi_master.v
../ip/mem2apb.v
../ip/natv_ip_wrapper.v
../ip/apb_ip_wrapper.v
../ip/bus.v
../ip/bus.v
../ip/rcu.v
-3
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@@ -1,3 +0,0 @@
../retrosoc_asic.v
../retrosoc.v
../picorv32.v
+2 -1
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@@ -1,4 +1,5 @@
../ip/cust/spfs_model/N25Qxxx.v
../ip/kdb_model.v
../ip/psram_model.v
../retrosoc_tb.v
../ip/rs232.v
../tb/retrosoc_tb.v
+2
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@@ -0,0 +1,2 @@
../top/retrosoc_asic.v
../top/retrosoc.v
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@@ -34,7 +34,6 @@ module retrosoc #(
) (
input clk_i,
input rst_n_i,
//sram if including clk_i and rst_n_i above,
output [14:0] ram_addr_o,
output [31:0] ram_wdata_o,
output [ 3:0] ram_wstrb_o,
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+2 -1
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@@ -14,7 +14,8 @@ RTL_INC := +incdir+../ip \
+incdir+../ip/cust/spfs_model
RTL_FLIST := -f ../filelist/soc.fl \
RTL_FLIST := -f ../filelist/top.fl \
-f ../filelist/core.fl \
-f ../filelist/ip.fl \
-f ../filelist/tech.fl \
-f ../filelist/pdk_s110.fl