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https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
chore: mv the rtl to the right place
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13 files changed
+12
-9
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@@ -0,0 +1 @@
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../core/picorv32.v
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@@ -1,8 +1,7 @@
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../ip/onchip_ram.v
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../ip/simpleuart.v
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../ip/counter_timer.v
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../ip/rs232.v
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../ip/rcu.v
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../ip/cust/register.v
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../ip/cust/lfsr.v
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../ip/cust/fifo.v
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@@ -10,6 +9,7 @@
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../ip/cust/clk_int_div.v
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../ip/cust/edge_det.v
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../ip/cust/rst_sync.v
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../ip/cust/archinfo.v
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../ip/cust/rng.v
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../ip/cust/uart.v
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@@ -29,7 +29,9 @@
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../ip/cust/apb_spi_master/spi_master_rx.v
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../ip/cust/apb_spi_master/spi_master_tx.v
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../ip/cust/apb_spi_master/apb_spi_master.v
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../ip/mem2apb.v
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../ip/natv_ip_wrapper.v
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../ip/apb_ip_wrapper.v
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../ip/bus.v
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../ip/bus.v
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../ip/rcu.v
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@@ -1,3 +0,0 @@
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../retrosoc_asic.v
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../retrosoc.v
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../picorv32.v
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@@ -1,4 +1,5 @@
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../ip/cust/spfs_model/N25Qxxx.v
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../ip/kdb_model.v
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../ip/psram_model.v
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../retrosoc_tb.v
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../ip/rs232.v
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../tb/retrosoc_tb.v
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@@ -0,0 +1,2 @@
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../top/retrosoc_asic.v
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../top/retrosoc.v
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File renamed without changes.
File renamed without changes.
@@ -34,7 +34,6 @@ module retrosoc #(
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) (
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input clk_i,
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input rst_n_i,
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//sram if including clk_i and rst_n_i above,
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output [14:0] ram_addr_o,
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output [31:0] ram_wdata_o,
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output [ 3:0] ram_wstrb_o,
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File renamed without changes.
File renamed without changes.
File renamed without changes.
+2
-1
@@ -14,7 +14,8 @@ RTL_INC := +incdir+../ip \
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+incdir+../ip/cust/spfs_model
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RTL_FLIST := -f ../filelist/soc.fl \
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RTL_FLIST := -f ../filelist/top.fl \
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-f ../filelist/core.fl \
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-f ../filelist/ip.fl \
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-f ../filelist/tech.fl \
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-f ../filelist/pdk_s110.fl
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