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feat: add rtl behv model to the tech modules

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maksyuki committed 2025-02-04 17:12:22 +08:00
1 parent 49969621b1
commit a5522b1bc3
3 files changed
+42 -53
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tech/tc_clk.v
+19 -26
View File
@@ -5,30 +5,37 @@
//
// -Thomas Benz <tbenz@iis.ee.ethz.ch>
// -Tobias Senti <tsenti@student.ethz.ch>
module tc_clk_inverter (
module tc_clk_inv (
input clk_i,
output clk_o
);
`ifdef RTL_BEHAV
assign clk_o = ~clk_i;
`else
(* keep *) (* dont_touch = "true" *)
sg13g2_inv_1 i_inv (
.A(clk_i),
.Y(clk_o)
);
`endif
endmodule
module tc_clk_buffer (
module tc_clk_buf (
input clk_i,
output clk_o
);
`ifdef RTL_BEHAV
assign clk_o = clk_i;
`else
(* keep *) (* dont_touch = "true" *)
sg13g2_buf_1 i_buf (
.A(clk_i),
.X(clk_o)
);
`endif
endmodule
module tc_clk_mux2 (
@@ -37,6 +44,10 @@ module tc_clk_mux2 (
input clk_sel_i,
output clk_o
);
`ifdef RTL_BEHAV
assign clk_o = clk_sel_i ? clk1_i : clk0_i;
`else
(* keep *) (* dont_touch = "true" *)
sg13g2_mux2_1 i_mux (
.A0(clk0_i),
@@ -44,6 +55,7 @@ module tc_clk_mux2 (
.S (clk_sel_i),
.X (clk_o)
);
`endif
endmodule
module tc_clk_xor2 (
@@ -52,33 +64,14 @@ module tc_clk_xor2 (
output clk_o
);
`ifdef RTL_BEHAV
assign clk_o = clk0_i ^ clk1_i;
`else
(* keep *) (* dont_touch = "true" *)
sg13g2_xor2_1 i_mux (
.A(clk0_i),
.B(clk1_i),
.X(clk_o)
);
`endif
endmodule
// module tc_clk_gating #(
// parameter [0:0] IS_FUNCTIONAL = 1'b1
// ) (
// input clk_i,
// input en_i,
// input test_en_i,
// output clk_o
// );
// // if (IS_FUNCTIONAL || `ifdef USE_CLKGATE 1 `else 0 `endif) begin
// // (* keep *)(* dont_touch = "true" *)
// // sg13g2_slgcp_1 i_clkgate (
// // .GATE ( en_i ),
// // .SCE ( test_en_i ),
// // .CLK ( clk_i ),
// // .GCLK ( clk_o )
// // );
// // end else begin
// assign clk_o = clk_i;
// // end
// endmodule
tech/tc_io.v
+5
View File
@@ -16,6 +16,10 @@ module tc_io_tri_pad (
output p2c
);
`ifdef RTL_BEHAV
assign pad = c2p_en ? c2p : 1'bz;
assign p2c = pad;
`else
(* keep *) (* dont_touch = "true" *)
sg13g2_IOPadInOut4mA u_sg13g2_IOPadInOut4mA (
.pad (pad),
@@ -23,5 +27,6 @@ module tc_io_tri_pad (
.c2p_en(c2p_en),
.p2c (p2c)
);
`endif
endmodule
tech/tc_sram.v
+18 -27
View File
@@ -8,6 +8,22 @@ module tc_sram_1024x32 (
output [31:0] data_o
);
`ifdef RTL_BEHAV
reg [31:0] mem[0:1023];
always @(posedge clk_i) begin
if (cs_i) begin
if (!wren_i) begin
data_o <= mem[addr_i];
end else begin
if (mask_i[0]) mem[addr_i][7:0] <= data_i[7:0];
if (mask_i[1]) mem[addr_i][15:8] <= data_i[15:8];
if (mask_i[2]) mem[addr_i][23:16] <= data_i[23:16];
if (mask_i[3]) mem[addr_i][31:24] <= data_i[31:24];
data_o <= 32'bx;
end
end
end
`else
wire [63:0] s_rd_data_mem;
assign data_o = s_rd_data_mem[31:0];
RM_IHPSG13_1P_1024x64_c2_bm_bist u_mem (
@@ -29,30 +45,5 @@ module tc_sram_1024x32 (
.A_BIST_DIN (64'd0),
.A_BIST_BM (64'd0)
);
endmodule
// 4KB
// module SPRAM1024X16 (
// input clk_i,
// input cs_i,
// input [ 9:0] addr_i,
// input [15:0] data_i,
// input [ 3:0] mask_i,
// input wren_i,
// output reg [15:0] data_o
// );
// reg [15:0] mem[0:1023];
// always @(posedge clk_i) begin
// if (cs_i) begin
// if (!wren_i) begin
// data_o <= mem[addr_i];
// end else begin
// if (mask_i[0]) mem[addr_i][7:0] <= data_i[7:0];
// if (mask_i[1]) mem[addr_i][15:8] <= data_i[15:8];
// if (mask_i[2]) mem[addr_i][23:16] <= data_i[23:16];
// if (mask_i[3]) mem[addr_i][31:24] <= data_i[31:24];
// data_o <= 32'bx;
// end
// end
// end
// endmodule
`endif
endmodule