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Merge pull request #177 from retroSoC/dev

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Yuchi Miao authored and GitHub committed 2026-06-25 11:12:56 +08:00
2 parents 76651fdddb f652cf81b8
commit ac9d7b21e7
6 files changed
+5 -5
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rtl/ip/native/DVP_CAMERA.sv → rtl/ip/tb/DVP_CAMERA.sv
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File renamed without changes.
rtl/ip/native/ESP_PSRAM64H.sv → rtl/ip/tb/ESP_PSRAM64H.sv
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File renamed without changes.
rtl/mini/filelist/tb.fl
+2 -2
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@@ -3,7 +3,7 @@
/clusterip/uart/model/rs232.sv
/clusterip/i2s/model/mic.sv
/clusterip/spi/model/w25q128jvxim.sv
/ip/native/ESP_PSRAM64H.sv
/ip/native/DVP_CAMERA.sv
/ip/tb/ESP_PSRAM64H.sv
/ip/tb/DVP_CAMERA.sv
/ip/3rd-party/model/sdram/sdr.v
/tb/retrosoc_tb.sv
rtl/mini/lint.msg
+1 -1
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@@ -1,5 +1,5 @@
{
+lint=all;
-file=/mpw/core/username3/Hazard3/arith/hazard3_muldiv_seq.v,/mpw/core/username3/Hazard3/hazard3_frontend.v,/mpw/core/username3/Hazard3/arith/hazard3_onehot_encode.v,/mpw/core/username3/Hazard3/hazard3_instr_decompress.v,/pdk/icsprout55-pdk/IP/IO/ICsprout_55LLULP1233_IO_251013/verilog/icsIOA_N55_3P3.v,/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/verilog/ics55_LLSC_H7CR.v,/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/verilog/ics55_LLSC_H7CL.v,/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CH/verilog/ics55_LLSC_H7CH.v,/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v,/clusterip/i2c/model/at24cxxx.sv,/clusterip/spi/model/w25q128jvxim.sv,/core/picorv32_ver.v,/core/picorv32.v,/clusterip/common/rtl/cdc/cdc_2phase.sv,/clusterip/common/rtl/utils/register.sv,/clusterip/uart/model/rs232.sv,/tb/retrosoc_tb.sv,/clusterip/i2s/model/mic.sv,/ip/native/ESP_PSRAM64H.sv,/ip/3rd-party/model/sdram/sdr.v;
-file=/mpw/core/username3/Hazard3/arith/hazard3_muldiv_seq.v,/mpw/core/username3/Hazard3/hazard3_frontend.v,/mpw/core/username3/Hazard3/arith/hazard3_onehot_encode.v,/mpw/core/username3/Hazard3/hazard3_instr_decompress.v,/pdk/icsprout55-pdk/IP/IO/ICsprout_55LLULP1233_IO_251013/verilog/icsIOA_N55_3P3.v,/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/verilog/ics55_LLSC_H7CR.v,/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/verilog/ics55_LLSC_H7CL.v,/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CH/verilog/ics55_LLSC_H7CH.v,/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v,/clusterip/i2c/model/at24cxxx.sv,/clusterip/spi/model/w25q128jvxim.sv,/core/picorv32_ver.v,/core/picorv32.v,/clusterip/common/rtl/cdc/cdc_2phase.sv,/clusterip/common/rtl/utils/register.sv,/clusterip/uart/model/rs232.sv,/tb/retrosoc_tb.sv,/clusterip/i2s/model/mic.sv,/ip/tb/ESP_PSRAM64H.sv,/ip/3rd-party/model/sdram/sdr.v;
}
{ +warn=all; }
rtl/mini/mk/verilator.mk
+1 -1
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@@ -12,7 +12,7 @@ SOC_COMPILE_HOME := $(BUILD_DIR)/emu_compile
SOC_VXXFILES := $(RTL_FLIST)
SOC_VXXFILES += $(RTL_PATH)/../ip/native/ESP_PSRAM64H.sv
SOC_VXXFILES += $(RTL_PATH)/../ip/tb/ESP_PSRAM64H.sv
SOC_VXXFILES += $(RTL_PATH)/vsrc/flash_read_binder.sv
SOC_VXXFILES += $(RTL_PATH)/vsrc/QSPIFlash.sv
SOC_VXXFILES += $(RTL_PATH)/vsrc/retrosoc_top.sv
rtl/mini/top/onchip_ram.sv
+1 -1
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@@ -63,7 +63,7 @@ module onchip_ram (
.addr_i(ram.addr[9:0]),
.data_i(ram.wdata),
.mask_i(ram.wstrb),
.wren_i(|ram.wstrb_i),
.wren_i(|ram.wstrb),
.data_o(s_rdata[i])
);
end