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Merge pull request #144 from retroSoC/dev

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Dev
This commit is contained in:
Yuchi Miao authored and GitHub committed 2026-01-04 22:16:27 +08:00
2 parents ccddec666d 150401c53d
commit af1a7975a2
4 files changed
+8 -52
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app/asm/hello.s
+2 -2
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@@ -18,7 +18,7 @@ APP_INIT:
li t2, 6
APP_LOOP:
la s0, msg_luck
li a0, 72
li a0, 67
INTER_LOOP:
addi s0, s0, 1
jal ra, PUTC
@@ -139,5 +139,5 @@ PUTC:
.section .data
msg_hello: .string "Hello retroSoC!\n"
msg_luck: .string "Have a good luck!\n"
msg_luck: .string "Clock in luck, reset doubts!\n"
msg_succ: .string "Mem wr/rd test succ!\n"
rtl/ip/native/ahbl2nmi.sv
+4 -25
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@@ -41,28 +41,7 @@ module ahbl2nmi (
// NOTE: need to gurantee `ahbl.hready` and `ahbl.hrdata` sampled in same cycle
assign ahbl.hready = (s_fsm_q == STATE_IDLE) || nmi.ready;
assign ahbl.hresp = AHBL_RESP_OKAY;
always_comb begin
ahbl.hrdata = '0;
unique case (s_hsize_q)
AHBL_SIZE_BYTE: begin
unique case (s_haddr_q[1:0])
2'b00: ahbl.hrdata = {24'b0, nmi.rdata[7:0]};
2'b01: ahbl.hrdata = {24'b0, nmi.rdata[15:8]};
2'b10: ahbl.hrdata = {24'b0, nmi.rdata[23:16]};
2'b11: ahbl.hrdata = {24'b0, nmi.rdata[31:24]};
default: ahbl.hrdata = {24'b0, nmi.rdata[7:0]};
endcase
end
AHBL_SIZE_HWRD: begin
unique case (s_haddr_q[1])
1'b0: ahbl.hrdata = {16'b0, nmi.rdata[15:0]};
1'b1: ahbl.hrdata = {16'b0, nmi.rdata[31:16]};
endcase
end
AHBL_SIZE_WORD: ahbl.hrdata = nmi.rdata;
default: ahbl.hrdata = nmi.rdata;
endcase
end
assign ahbl.hrdata = nmi.rdata;
// nmi if
assign nmi.valid = s_fsm_q != STATE_IDLE;
@@ -130,7 +109,7 @@ module ahbl2nmi (
unique case (s_fsm_q)
STATE_IDLE: begin
// just for no-burst ahbl
if (ahbl.htrans == AHBL_TRANS_NSEQ && ahbl.hburst == '0) begin
if (ahbl.htrans == AHBL_TRANS_NSEQ && ahbl.hready) begin
s_fsm_d = STATE_DATA;
s_haddr_d = ahbl.haddr;
s_hwrite_d = ahbl.hwrite;
@@ -140,7 +119,7 @@ module ahbl2nmi (
STATE_DATA: begin
if (~nmi.ready) s_fsm_d = STATE_WAIT;
// nmi.ready == 1'b1
else if (ahbl.htrans == AHBL_TRANS_NSEQ && ahbl.hburst == '0) begin
else if (ahbl.htrans == AHBL_TRANS_NSEQ) begin
s_fsm_d = STATE_DATA;
s_haddr_d = ahbl.haddr;
s_hwrite_d = ahbl.hwrite;
@@ -149,7 +128,7 @@ module ahbl2nmi (
end
STATE_WAIT: begin
if (nmi.ready) begin
if (ahbl.htrans == AHBL_TRANS_NSEQ && ahbl.hburst == '0) begin
if (ahbl.htrans == AHBL_TRANS_NSEQ) begin
s_fsm_d = STATE_DATA;
s_haddr_d = ahbl.haddr;
s_hwrite_d = ahbl.hwrite;
rtl/mini/top/retrosoc.sv
+2 -2
View File
@@ -91,8 +91,8 @@ module retrosoc (
assign qspi.irq_o = '0;
// interrupt
assign s_irq[0] = u_clint_if.tmr_irq_o;
assign s_irq[1] = u_clint_if.sfr_irq_o;
assign s_irq[0] = u_clint_if.sfr_irq_o;
assign s_irq[1] = u_clint_if.tmr_irq_o;
assign s_irq[2] = extn_irq_i;
assign s_irq[5:3] = s_natv_irq;
assign s_irq[14:6] = s_apb_irq;
rtl/mini/top/user_core_top.sv
-23
View File
@@ -28,14 +28,12 @@ module user_core_top (
nmi_if u_user_4_nmi_if ();
nmi_if u_user_5_nmi_if ();
nmi_if u_user_6_nmi_if ();
nmi_if u_user_7_nmi_if ();
logic [31:0] s_user_1_irq;
logic [31:0] s_user_2_irq;
logic [31:0] s_user_3_irq;
logic [31:0] s_user_4_irq;
logic [31:0] s_user_5_irq;
logic [31:0] s_user_6_irq;
logic [31:0] s_user_7_irq;
// ...
// verilog_format: on
always_comb begin
@@ -61,9 +59,6 @@ module user_core_top (
u_user_6_nmi_if.rdata = '0;
u_user_6_nmi_if.ready = '0;
s_user_6_irq = '0;
u_user_7_nmi_if.rdata = '0;
u_user_7_nmi_if.ready = '0;
s_user_7_irq = '0;
unique case (sel_i)
5'd1: begin
nmi.valid = u_user_1_nmi_if.valid;
@@ -119,15 +114,6 @@ module user_core_top (
u_user_6_nmi_if.ready = nmi.ready;
s_user_6_irq = irq_i;
end
5'd7: begin
nmi.valid = u_user_7_nmi_if.valid;
nmi.addr = u_user_7_nmi_if.addr;
nmi.wdata = u_user_7_nmi_if.wdata;
nmi.wstrb = u_user_7_nmi_if.wstrb;
u_user_7_nmi_if.rdata = nmi.rdata;
u_user_7_nmi_if.ready = nmi.ready;
s_user_7_irq = irq_i;
end
default: begin
nmi.valid = '0;
nmi.addr = '0;
@@ -151,9 +137,6 @@ module user_core_top (
u_user_6_nmi_if.rdata = '0;
u_user_6_nmi_if.ready = '0;
s_user_6_irq = '0;
u_user_7_nmi_if.rdata = '0;
u_user_7_nmi_if.ready = '0;
s_user_7_irq = '0;
end
endcase
end
@@ -201,10 +184,4 @@ module user_core_top (
.nmi (u_user_6_nmi_if)
);
user_core_design_username7 #(7) u_user_core_design_username7 (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.irq_i (s_user_7_irq),
.nmi (u_user_7_nmi_if)
);
endmodule