feat: enhance DMA and RIB functionality with burst support and performance tests

- Updated dma_error_tb to implement burst transfer handling and performance measurement for INCR4 transfers.
- Introduced rib_burst_bus_tb to validate RIB burst arbitration and protocol compliance.
- Added soc_rib_burst_ram_tb to test SRAM behavior with burst commands.
- Created spill_register_tb to verify the functionality of the spill register under various conditions.
- Modified test_dma.py to reflect changes in DMA error handling and performance reporting.
- Updated test_memory_map.py to include new RIB burst interfaces and spill register utilities.
- Enhanced test_rib_burst.py with directed tests for RIB burst building blocks and spill register behavior.
- Adjusted test_soc_topology.py to ensure correct instantiation counts for RIB interfaces.
- Improved test_user_extensions.py to validate the generation of isolated scalar bindings for burst interfaces.

tests/test_performance_log.py

@@ -7,7 +7,7 @@ from scripts.parse_performance_log import parse_log
 
 def test_parse_log_requires_terminal_marker_and_complete_samples() -> None:
     report = parse_log(
-        "PERF region=sdram op=read words=1024 checksum=0x1234 mgmt_wait=10 "
+        "PERF region=sdram op=read words=1024 checksum=0x1234 cycles=123 mgmt_wait=10 "
         "rib_wait=9 sdram_wait=8 psram_wait=0 flash_wait=0 dma_wait=0\n"
         "PERF_BENCHMARK_PASS\n"
     )
@@ -18,6 +18,7 @@ def test_parse_log_requires_terminal_marker_and_complete_samples() -> None:
     assert report["samples"] == [
         {
             "checksum": 0x1234,
+            "cycles": 123,
             "dma_wait": 0,
             "flash_wait": 0,
             "mgmt_wait": 10,
@@ -33,7 +34,7 @@ def test_parse_log_requires_terminal_marker_and_complete_samples() -> None:
 
 def test_parse_log_rejects_missing_benchmark_marker() -> None:
     report = parse_log(
-        "PERF region=flash op=read words=1024 checksum=0 mgmt_wait=1 rib_wait=1 "
+        "PERF region=flash op=read words=1024 checksum=0 cycles=10 mgmt_wait=1 rib_wait=1 "
         "sdram_wait=0 psram_wait=0 flash_wait=1 dma_wait=0\n"
     )
 
@@ -42,7 +43,7 @@ def test_parse_log_rejects_missing_benchmark_marker() -> None:
 
 def test_parse_log_rejects_report_with_performance_failure() -> None:
     report = parse_log(
-        "PERF region=sdram op=read words=1024 checksum=0x1234 mgmt_wait=10 "
+        "PERF region=sdram op=read words=1024 checksum=0x1234 cycles=123 mgmt_wait=10 "
         "rib_wait=9 sdram_wait=8 psram_wait=0 flash_wait=0 dma_wait=0\n"
         "PERF_FAIL region=sdram op=read reason=data expected=1234 actual=0\n"
         "PERF_BENCHMARK_PASS\n"