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https://github.com/retroSoC/retroSoC.git
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feat: refactor NMI to RIB Interface and Update Related Tests
- Replaced instances of nmi_if with rib_if in sysctrl_fault_tb.sv, test_dma.py, test_gpio_user_mux.py, test_memory_map.py, test_performance_log.py, test_script_tools.py, test_sdram.py, test_soc_topology.py, test_sta_constraints.py, and test_user_extensions.py. - Updated test cases to reflect changes from NMI to RIB, ensuring all references and assertions are consistent with the new interface. - Adjusted memory map and performance log tests to validate RIB-specific configurations and behaviors. - Ensured that all relevant file paths and definitions are updated to maintain functionality and correctness across the test suite.
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@@ -15,6 +15,7 @@ ROOT = Path(__file__).resolve().parents[1]
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DOMAINS = ROOT / "rtl/mini/integration/clock_reset_domains.json"
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PIN_MAP = ROOT / "rtl/mini/pin_map/pin_map.json"
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GENERATOR = ROOT / "sta/opensta/generate_sdc.py"
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OPENSTA_MAKEFILE = ROOT / "sta/opensta/opensta.mk"
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GF180_GENERATOR = ROOT / "pdk/generate_gf180_liberty.py"
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ICS55_PREPARER = ROOT / "pdk/prepare_ics55_liberty.py"
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ICS55_SIM_MODEL_PREPARER = ROOT / "pdk/prepare_ics55_sim_model.py"
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@@ -47,13 +48,20 @@ def test_core_sdc_covers_current_clock_domains(tmp_path: Path) -> None:
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assert "create_generated_clock -name clk_system" in sdc
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assert "create_clock -name clk_audio -period 54.253472222" in sdc
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assert "create_clock -name clk_dvp -period 41.666666667" in sdc
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assert "u_dvp_pclk_clk_buf/clk_o" in sdc
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assert "get_pins -quiet" in sdc
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assert "u_retrosoc.u_ip_rib_wrapper/u_rib_dvp.u_dvp_pclk_clk_buf/clk_o" in sdc
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assert "-group [get_clocks {clk_external clk_system}]" in sdc
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assert "set_clock_transition 0.1 [get_clocks {clk_dvp}]" in sdc
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assert "set_input_transition" not in sdc
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assert "set_false_path -from $reset_ext_rst_n_i_pad" in sdc
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def test_opensta_invocation_exits_after_a_tcl_error() -> None:
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makefile = OPENSTA_MAKEFILE.read_text(encoding="utf-8")
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assert "$(OPENSTA) -no_init -exit -threads $(OPENSTA_THREADS)" in makefile
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def test_core_sdc_rejects_pads_missing_from_the_pin_map(tmp_path: Path) -> None:
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document = json.loads(DOMAINS.read_text(encoding="utf-8"))
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document["domains"][3]["sta"]["source_port"] = "missing_pad"
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