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feat: refactor NMI to RIB Interface and Update Related Tests

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- Replaced instances of nmi_if with rib_if in sysctrl_fault_tb.sv, test_dma.py, test_gpio_user_mux.py, test_memory_map.py, test_performance_log.py, test_script_tools.py, test_sdram.py, test_soc_topology.py, test_sta_constraints.py, and test_user_extensions.py.
- Updated test cases to reflect changes from NMI to RIB, ensuring all references and assertions are consistent with the new interface.
- Adjusted memory map and performance log tests to validate RIB-specific configurations and behaviors.
- Ensured that all relevant file paths and definitions are updated to maintain functionality and correctness across the test suite.
This commit is contained in:
maksyuki committed 2026-08-02 15:57:08 +08:00
1 parent 0a6055134e
commit c5dfa96c6f
134 files changed
+3130 -3336
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ATTRIBUTIONS.md
+10 -10
View File
@@ -16,26 +16,26 @@ The header in rtl/tech/tc_clk.sv also states the Solderpad Hardware License, Ver
The following RTL files retain the original header from the Ravenna example SoC project, which refers to a design using PicoRV32 in ASIC:
- rtl/ip/native/peripheral/gpio.sv
- rtl/ip/native/peripheral/timer.sv
- rtl/ip/native/serial/uart.sv
- rtl/ip/rib/peripheral/gpio.sv
- rtl/ip/rib/peripheral/timer.sv
- rtl/ip/rib/serial/uart.sv
The preserved notice attributes the work to Clifford Wolf and Tim Edwards.
## 3. Hirosh Dabui
The SDRAM controller implementation in rtl/ip/native/memory/sdram_core.sv retains the original copyright notice attributed to Hirosh Dabui.
The SDRAM controller implementation in rtl/ip/rib/memory/sdram_core.sv retains the original copyright notice attributed to Hirosh Dabui.
## 4. EmbedFire
Several SPI/I2C-related RTL files retain the original attribution to EmbedFire and refer to source files such as sd_init.v, sd_write.v, sd_read.v, data_rw_ctrl.v, and i2c_ctrl.v:
- rtl/ip/native/serial/i2c_core.sv
- rtl/ip/native/storage/spisd_core.sv
- rtl/ip/native/storage/spisd_data.sv
- rtl/ip/native/storage/spisd_init.sv
- rtl/ip/native/storage/spisd_read.sv
- rtl/ip/native/storage/spisd_write.sv
- rtl/ip/rib/serial/i2c_core.sv
- rtl/ip/rib/storage/spisd_core.sv
- rtl/ip/rib/storage/spisd_data.sv
- rtl/ip/rib/storage/spisd_init.sv
- rtl/ip/rib/storage/spisd_read.sv
- rtl/ip/rib/storage/spisd_write.sv
These headers state that the original code was published on GitHub by EmbedFire, but that the original license was not specified in the retained header.
Makefile
+2 -2
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@@ -208,7 +208,7 @@ endif
benchmark-report \
pin-map check-pin-map soc-topology check-soc-topology user-extensions check-user-extensions \
check-clock-reset-domains tech-cell-test rtl-lint check-rtl-lint \
formal formal-bus formal-nmi2apb formal-clean formal-doctor
formal formal-bus formal-rib2apb formal-clean formal-doctor
.NOTPARALLEL: setup
help:
@@ -233,7 +233,7 @@ help:
' check-user-extensions validate the canonical user-extension map' \
' check-clock-reset-domains validate the root clock/reset and CDC inventory' \
' rtl-lint | check-rtl-lint run/check strict Verilator RTL lint warnings' \
' formal | formal-bus | formal-nmi2apb | formal-sysctrl | formal-pll-rcu | formal-gpio-user run SBY protocol proofs' \
' formal | formal-bus | formal-rib2apb | formal-sysctrl | formal-pll-rcu | formal-gpio-user run SBY protocol proofs' \
' formal-doctor check the SBY, Yosys, sv2v, and Bitwuzla formal toolchain' \
' benchmark-report run the benchmark profile and write meta/performance.json' \
' tech-cell-test test GF180/SKY130 technology IO and clock wrappers' \
NOTICE
+3 -3
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@@ -5,8 +5,8 @@ This repository includes RTL source files that preserve third-party copyright an
The following third-party projects or authors are referenced in the RTL source headers currently present in this repository:
- ETH Zurich and University of Bologna: notices are preserved in several RTL files under rtl/managed/clusterip/, rtl/managed/mpw/core/username7/ibex/, and in rtl/tech/tc_clk.sv.
- Ravenna / PicoRV32 in ASIC: notices are preserved in rtl/ip/native/peripheral/gpio.sv, rtl/ip/native/peripheral/timer.sv, and rtl/ip/native/serial/uart.sv.
- Hirosh Dabui: the original copyright notice is preserved in rtl/ip/native/memory/sdram_core.sv.
- EmbedFire: attribution is preserved in rtl/ip/native/serial/i2c_core.sv and the SPI SD card related files under rtl/ip/native/storage/.
- Ravenna / PicoRV32 in ASIC: notices are preserved in rtl/ip/rib/peripheral/gpio.sv, rtl/ip/rib/peripheral/timer.sv, and rtl/ip/rib/serial/uart.sv.
- Hirosh Dabui: the original copyright notice is preserved in rtl/ip/rib/memory/sdram_core.sv.
- EmbedFire: attribution is preserved in rtl/ip/rib/serial/i2c_core.sv and the SPI SD card related files under rtl/ip/rib/storage/.
These notices are included solely to preserve attribution for the retained third-party source material. They do not alter the licensing terms of the retroSoC repository itself, which is distributed under the Mulan PSL v2 license.
app/apps/benchmark/main.c
+1 -1
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@@ -84,7 +84,7 @@ static void rs_benchmark_report(const char *region, const char *operation, uint3
rs_benchmark_puts(" checksum=");
rs_benchmark_put_hex(checksum);
rs_benchmark_put_counter(" mgmt_wait=", snapshot->mgmt_wait);
rs_benchmark_put_counter(" native_wait=", snapshot->native_wait);
rs_benchmark_put_counter(" rib_wait=", snapshot->rib_wait);
rs_benchmark_put_counter(" sdram_wait=", snapshot->sdram_wait);
rs_benchmark_put_counter(" psram_wait=", snapshot->psram_wait);
rs_benchmark_put_counter(" flash_wait=", snapshot->flash_wait);
app/board/src/w25q128jvxim.c
+1 -1
View File
@@ -283,7 +283,7 @@ void ip_norflash_test(int argc, char **argv) {
(void)argc;
(void)argv;
printf("[NATV IP] qspi nor flash test\n");
printf("[RIB IP] qspi nor flash test\n");
QSPI0_InitStruct_t qspi0 = {
(uint32_t)0, (uint32_t)0b0001, (uint32_t)0, (uint32_t)250,
config/dependencies.lock.json
+2 -2
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@@ -3,7 +3,7 @@
"sources": {
"mpw": {
"url": "https://github.com/retroSoC/mini-ver-mpw.git",
"revision": "30503eb8a7cf33a0c955913faba5014ebd00186f",
"revision": "41955b19fe17d8adbb4b6634ae59709e118f70f9",
"destination": "rtl/managed/mpw",
"license": "NOASSERTION"
},
@@ -62,7 +62,7 @@
},
"cluster_archinfo": {"url": "https://github.com/retroSoC/archinfo.git", "revision": "d65dd13c83a1176668bf5178004814a1551bf6ba", "destination": "rtl/managed/clusterip/archinfo", "license": "NOASSERTION"},
"cluster_clint": {"url": "https://github.com/retroSoC/clint.git", "revision": "ce49f1a5501c0a9f18c0e3f358417648f3f2fb18", "destination": "rtl/managed/clusterip/clint", "license": "NOASSERTION"},
"cluster_common": {"url": "https://github.com/retroSoC/common.git", "revision": "d9921eb05160be873aebc46bb2f820bee2c7eebc", "destination": "rtl/managed/clusterip/common", "license": "NOASSERTION"},
"cluster_common": {"url": "https://github.com/retroSoC/common.git", "revision": "215e47f3774a0f7a493aa2a74da68861d3b6d397", "destination": "rtl/managed/clusterip/common", "license": "NOASSERTION"},
"cluster_crc": {"url": "https://github.com/retroSoC/crc.git", "revision": "4654a63d06d487b5b9fe22af228c36c736b90bad", "destination": "rtl/managed/clusterip/crc", "license": "NOASSERTION"},
"cluster_i2c": {"url": "https://github.com/retroSoC/i2c.git", "revision": "73b024547c5cd70fb8bf801cc7757db2536c604f", "destination": "rtl/managed/clusterip/i2c", "license": "NOASSERTION"},
"cluster_i2s": {"url": "https://github.com/retroSoC/i2s.git", "revision": "bd0978e8b45e4cf4c1335a1fa7311385d2a4e805", "destination": "rtl/managed/clusterip/i2s", "license": "NOASSERTION"},
crt/include/retrosoc/core/soc.h
+126 -126
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@@ -38,125 +38,125 @@
#define RS_SOC_REG32(base, offset) (*(volatile uint32_t *)(uintptr_t)((base) + (offset)))
// gpio
#define reg_gpio_oe RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x00))
#define reg_gpio_cs RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x04))
#define reg_gpio_pu RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x08))
#define reg_gpio_pd RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x0C))
#define reg_gpio_do RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x10))
#define reg_gpio_di RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x14))
#define reg_gpio_ien RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x18))
#define reg_gpio_itype0 RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x1C))
#define reg_gpio_itype1 RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x20))
#define reg_gpio_istat RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x24))
#define reg_gpio_iofcfg RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x28))
#define reg_gpio_pinmux RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x2C))
#define reg_gpio_user_sel RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x30))
#define reg_gpio_user_lock RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x34))
#define reg_gpio_user_status RS_SOC_REG32(RS_SOC_NMI_GPIO_BASE, UINT32_C(0x38))
#define reg_gpio_oe RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x00))
#define reg_gpio_cs RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x04))
#define reg_gpio_pu RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x08))
#define reg_gpio_pd RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x0C))
#define reg_gpio_do RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x10))
#define reg_gpio_di RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x14))
#define reg_gpio_ien RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x18))
#define reg_gpio_itype0 RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x1C))
#define reg_gpio_itype1 RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x20))
#define reg_gpio_istat RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x24))
#define reg_gpio_iofcfg RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x28))
#define reg_gpio_pinmux RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x2C))
#define reg_gpio_user_sel RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x30))
#define reg_gpio_user_lock RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x34))
#define reg_gpio_user_status RS_SOC_REG32(RS_SOC_RIB_GPIO_BASE, UINT32_C(0x38))
// uart0
#define reg_uart0_clkdiv RS_SOC_REG32(RS_SOC_NMI_UART0_BASE, UINT32_C(0x00))
#define reg_uart0_data RS_SOC_REG32(RS_SOC_NMI_UART0_BASE, UINT32_C(0x04))
#define reg_uart0_clkdiv RS_SOC_REG32(RS_SOC_RIB_UART0_BASE, UINT32_C(0x00))
#define reg_uart0_data RS_SOC_REG32(RS_SOC_RIB_UART0_BASE, UINT32_C(0x04))
// tim0
#define reg_tim0_cfg RS_SOC_REG32(RS_SOC_NMI_TIM0_BASE, UINT32_C(0x00))
#define reg_tim0_rld RS_SOC_REG32(RS_SOC_NMI_TIM0_BASE, UINT32_C(0x04))
#define reg_tim0_val RS_SOC_REG32(RS_SOC_NMI_TIM0_BASE, UINT32_C(0x08))
#define reg_tim0_cfg RS_SOC_REG32(RS_SOC_RIB_TIM0_BASE, UINT32_C(0x00))
#define reg_tim0_rld RS_SOC_REG32(RS_SOC_RIB_TIM0_BASE, UINT32_C(0x04))
#define reg_tim0_val RS_SOC_REG32(RS_SOC_RIB_TIM0_BASE, UINT32_C(0x08))
// tim1
#define reg_tim1_cfg RS_SOC_REG32(RS_SOC_NMI_TIM1_BASE, UINT32_C(0x00))
#define reg_tim1_rld RS_SOC_REG32(RS_SOC_NMI_TIM1_BASE, UINT32_C(0x04))
#define reg_tim1_val RS_SOC_REG32(RS_SOC_NMI_TIM1_BASE, UINT32_C(0x08))
#define reg_tim1_cfg RS_SOC_REG32(RS_SOC_RIB_TIM1_BASE, UINT32_C(0x00))
#define reg_tim1_rld RS_SOC_REG32(RS_SOC_RIB_TIM1_BASE, UINT32_C(0x04))
#define reg_tim1_val RS_SOC_REG32(RS_SOC_RIB_TIM1_BASE, UINT32_C(0x08))
// psram
#define reg_psram_wait RS_SOC_REG32(RS_SOC_NMI_PSRAM_BASE, UINT32_C(0x00))
#define reg_psram_chd RS_SOC_REG32(RS_SOC_NMI_PSRAM_BASE, UINT32_C(0x04))
#define reg_psram_init RS_SOC_REG32(RS_SOC_NMI_PSRAM_BASE, UINT32_C(0x08))
#define reg_psram_wait RS_SOC_REG32(RS_SOC_RIB_PSRAM_BASE, UINT32_C(0x00))
#define reg_psram_chd RS_SOC_REG32(RS_SOC_RIB_PSRAM_BASE, UINT32_C(0x04))
#define reg_psram_init RS_SOC_REG32(RS_SOC_RIB_PSRAM_BASE, UINT32_C(0x08))
// spisd
#define reg_spisd_mode RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x00))
#define reg_spisd_clkdiv RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x04))
#define reg_spisd_addr RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x08))
#define reg_spisd_txdata RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x0C))
#define reg_spisd_rxdata RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x10))
#define reg_spisd_status RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x14))
#define reg_spisd_sync RS_SOC_REG32(RS_SOC_NMI_SPISD_BASE, UINT32_C(0x18))
#define reg_spisd_mode RS_SOC_REG32(RS_SOC_RIB_SPISD_BASE, UINT32_C(0x00))
#define reg_spisd_clkdiv RS_SOC_REG32(RS_SOC_RIB_SPISD_BASE, UINT32_C(0x04))
#define reg_spisd_addr RS_SOC_REG32(RS_SOC_RIB_SPISD_BASE, UINT32_C(0x08))
#define reg_spisd_txdata RS_SOC_REG32(RS_SOC_RIB_SPISD_BASE, UINT32_C(0x0C))
#define reg_spisd_rxdata RS_SOC_REG32(RS_SOC_RIB_SPISD_BASE, UINT32_C(0x10))
#define reg_spisd_status RS_SOC_REG32(RS_SOC_RIB_SPISD_BASE, UINT32_C(0x14))
#define reg_spisd_sync RS_SOC_REG32(RS_SOC_RIB_SPISD_BASE, UINT32_C(0x18))
// i2c0
#define reg_i2c0_clkdiv RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x00))
#define reg_i2c0_devaddr RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x04))
#define reg_i2c0_regaddr RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x08))
#define reg_i2c0_txdata RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x0C))
#define reg_i2c0_rxdata RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x10))
#define reg_i2c0_xfer RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x14))
#define reg_i2c0_cfg RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x18))
#define reg_i2c0_status RS_SOC_REG32(RS_SOC_NMI_I2C0_BASE, UINT32_C(0x1C))
#define reg_i2c0_clkdiv RS_SOC_REG32(RS_SOC_RIB_I2C0_BASE, UINT32_C(0x00))
#define reg_i2c0_devaddr RS_SOC_REG32(RS_SOC_RIB_I2C0_BASE, UINT32_C(0x04))
#define reg_i2c0_regaddr RS_SOC_REG32(RS_SOC_RIB_I2C0_BASE, UINT32_C(0x08))
#define reg_i2c0_txdata RS_SOC_REG32(RS_SOC_RIB_I2C0_BASE, UINT32_C(0x0C))
#define reg_i2c0_rxdata RS_SOC_REG32(RS_SOC_RIB_I2C0_BASE, UINT32_C(0x10))
#define reg_i2c0_xfer RS_SOC_REG32(RS_SOC_RIB_I2C0_BASE, UINT32_C(0x14))
#define reg_i2c0_cfg RS_SOC_REG32(RS_SOC_RIB_I2C0_BASE, UINT32_C(0x18))
#define reg_i2c0_status RS_SOC_REG32(RS_SOC_RIB_I2C0_BASE, UINT32_C(0x1C))
// i2s
#define reg_i2s_mode RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x00))
#define reg_i2s_format RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x04))
#define reg_i2s_upbound RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x08))
#define reg_i2s_lowbound RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x0C))
#define reg_i2s_recven RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x10))
#define reg_i2s_txdata RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x14))
#define reg_i2s_rxdata RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x18))
#define reg_i2s_status RS_SOC_REG32(RS_SOC_NMI_I2S_BASE, UINT32_C(0x1C))
#define reg_i2s_mode RS_SOC_REG32(RS_SOC_RIB_I2S_BASE, UINT32_C(0x00))
#define reg_i2s_format RS_SOC_REG32(RS_SOC_RIB_I2S_BASE, UINT32_C(0x04))
#define reg_i2s_upbound RS_SOC_REG32(RS_SOC_RIB_I2S_BASE, UINT32_C(0x08))
#define reg_i2s_lowbound RS_SOC_REG32(RS_SOC_RIB_I2S_BASE, UINT32_C(0x0C))
#define reg_i2s_recven RS_SOC_REG32(RS_SOC_RIB_I2S_BASE, UINT32_C(0x10))
#define reg_i2s_txdata RS_SOC_REG32(RS_SOC_RIB_I2S_BASE, UINT32_C(0x14))
#define reg_i2s_rxdata RS_SOC_REG32(RS_SOC_RIB_I2S_BASE, UINT32_C(0x18))
#define reg_i2s_status RS_SOC_REG32(RS_SOC_RIB_I2S_BASE, UINT32_C(0x1C))
// onewire
#define reg_onewire_clkdiv RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x00))
#define reg_onewire_zerocnt RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x04))
#define reg_onewire_onecnt RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x08))
#define reg_onewire_rstcnt RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x0C))
#define reg_onewire_txdata RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x10))
#define reg_onewire_ctrl RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x14))
#define reg_onewire_status RS_SOC_REG32(RS_SOC_NMI_ONEWIRE_BASE, UINT32_C(0x18))
#define reg_onewire_clkdiv RS_SOC_REG32(RS_SOC_RIB_ONEWIRE_BASE, UINT32_C(0x00))
#define reg_onewire_zerocnt RS_SOC_REG32(RS_SOC_RIB_ONEWIRE_BASE, UINT32_C(0x04))
#define reg_onewire_onecnt RS_SOC_REG32(RS_SOC_RIB_ONEWIRE_BASE, UINT32_C(0x08))
#define reg_onewire_rstcnt RS_SOC_REG32(RS_SOC_RIB_ONEWIRE_BASE, UINT32_C(0x0C))
#define reg_onewire_txdata RS_SOC_REG32(RS_SOC_RIB_ONEWIRE_BASE, UINT32_C(0x10))
#define reg_onewire_ctrl RS_SOC_REG32(RS_SOC_RIB_ONEWIRE_BASE, UINT32_C(0x14))
#define reg_onewire_status RS_SOC_REG32(RS_SOC_RIB_ONEWIRE_BASE, UINT32_C(0x18))
// xpi
#define reg_xpi_cfgidx RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x00))
#define reg_xpi_accmd RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x04))
#define reg_xpi_mmstad RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x08))
#define reg_xpi_mmoffst RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x0C))
#define reg_xpi_mode RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x10))
#define reg_xpi_nss RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x14))
#define reg_xpi_clkdiv RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x18))
#define reg_xpi_rdwr RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x1C))
#define reg_xpi_revdat RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x20))
#define reg_xpi_txupb RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x24))
#define reg_xpi_txlowb RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x28))
#define reg_xpi_rxupb RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x2C))
#define reg_xpi_rxlowb RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x30))
#define reg_xpi_flush RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x34))
#define reg_xpi_cmdtyp RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x38))
#define reg_xpi_cmdlen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x3C))
#define reg_xpi_cmddat RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x40))
#define reg_xpi_adrtyp RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x44))
#define reg_xpi_adrlen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x48))
#define reg_xpi_adrdat RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x4C))
#define reg_xpi_alttyp RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x50))
#define reg_xpi_altlen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x54))
#define reg_xpi_altdat RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x58))
#define reg_xpi_tdulen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x5C))
#define reg_xpi_rdulen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x60))
#define reg_xpi_dattyp RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x64))
#define reg_xpi_datlen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x68))
#define reg_xpi_datbit RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x6C))
#define reg_xpi_hlvlen RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x70))
#define reg_xpi_txdata RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x74))
#define reg_xpi_rxdata RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x78))
#define reg_xpi_start RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x7C))
#define reg_xpi_status RS_SOC_REG32(RS_SOC_NMI_XPI_BASE, UINT32_C(0x80))
#define reg_xpi_cfgidx RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x00))
#define reg_xpi_accmd RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x04))
#define reg_xpi_mmstad RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x08))
#define reg_xpi_mmoffst RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x0C))
#define reg_xpi_mode RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x10))
#define reg_xpi_nss RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x14))
#define reg_xpi_clkdiv RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x18))
#define reg_xpi_rdwr RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x1C))
#define reg_xpi_revdat RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x20))
#define reg_xpi_txupb RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x24))
#define reg_xpi_txlowb RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x28))
#define reg_xpi_rxupb RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x2C))
#define reg_xpi_rxlowb RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x30))
#define reg_xpi_flush RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x34))
#define reg_xpi_cmdtyp RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x38))
#define reg_xpi_cmdlen RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x3C))
#define reg_xpi_cmddat RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x40))
#define reg_xpi_adrtyp RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x44))
#define reg_xpi_adrlen RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x48))
#define reg_xpi_adrdat RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x4C))
#define reg_xpi_alttyp RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x50))
#define reg_xpi_altlen RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x54))
#define reg_xpi_altdat RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x58))
#define reg_xpi_tdulen RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x5C))
#define reg_xpi_rdulen RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x60))
#define reg_xpi_dattyp RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x64))
#define reg_xpi_datlen RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x68))
#define reg_xpi_datbit RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x6C))
#define reg_xpi_hlvlen RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x70))
#define reg_xpi_txdata RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x74))
#define reg_xpi_rxdata RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x78))
#define reg_xpi_start RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x7C))
#define reg_xpi_status RS_SOC_REG32(RS_SOC_RIB_XPI_BASE, UINT32_C(0x80))
// dma(32b xfer, hardware trigger by I2S fifo, QSPI fifo)
#define reg_dma_mode RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x00))
#define reg_dma_srcaddr RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x04))
#define reg_dma_srcincr RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x08))
#define reg_dma_dstaddr RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x0C))
#define reg_dma_dstincr RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x10))
#define reg_dma_xferlen RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x14))
#define reg_dma_start RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x18))
#define reg_dma_stop RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x1C))
#define reg_dma_reset RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x20))
#define reg_dma_status RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x24))
#define reg_dma_fsm RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x28))
#define reg_dma_error_status RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x2C))
#define reg_dma_error_addr RS_SOC_REG32(RS_SOC_NMI_DMA_BASE, UINT32_C(0x30))
#define reg_dma_mode RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x00))
#define reg_dma_srcaddr RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x04))
#define reg_dma_srcincr RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x08))
#define reg_dma_dstaddr RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x0C))
#define reg_dma_dstincr RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x10))
#define reg_dma_xferlen RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x14))
#define reg_dma_start RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x18))
#define reg_dma_stop RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x1C))
#define reg_dma_reset RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x20))
#define reg_dma_status RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x24))
#define reg_dma_fsm RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x28))
#define reg_dma_error_status RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x2C))
#define reg_dma_error_addr RS_SOC_REG32(RS_SOC_RIB_DMA_BASE, UINT32_C(0x30))
#define RS_SOC_DMA_ERROR_PENDING UINT32_C(0x00000001)
#define RS_SOC_DMA_ERROR_RESPONSE_SHIFT 1U
#define RS_SOC_DMA_ERROR_RESPONSE_MASK UINT32_C(0x0000000E)
// sys ctrl
#define RS_SOC_SYSCTRL_REG32(offset) RS_SOC_REG32(RS_SOC_NMI_SYSCTRL_BASE, (offset))
#define reg_sysctrl_coresel RS_SOC_REG32(RS_SOC_NMI_SYSCTRL_BASE, UINT32_C(0x00))
#define reg_sysctrl_ipsel RS_SOC_REG32(RS_SOC_NMI_SYSCTRL_BASE, UINT32_C(0x04))
#define RS_SOC_SYSCTRL_REG32(offset) RS_SOC_REG32(RS_SOC_RIB_SYSCTRL_BASE, (offset))
#define reg_sysctrl_coresel RS_SOC_REG32(RS_SOC_RIB_SYSCTRL_BASE, UINT32_C(0x00))
#define reg_sysctrl_ipsel RS_SOC_REG32(RS_SOC_RIB_SYSCTRL_BASE, UINT32_C(0x04))
#define reg_sysctrl_pll_cfg RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PLL_CFG_OFFSET)
#define reg_sysctrl_pll_cmd RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PLL_CMD_OFFSET)
/* Status: bit 0 pending (W1C), bit 1 write, bits 3:2 reason (1 unmapped, 2 reserved). */
@@ -175,8 +175,8 @@
#define reg_sysctrl_perf_user_wait_hi RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_USER_WAIT_HI_OFFSET)
#define reg_sysctrl_perf_dma_wait_lo RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_DMA_WAIT_LO_OFFSET)
#define reg_sysctrl_perf_dma_wait_hi RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_DMA_WAIT_HI_OFFSET)
#define reg_sysctrl_perf_natv_wait_lo RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_NATV_WAIT_LO_OFFSET)
#define reg_sysctrl_perf_natv_wait_hi RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_NATV_WAIT_HI_OFFSET)
#define reg_sysctrl_perf_rib_wait_lo RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_RIB_WAIT_LO_OFFSET)
#define reg_sysctrl_perf_rib_wait_hi RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_RIB_WAIT_HI_OFFSET)
#define reg_sysctrl_perf_apb_wait_lo RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_APB_WAIT_LO_OFFSET)
#define reg_sysctrl_perf_apb_wait_hi RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_PERF_APB_WAIT_HI_OFFSET)
#define reg_sysctrl_perf_sdram_wait_lo \
@@ -206,28 +206,28 @@
#define RS_SOC_PERF_CTRL_CLEAR UINT32_C(0x00000002)
#define RS_SOC_PERF_CTRL_SNAPSHOT UINT32_C(0x00000004)
// clint
#define reg_clint_mtimel RS_SOC_REG32(RS_SOC_NMI_CLINT_BASE, UINT32_C(0x00))
#define reg_clint_mtimeh RS_SOC_REG32(RS_SOC_NMI_CLINT_BASE, UINT32_C(0x04))
#define reg_clint_mtimecmpl RS_SOC_REG32(RS_SOC_NMI_CLINT_BASE, UINT32_C(0x08))
#define reg_clint_mtimecmph RS_SOC_REG32(RS_SOC_NMI_CLINT_BASE, UINT32_C(0x0C))
#define reg_clint_msip RS_SOC_REG32(RS_SOC_NMI_CLINT_BASE, UINT32_C(0x10))
#define reg_clint_clkdiv RS_SOC_REG32(RS_SOC_NMI_CLINT_BASE, UINT32_C(0x14))
#define reg_clint_mtimel RS_SOC_REG32(RS_SOC_RIB_CLINT_BASE, UINT32_C(0x00))
#define reg_clint_mtimeh RS_SOC_REG32(RS_SOC_RIB_CLINT_BASE, UINT32_C(0x04))
#define reg_clint_mtimecmpl RS_SOC_REG32(RS_SOC_RIB_CLINT_BASE, UINT32_C(0x08))
#define reg_clint_mtimecmph RS_SOC_REG32(RS_SOC_RIB_CLINT_BASE, UINT32_C(0x0C))
#define reg_clint_msip RS_SOC_REG32(RS_SOC_RIB_CLINT_BASE, UINT32_C(0x10))
#define reg_clint_clkdiv RS_SOC_REG32(RS_SOC_RIB_CLINT_BASE, UINT32_C(0x14))
// sdram
#define reg_sdram_clkdiv RS_SOC_REG32(RS_SOC_NMI_SDRAM_BASE, UINT32_C(0x00))
#define reg_sdram_cfg RS_SOC_REG32(RS_SOC_NMI_SDRAM_BASE, UINT32_C(0x04))
#define reg_sdram_clkdiv RS_SOC_REG32(RS_SOC_RIB_SDRAM_BASE, UINT32_C(0x00))
#define reg_sdram_cfg RS_SOC_REG32(RS_SOC_RIB_SDRAM_BASE, UINT32_C(0x04))
// dvp
#define reg_dvp_recven RS_SOC_REG32(RS_SOC_NMI_DVP_BASE, UINT32_C(0x00))
#define reg_dvp_rxdata RS_SOC_REG32(RS_SOC_NMI_DVP_BASE, UINT32_C(0x04))
#define reg_dvp_status RS_SOC_REG32(RS_SOC_NMI_DVP_BASE, UINT32_C(0x08))
#define reg_dvp_recven RS_SOC_REG32(RS_SOC_RIB_DVP_BASE, UINT32_C(0x00))
#define reg_dvp_rxdata RS_SOC_REG32(RS_SOC_RIB_DVP_BASE, UINT32_C(0x04))
#define reg_dvp_status RS_SOC_REG32(RS_SOC_RIB_DVP_BASE, UINT32_C(0x08))
// i2c1
#define reg_i2c1_clkdiv RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x00))
#define reg_i2c1_devaddr RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x04))
#define reg_i2c1_regaddr RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x08))
#define reg_i2c1_txdata RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x0C))
#define reg_i2c1_rxdata RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x10))
#define reg_i2c1_xfer RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x14))
#define reg_i2c1_cfg RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x18))
#define reg_i2c1_status RS_SOC_REG32(RS_SOC_NMI_I2C1_BASE, UINT32_C(0x1C))
#define reg_i2c1_clkdiv RS_SOC_REG32(RS_SOC_RIB_I2C1_BASE, UINT32_C(0x00))
#define reg_i2c1_devaddr RS_SOC_REG32(RS_SOC_RIB_I2C1_BASE, UINT32_C(0x04))
#define reg_i2c1_regaddr RS_SOC_REG32(RS_SOC_RIB_I2C1_BASE, UINT32_C(0x08))
#define reg_i2c1_txdata RS_SOC_REG32(RS_SOC_RIB_I2C1_BASE, UINT32_C(0x0C))
#define reg_i2c1_rxdata RS_SOC_REG32(RS_SOC_RIB_I2C1_BASE, UINT32_C(0x10))
#define reg_i2c1_xfer RS_SOC_REG32(RS_SOC_RIB_I2C1_BASE, UINT32_C(0x14))
#define reg_i2c1_cfg RS_SOC_REG32(RS_SOC_RIB_I2C1_BASE, UINT32_C(0x18))
#define reg_i2c1_status RS_SOC_REG32(RS_SOC_RIB_I2C1_BASE, UINT32_C(0x1C))
// archinfo
#define reg_archinfo_sys RS_SOC_REG32(RS_SOC_APB_ARCHINFO_BASE, UINT32_C(0x00))
#define reg_archinfo_idl RS_SOC_REG32(RS_SOC_APB_ARCHINFO_BASE, UINT32_C(0x04))
crt/include/retrosoc/hal/perf.h
+1 -1
View File
@@ -9,7 +9,7 @@ typedef struct {
uint64_t mgmt_wait;
uint64_t user_wait;
uint64_t dma_wait;
uint64_t native_wait;
uint64_t rib_wait;
uint64_t apb_wait;
uint64_t sdram_wait;
uint64_t psram_wait;
crt/src/hal/gpio.c
+1 -1
View File
@@ -7,7 +7,7 @@ void ip_gpio_test(int argc, char **argv) {
(void)argc;
(void)argv;
printf("[NATV IP] gpio test\n");
printf("[RIB IP] gpio test\n");
printf("[GPIO OE] %x\n", reg_gpio_oe);
reg_gpio_oe = (uint32_t)0b1111;
crt/src/hal/perf.c
+2 -2
View File
@@ -30,8 +30,8 @@ rs_status_t rs_perf_snapshot(rs_perf_snapshot_t *snapshot) {
rs_perf_read_counter(&reg_sysctrl_perf_user_wait_lo, &reg_sysctrl_perf_user_wait_hi);
snapshot->dma_wait =
rs_perf_read_counter(&reg_sysctrl_perf_dma_wait_lo, &reg_sysctrl_perf_dma_wait_hi);
snapshot->native_wait =
rs_perf_read_counter(&reg_sysctrl_perf_natv_wait_lo, &reg_sysctrl_perf_natv_wait_hi);
snapshot->rib_wait =
rs_perf_read_counter(&reg_sysctrl_perf_rib_wait_lo, &reg_sysctrl_perf_rib_wait_hi);
snapshot->apb_wait =
rs_perf_read_counter(&reg_sysctrl_perf_apb_wait_lo, &reg_sysctrl_perf_apb_wait_hi);
snapshot->sdram_wait =
crt/src/hal/timer.c
+1 -1
View File
@@ -29,7 +29,7 @@ void ip_tim_test(int argc, char **argv) {
(void)argc;
(void)argv;
printf("[NATV IP] counter timer test\n");
printf("[RIB IP] counter timer test\n");
printf("[tim0 reload] %x\n", reg_tim0_rld);
printf("[tim0 config] %x\n", reg_tim0_cfg);
printf("[tim1 reload] %x\n", reg_tim1_rld);
docs/engineering.md
+1 -1
View File
@@ -111,7 +111,7 @@ Verilator regressions.
`make CONFIG=configs/ci/ihp130.mk formal` proves selected
protocol invariants with SymbiYosys, Yosys, `sv2v`, and Bitwuzla. The current
targets are `bus`, `nmi2apb`, `sysctrl`, `pll_rcu`, and `gpio_user`; each uses
targets are `bus`, `rib2apb`, `sysctrl`, `pll_rcu`, and `gpio_user`; each uses
the SBY `prove` task for bounded model checking and k-induction, plus a
`cover` task, at depth 20. `sysctrl` checks register side effects, PLL request
handling, and fault reporting. `pll_rcu` checks the clock-switch controller
docs/soc-integration-wiring.md
+4 -4
View File
@@ -29,15 +29,15 @@ only exposes the pad-side subset of `gpio_if`; neither module contains state.
## User IP GPIO ownership
The fixed user-IP integration does not add dedicated user GPIO pads. A user IP
can instead drive any of the 32 native GPIO pads through `user_gpio_if`. Software
selects an owner per pin with the native GPIO `USER_SEL` register at offset
can instead drive any of the 32 rib GPIO pads through `user_gpio_if`. Software
selects an owner per pin with the rib GPIO `USER_SEL` register at offset
`0x30`; clear selects the existing software/alternate GPIO path and set selects
the user IP. `USER_LOCK` at `0x34` is write-one-set and prevents a selected
owner bit from changing until reset. `USER_STATUS` at `0x38` reports the user
IP pins that are actively connected.
On every accepted ownership change, the pad output enable is forced low for one
full system clock. The native GPIO block retains `CS`, `PU`, and `PD` control
full system clock. The rib GPIO block retains `CS`, `PU`, and `PD` control
in all modes. User IPs provide only output data, output enable, and sampled pad
input. Configure the target output data and enable before writing `USER_SEL`,
then program `USER_LOCK` after the handoff when the assignment is permanent.
@@ -45,5 +45,5 @@ then program `USER_LOCK` after the handoff when the assignment is permanent.
User-IP RTL must declare its GPIO port as `user_gpio_if.user_ip gpio`; the only
signals available through that port are `do_o`, `oe_o`, and `di_i`. The MPW
generator migrates the locked legacy examples in its isolated build output, so
they cannot drive native GPIO electrical controls. New IP submissions must use
they cannot drive rib GPIO electrical controls. New IP submissions must use
the `user_gpio_if` declaration directly.
quality/warnings/ihp130/rtl-lint.json
+274 -484
View File
File diff suppressed because it is too large. Load diff
quality/warnings/ihp130/yosys.json
+4 -19
View File
@@ -1,39 +1,24 @@
{
"entries": [
{
"count": 1,
"example": "warning:Wire hazard3_csr$retrosoc_asic.u_retrosoc.u_core_wrapper.u_hazard3_cpu_1port.core.csr_u.\\debug_mode is used but has no driver.",
"signature": "1097d6b92f19e707"
},
{
"count": 1,
"count": 2,
"example": "warning:asynchronous load value missing for variable '\\update_irq_reg_arrays.i'",
"signature": "56c5f69398be8d7b"
},
{
"count": 1,
"example": "warning:Wire hazard3_csr$retrosoc_asic.u_retrosoc.u_core_wrapper.u_hazard3_cpu_1port.core.csr_u.\\pending_dbg_resume_prev is used but has no driver.",
"signature": "5bbc6025e51705ec"
},
{
"count": 9,
"count": 11,
"example": "warning:The network is combinational (run \"fraig\" or \"fraig_sweep\").",
"signature": "62cc5ee554312205"
},
{
"count": 2,
"count": 4,
"example": "warning:asynchronous load value missing for variable '\\update_nonconst.prev'",
"signature": "a30df20b98d49196"
},
{
"count": 2,
"count": 4,
"example": "warning:asynchronous load value missing for variable '\\update_nonconst.nonconst'",
"signature": "d35463a1de40c7b2"
},
{
"count": 1,
"example": "warning:Wire hazard3_csr$retrosoc_asic.u_retrosoc.u_core_wrapper.u_hazard3_cpu_1port.core.csr_u.\\dbg_req_resume_prev is used but has no driver.",
"signature": "ef03dcca25b39dcb"
}
],
"profile": "ihp130",
rtl/ip/README.md
+2 -2
View File
@@ -1,8 +1,8 @@
# Native and Experimental IP
# RIB and Experimental IP
This directory owns project RTL IP.
native groups maintained blocks by function: interconnect, util, memory,
rib groups maintained blocks by function: interconnect, util, memory,
storage, serial, multimedia, and peripheral. The Mini SoC selects active
sources explicitly in rtl/mini/filelist/ip.fl, whose source order is part of
the build contract.
rtl/ip/experimental/axi4f2nmi.sv → rtl/ip/experimental/axi4f2rib.sv
+2 -2
View File
@@ -8,7 +8,7 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
module axi4f2nmi (
module axi4f2rib (
// verilog_format: off
input logic aclk_i,
input logic aresetn_i,
@@ -29,7 +29,7 @@ module axi4f2nmi (
output logic [ 1:0] rresp_o,
output logic rvalid_o,
input logic rready_i,
nmi_if.master nmi
rib_if.master rib
// verilog_format: on
);
rtl/ip/experimental/gpu.sv
+1 -1
View File
@@ -8,5 +8,5 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
module nmi_gpu ();
module rib_gpu ();
endmodule
rtl/ip/experimental/wb2nmi.sv → rtl/ip/experimental/wb2rib.sv
+1 -1
View File
@@ -10,5 +10,5 @@
`include "mmap_define.svh"
module wb2nmi ();
module wb2rib ();
endmodule
rtl/ip/native/interconnect/nmi_regslice.sv
-136
View File
@@ -1,136 +0,0 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
module nmi_regslice (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
nmi_if.slave nmi_slv,
nmi_if.master nmi_mst
// verilog_format: on
);
localparam FSM_IDLE = 2'd0;
localparam FSM_REQ = 2'd1;
localparam FSM_RESP = 2'd2;
logic [1:0] s_fsm_d, s_fsm_q;
logic s_nmi_mst_valid_d, s_nmi_mst_valid_q;
logic [31:0] s_nmi_mst_addr_d, s_nmi_mst_addr_q;
logic [31:0] s_nmi_mst_wdata_d, s_nmi_mst_wdata_q;
logic [3:0] s_nmi_mst_wstrb_d, s_nmi_mst_wstrb_q;
logic [31:0] s_nmi_mst_rdata_d, s_nmi_mst_rdata_q;
logic s_nmi_mst_ready_d, s_nmi_mst_ready_q;
// nmi mst if
assign nmi_mst.valid = s_nmi_mst_valid_q;
assign nmi_mst.addr = s_nmi_mst_addr_q;
assign nmi_mst.wdata = s_nmi_mst_wdata_q;
assign nmi_mst.wstrb = s_nmi_mst_wstrb_q;
always_comb begin
s_fsm_d = s_fsm_q;
s_nmi_mst_valid_d = s_nmi_mst_valid_q;
s_nmi_mst_addr_d = s_nmi_mst_addr_q;
s_nmi_mst_wdata_d = s_nmi_mst_wdata_q;
s_nmi_mst_wstrb_d = s_nmi_mst_wstrb_q;
s_nmi_mst_ready_d = s_nmi_mst_ready_q;
s_nmi_mst_rdata_d = s_nmi_mst_rdata_q;
nmi_slv.ready = '0;
nmi_slv.rdata = '0;
unique case (s_fsm_q)
FSM_IDLE: begin
if (nmi_slv.valid) begin
s_fsm_d = FSM_REQ;
s_nmi_mst_valid_d = nmi_slv.valid;
s_nmi_mst_addr_d = nmi_slv.addr;
s_nmi_mst_wdata_d = nmi_slv.wdata;
s_nmi_mst_wstrb_d = nmi_slv.wstrb;
end
end
FSM_REQ: begin
if (nmi_mst.ready) begin
s_fsm_d = FSM_RESP;
s_nmi_mst_valid_d = 1'b0;
s_nmi_mst_ready_d = nmi_mst.ready;
s_nmi_mst_rdata_d = nmi_mst.rdata;
end
end
FSM_RESP: begin
s_fsm_d = FSM_IDLE;
nmi_slv.ready = s_nmi_mst_ready_q;
nmi_slv.rdata = s_nmi_mst_rdata_q;
end
default: begin
s_fsm_d = s_fsm_q;
s_nmi_mst_valid_d = s_nmi_mst_valid_q;
s_nmi_mst_addr_d = s_nmi_mst_addr_q;
s_nmi_mst_wdata_d = s_nmi_mst_wdata_q;
s_nmi_mst_wstrb_d = s_nmi_mst_wstrb_q;
s_nmi_mst_ready_d = s_nmi_mst_ready_q;
s_nmi_mst_rdata_d = s_nmi_mst_rdata_q;
nmi_slv.ready = '0;
nmi_slv.rdata = '0;
end
endcase
end
dffr #(2) u_fsm_dffr (
clk_i,
rst_n_i,
s_fsm_d,
s_fsm_q
);
dffr #(1) u_nmi_mstr_valid_dffr (
clk_i,
rst_n_i,
s_nmi_mst_valid_d,
s_nmi_mst_valid_q
);
dffr #(32) u_nmi_mst_addr_dffr (
clk_i,
rst_n_i,
s_nmi_mst_addr_d,
s_nmi_mst_addr_q
);
dffr #(32) u_nmi_mst_wdata_dffr (
clk_i,
rst_n_i,
s_nmi_mst_wdata_d,
s_nmi_mst_wdata_q
);
dffr #(4) u_nmi_mst_wstrb_dffr (
clk_i,
rst_n_i,
s_nmi_mst_wstrb_d,
s_nmi_mst_wstrb_q
);
dffr #(32) u_nmi_mst_rdata_dffr (
clk_i,
rst_n_i,
s_nmi_mst_rdata_d,
s_nmi_mst_rdata_q
);
dffr #(1) u_nmi_mst_ready_dffr (
clk_i,
rst_n_i,
s_nmi_mst_ready_d,
s_nmi_mst_ready_q
);
endmodule
rtl/ip/native/peripheral/gpio_define.svh
-32
View File
@@ -1,32 +0,0 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef NMI_GPIO_DEF_SV
`define NMI_GPIO_DEF_SV
// verilog_format: off
`define NMI_GPIO_NUM 32
`define NMI_GPIO_OE 8'h00 // rw
`define NMI_GPIO_CS 8'h04 // rw
`define NMI_GPIO_PU 8'h08 // rw
`define NMI_GPIO_PD 8'h0C // rw
`define NMI_GPIO_DO 8'h10 // rw
`define NMI_GPIO_DI 8'h14 // ro
`define NMI_GPIO_IEN 8'h18 // rw
`define NMI_GPIO_ITYPE0 8'h1c // rw
`define NMI_GPIO_ITYPE1 8'h20 // rw
`define NMI_GPIO_ISTAT 8'h24 // ro
`define NMI_GPIO_IOFCFG 8'h28 // rw
`define NMI_GPIO_PINMUX 8'h2c // rw
`define NMI_GPIO_USER_SEL 8'h30 // rw
`define NMI_GPIO_USER_LOCK 8'h34 // rw1s
`define NMI_GPIO_USER_STATUS 8'h38 // ro
// verilog_format: on
`endif
rtl/ip/native/storage/spisd_reg.sv
-157
View File
@@ -1,157 +0,0 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef NATV_SPISD_DEF_SV
`define NATV_SPISD_DEF_SV
// verilog_format: off
`define NATV_SPISD_MODE 8'h00
`define NATV_SPISD_CLKDIV 8'h04
`define NATV_SPISD_ADDR 8'h08
`define NATV_SPISD_TXDATA 8'h0C
`define NATV_SPISD_RXDATA 8'h10
`define NATV_SPISD_STATUS 8'h14
`define NATV_SPISD_SYNC 8'h18
// verilog_format: on
`endif
module spisd_reg (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
input logic init_done_i,
output logic wr_sync_o,
input logic wr_sync_done_i,
output logic mode_o,
output logic [1:0] clkdiv_o,
nmi_if.slave nmi,
nmi_if.master byp_nmi
// verilog_format: on
);
// nmi
logic s_nmi_wr_hdshk, s_nmi_rd_hdshk;
logic s_nmi_ready_d, s_nmi_ready_q;
logic s_nmi_rdata_en;
logic [31:0] s_nmi_rdata_d, s_nmi_rdata_q;
// reg
logic s_spisd_mode_en;
logic s_spisd_mode_d, s_spisd_mode_q;
logic s_spisd_clkdiv_en;
logic [1:0] s_spisd_clkdiv_d, s_spisd_clkdiv_q;
logic s_spisd_addr_en;
logic [31:0] s_spisd_addr_d, s_spisd_addr_q;
logic [1:0] s_spisd_status_d, s_spisd_status_q;
// common
logic s_wr_byp, s_rd_byp;
// nmi
assign s_nmi_wr_hdshk = nmi.valid && (~s_nmi_ready_q) && (|nmi.wstrb);
assign s_nmi_rd_hdshk = nmi.valid && (~s_nmi_ready_q) && (~(|nmi.wstrb));
assign s_wr_byp = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_SPISD_TXDATA;
assign s_rd_byp = s_nmi_rd_hdshk && nmi.addr[7:0] == `NATV_SPISD_RXDATA;
assign nmi.ready = (s_wr_byp || s_rd_byp) ? byp_nmi.ready : s_nmi_ready_q;
assign nmi.rdata = (s_wr_byp || s_rd_byp) ? byp_nmi.rdata : s_nmi_rdata_q;
// common
assign mode_o = s_spisd_mode_q;
assign clkdiv_o = s_spisd_clkdiv_q;
// byp
assign byp_nmi.valid = s_wr_byp || s_rd_byp;
assign byp_nmi.addr = s_spisd_addr_q;
assign byp_nmi.wdata = nmi.wdata;
assign byp_nmi.wstrb = nmi.wstrb;
assign s_spisd_mode_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_SPISD_MODE;
assign s_spisd_mode_d = nmi.wdata[0];
dffer #(1) u_spisd_mode_dffer (
clk_i,
rst_n_i,
s_spisd_mode_en,
s_spisd_mode_d,
s_spisd_mode_q
);
assign s_spisd_clkdiv_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_SPISD_CLKDIV;
assign s_spisd_clkdiv_d = nmi.wdata[1:0];
dffer #(2) u_spisd_clkdiv_dffer (
clk_i,
rst_n_i,
s_spisd_clkdiv_en,
s_spisd_clkdiv_d,
s_spisd_clkdiv_q
);
assign s_spisd_addr_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_SPISD_ADDR;
always_comb begin
s_spisd_addr_d = s_spisd_addr_q;
if (nmi.wstrb[0]) s_spisd_addr_d[7:0] = nmi.wdata[7:0];
if (nmi.wstrb[1]) s_spisd_addr_d[15:8] = nmi.wdata[15:8];
if (nmi.wstrb[2]) s_spisd_addr_d[23:16] = nmi.wdata[23:16];
if (nmi.wstrb[3]) s_spisd_addr_d[31:24] = nmi.wdata[31:24];
end
dffer #(32) u_spisd_addr_dffer (
clk_i,
rst_n_i,
s_spisd_addr_en,
s_spisd_addr_d,
s_spisd_addr_q
);
// 0: init done
// 1: wr sync done
always_comb begin
s_spisd_status_d = s_spisd_status_q;
s_spisd_status_d[0] = init_done_i;
if (wr_sync_done_i && ~s_spisd_status_q[1]) begin
s_spisd_status_d[1] = 1'b1;
end else if (s_spisd_status_q[1] && s_nmi_rd_hdshk && nmi.addr[7:0] == `NATV_SPISD_STATUS) begin
s_spisd_status_d[1] = 1'b0;
end
end
dffr #(2) u_spisd_status_dffr (
clk_i,
rst_n_i,
s_spisd_status_d,
s_spisd_status_q
);
// software wr sync
assign wr_sync_o = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_SPISD_SYNC;
assign s_nmi_ready_d = nmi.valid && (~s_nmi_ready_q);
dffr #(1) u_nmi_ready_dffr (
clk_i,
rst_n_i,
s_nmi_ready_d,
s_nmi_ready_q
);
assign s_nmi_rdata_en = s_nmi_rd_hdshk;
always_comb begin
s_nmi_rdata_d = s_nmi_rdata_q;
unique case (nmi.addr[7:0])
`NATV_SPISD_MODE: s_nmi_rdata_d = {31'd0, s_spisd_mode_q};
`NATV_SPISD_CLKDIV: s_nmi_rdata_d = {30'd0, s_spisd_clkdiv_q};
`NATV_SPISD_ADDR: s_nmi_rdata_d = s_spisd_addr_q;
`NATV_SPISD_STATUS: s_nmi_rdata_d = {30'd0, s_spisd_status_q};
default: s_nmi_rdata_d = s_nmi_rdata_q;
endcase
end
dffer #(32) u_nmi_rdata_dffer (
clk_i,
rst_n_i,
s_nmi_rdata_en,
s_nmi_rdata_d,
s_nmi_rdata_q
);
endmodule
rtl/ip/native/storage/xpi_define.svh
-58
View File
@@ -1,58 +0,0 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef NMI_XPI_DEF_SV
`define NMI_XPI_DEF_SV
// verilog_format: off
`define NMI_XPI_CFGIDX 8'h00
`define NMI_XPI_ACCMD 8'h04
`define NMI_XPI_MMSTAD 8'h08
`define NMI_XPI_MMOFFST 8'h0C
`define NMI_XPI_MODE 8'h10
`define NMI_XPI_NSS 8'h14
`define NMI_XPI_CLKDIV 8'h18
`define NMI_XPI_RDWR 8'h1C
`define NMI_XPI_REVDAT 8'h20
`define NMI_XPI_TXUPB 8'h24
`define NMI_XPI_TXLOWB 8'h28
`define NMI_XPI_RXUPB 8'h2C
`define NMI_XPI_RXLOWB 8'h30
`define NMI_XPI_FLUSH 8'h34
`define NMI_XPI_CMDTYP 8'h38
`define NMI_XPI_CMDLEN 8'h3C
`define NMI_XPI_CMDDAT 8'h40
`define NMI_XPI_ADRTYP 8'h44
`define NMI_XPI_ADRLEN 8'h48
`define NMI_XPI_ADRDAT 8'h4C
`define NMI_XPI_ALTTYP 8'h50
`define NMI_XPI_ALTLEN 8'h54
`define NMI_XPI_ALTDAT 8'h58
`define NMI_XPI_TDULEN 8'h5C
`define NMI_XPI_RDULEN 8'h60
`define NMI_XPI_DATTYP 8'h64
`define NMI_XPI_DATLEN 8'h68
`define NMI_XPI_DATBIT 8'h6C
`define NMI_XPI_HLVLEN 8'h70
`define NMI_XPI_TXDATA 8'h74
`define NMI_XPI_RXDATA 8'h78
`define NMI_XPI_XST 8'h7C
`define NMI_XPI_STATUS 8'h80
`define XPI_TYPE_NONE 2'd0
`define XPI_TYPE_SNGL 2'd1
`define XPI_TYPE_DUAL 2'd2
`define XPI_TYPE_QUAD 2'd3
`define XPI_NSS_NUM 4
`define XPI_LNS_NUM $clog2(`XPI_NSS_NUM)
// verilog_format: on
`endif
rtl/ip/native/interconnect/ahbl2nmi.sv → rtl/ip/rib/interconnect/ahbl2rib.sv
+30 -30
View File
@@ -9,9 +9,9 @@
// See the Mulan PSL v2 for more details.
module ahbl2nmi (
module ahbl2rib (
ahbl_if.slave ahbl,
nmi_if.master nmi
rib_if.master rib
);
localparam AHBL_TRANS_IDLE = 2'b00;
@@ -39,61 +39,61 @@ module ahbl2nmi (
// ahbl if
// NOTE: need to gurantee `ahbl.hready` and `ahbl.hrdata` sampled in same cycle
assign ahbl.hready = (s_fsm_q == STATE_IDLE) || nmi.ready;
assign ahbl.hready = (s_fsm_q == STATE_IDLE) || rib.ready;
assign ahbl.hresp = AHBL_RESP_OKAY;
assign ahbl.hrdata = nmi.rdata;
assign ahbl.hrdata = rib.rdata;
// nmi if
assign nmi.valid = s_fsm_q != STATE_IDLE;
assign nmi.addr = {s_haddr_q[31:2], 2'b00};
// rib if
assign rib.valid = s_fsm_q != STATE_IDLE;
assign rib.addr = {s_haddr_q[31:2], 2'b00};
always_comb begin
nmi.wstrb = '0;
nmi.wdata = '0;
rib.wstrb = '0;
rib.wdata = '0;
if (s_hwrite_q) begin
unique case (s_hsize_q)
AHBL_SIZE_BYTE: begin
unique case (s_haddr_q[1:0])
2'b00: begin
nmi.wstrb = 4'b0001;
nmi.wdata = {24'b0, ahbl.hwdata[7:0]};
rib.wstrb = 4'b0001;
rib.wdata = {24'b0, ahbl.hwdata[7:0]};
end
2'b01: begin
nmi.wstrb = 4'b0010;
nmi.wdata = {16'b0, ahbl.hwdata[7:0], 8'b0};
rib.wstrb = 4'b0010;
rib.wdata = {16'b0, ahbl.hwdata[7:0], 8'b0};
end
2'b10: begin
nmi.wstrb = 4'b0100;
nmi.wdata = {8'b0, ahbl.hwdata[7:0], 16'b0};
rib.wstrb = 4'b0100;
rib.wdata = {8'b0, ahbl.hwdata[7:0], 16'b0};
end
2'b11: begin
nmi.wstrb = 4'b1000;
nmi.wdata = {ahbl.hwdata[7:0], 24'b0};
rib.wstrb = 4'b1000;
rib.wdata = {ahbl.hwdata[7:0], 24'b0};
end
default: begin
nmi.wstrb = 4'b0001;
nmi.wdata = {24'b0, ahbl.hwdata[7:0]};
rib.wstrb = 4'b0001;
rib.wdata = {24'b0, ahbl.hwdata[7:0]};
end
endcase
end
AHBL_SIZE_HWRD: begin
unique case (s_haddr_q[1])
1'b0: begin
nmi.wstrb = 4'b0011;
nmi.wdata = {16'b0, ahbl.hwdata[15:0]};
rib.wstrb = 4'b0011;
rib.wdata = {16'b0, ahbl.hwdata[15:0]};
end
1'b1: begin
nmi.wstrb = 4'b1100;
nmi.wdata = {ahbl.hwdata[15:0], 16'd0};
rib.wstrb = 4'b1100;
rib.wdata = {ahbl.hwdata[15:0], 16'd0};
end
endcase
end
AHBL_SIZE_WORD: begin
nmi.wstrb = 4'b1111;
nmi.wdata = ahbl.hwdata;
rib.wstrb = 4'b1111;
rib.wdata = ahbl.hwdata;
end
default: begin
nmi.wstrb = 4'b1111;
nmi.wdata = ahbl.hwdata;
rib.wstrb = 4'b1111;
rib.wdata = ahbl.hwdata;
end
endcase
end
@@ -117,8 +117,8 @@ module ahbl2nmi (
end
end
STATE_DATA: begin
if (~nmi.ready) s_fsm_d = STATE_WAIT;
// nmi.ready == 1'b1
if (~rib.ready) s_fsm_d = STATE_WAIT;
// rib.ready == 1'b1
else if (ahbl.htrans == AHBL_TRANS_NSEQ) begin
s_fsm_d = STATE_DATA;
s_haddr_d = ahbl.haddr;
@@ -127,7 +127,7 @@ module ahbl2nmi (
end else s_fsm_d = STATE_IDLE;
end
STATE_WAIT: begin
if (nmi.ready) begin
if (rib.ready) begin
if (ahbl.htrans == AHBL_TRANS_NSEQ) begin
s_fsm_d = STATE_DATA;
s_haddr_d = ahbl.haddr;
rtl/ip/native/interconnect/axi4l2nmi.sv → rtl/ip/rib/interconnect/axi4l2rib.sv
+12 -12
View File
@@ -8,7 +8,7 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
module axi4l2nmi (
module axi4l2rib (
// verilog_format: off
input logic aclk_i,
input logic aresetn_i,
@@ -29,7 +29,7 @@ module axi4l2nmi (
output logic [ 1:0] rresp_o,
output logic rvalid_o,
input logic rready_i,
nmi_if.master nmi
rib_if.master rib
// verilog_format: on
);
@@ -58,7 +58,7 @@ module axi4l2nmi (
if (arvalid_i) s_rd_fsm_d = RD_DATA;
end
RD_DATA: begin
if (nmi.ready) s_rd_fsm_d = RD_WAIT;
if (rib.ready) s_rd_fsm_d = RD_WAIT;
end
RD_WAIT: begin
if (rready_i) s_rd_fsm_d = RD_IDLE;
@@ -83,7 +83,7 @@ module axi4l2nmi (
if (wvalid_i) s_wr_fsm_d = WR_WAIT;
end
WR_WAIT: begin
if (nmi.ready) s_wr_fsm_d = WR_RESP;
if (rib.ready) s_wr_fsm_d = WR_RESP;
end
WR_RESP: begin
if (bready_i) s_wr_fsm_d = WR_IDLE;
@@ -99,12 +99,12 @@ module axi4l2nmi (
);
always_comb begin
nmi.addr = s_addr_q;
rib.addr = s_addr_q;
if (s_rd_fsm_q == RD_IDLE && arvalid_i) begin
nmi.addr = araddr_i;
rib.addr = araddr_i;
s_addr_d = araddr_i;
end else if (s_wr_fsm_q == WR_IDLE && awvalid_i) begin
nmi.addr = awaddr_i;
rib.addr = awaddr_i;
s_addr_d = awaddr_i;
end
end
@@ -116,11 +116,11 @@ module axi4l2nmi (
s_addr_q
);
assign s_rdata_d = nmi.rdata;
assign s_rdata_d = rib.rdata;
dffer #(32) u_rdata_dffer (
aclk_i,
aresetn_i,
s_rd_fsm_q == RD_DATA && nmi.ready,
s_rd_fsm_q == RD_DATA && rib.ready,
s_rdata_d,
s_rdata_q
);
@@ -156,7 +156,7 @@ module axi4l2nmi (
assign s_rd_req = (s_rd_fsm_q == RD_DATA || s_rd_fsm_q == RD_WAIT);
assign s_wr_req = s_wr_fsm_q == WR_WAIT;
assign nmi.valid = s_rd_req || s_wr_req;
assign nmi.wdata = s_wdata_q;
assign nmi.wstrb = (s_wr_fsm_q == WR_WAIT) ? s_wstrb_q : '0;
assign rib.valid = s_rd_req || s_wr_req;
assign rib.wdata = s_wdata_q;
assign rib.wstrb = (s_wr_fsm_q == WR_WAIT) ? s_wstrb_q : '0;
endmodule
rtl/ip/native/interconnect/nmi2apb.sv → rtl/ip/rib/interconnect/rib2apb.sv
+6 -6
View File
@@ -10,11 +10,11 @@
`include "mmap_define.svh"
module nmi2apb (
module rib2apb (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
nmi_if.slave nmi,
rib_if.slave rib,
output logic resp_err_o,
`include "soc_apb_ports.svh"
// verilog_format: on
@@ -40,7 +40,7 @@ module nmi2apb (
edge_det_sync_re #(1) u_mem_valid_edge_det_sync_re (
clk_i,
rst_n_i,
nmi.valid,
rib.valid,
s_mem_valid_re
);
// verilog_format: on
@@ -64,9 +64,9 @@ module nmi2apb (
s_fsm_q
);
assign nmi.ready = nmi.valid && (s_fsm_q == FSM_ENAB) && s_xfer_ready;
assign nmi.rdata = {32{nmi.ready}} & s_rd_data;
assign resp_err_o = nmi.ready && s_xfer_error;
assign rib.ready = rib.valid && (s_fsm_q == FSM_ENAB) && s_xfer_ready;
assign rib.rdata = {32{rib.ready}} & s_rd_data;
assign resp_err_o = rib.ready && s_xfer_error;
// Capture slave-select one-hot at FSM_SETP for cleaner response mux.
`include "soc_apb_select_routes.svh"
rtl/ip/native/interconnect/nmi2nmi.sv → rtl/ip/rib/interconnect/rib2rib.sv
+1 -1
View File
@@ -8,7 +8,7 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
module nmi2nmi (
module rib2rib (
// mstr
input logic mstr_clk_i,
input logic mstr_rst_n_i,
rtl/ip/rib/interconnect/rib_regslice.sv
+136
View File
@@ -0,0 +1,136 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
module rib_regslice (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib_slv,
rib_if.master rib_mst
// verilog_format: on
);
localparam FSM_IDLE = 2'd0;
localparam FSM_REQ = 2'd1;
localparam FSM_RESP = 2'd2;
logic [1:0] s_fsm_d, s_fsm_q;
logic s_rib_mst_valid_d, s_rib_mst_valid_q;
logic [31:0] s_rib_mst_addr_d, s_rib_mst_addr_q;
logic [31:0] s_rib_mst_wdata_d, s_rib_mst_wdata_q;
logic [3:0] s_rib_mst_wstrb_d, s_rib_mst_wstrb_q;
logic [31:0] s_rib_mst_rdata_d, s_rib_mst_rdata_q;
logic s_rib_mst_ready_d, s_rib_mst_ready_q;
// rib mst if
assign rib_mst.valid = s_rib_mst_valid_q;
assign rib_mst.addr = s_rib_mst_addr_q;
assign rib_mst.wdata = s_rib_mst_wdata_q;
assign rib_mst.wstrb = s_rib_mst_wstrb_q;
always_comb begin
s_fsm_d = s_fsm_q;
s_rib_mst_valid_d = s_rib_mst_valid_q;
s_rib_mst_addr_d = s_rib_mst_addr_q;
s_rib_mst_wdata_d = s_rib_mst_wdata_q;
s_rib_mst_wstrb_d = s_rib_mst_wstrb_q;
s_rib_mst_ready_d = s_rib_mst_ready_q;
s_rib_mst_rdata_d = s_rib_mst_rdata_q;
rib_slv.ready = '0;
rib_slv.rdata = '0;
unique case (s_fsm_q)
FSM_IDLE: begin
if (rib_slv.valid) begin
s_fsm_d = FSM_REQ;
s_rib_mst_valid_d = rib_slv.valid;
s_rib_mst_addr_d = rib_slv.addr;
s_rib_mst_wdata_d = rib_slv.wdata;
s_rib_mst_wstrb_d = rib_slv.wstrb;
end
end
FSM_REQ: begin
if (rib_mst.ready) begin
s_fsm_d = FSM_RESP;
s_rib_mst_valid_d = 1'b0;
s_rib_mst_ready_d = rib_mst.ready;
s_rib_mst_rdata_d = rib_mst.rdata;
end
end
FSM_RESP: begin
s_fsm_d = FSM_IDLE;
rib_slv.ready = s_rib_mst_ready_q;
rib_slv.rdata = s_rib_mst_rdata_q;
end
default: begin
s_fsm_d = s_fsm_q;
s_rib_mst_valid_d = s_rib_mst_valid_q;
s_rib_mst_addr_d = s_rib_mst_addr_q;
s_rib_mst_wdata_d = s_rib_mst_wdata_q;
s_rib_mst_wstrb_d = s_rib_mst_wstrb_q;
s_rib_mst_ready_d = s_rib_mst_ready_q;
s_rib_mst_rdata_d = s_rib_mst_rdata_q;
rib_slv.ready = '0;
rib_slv.rdata = '0;
end
endcase
end
dffr #(2) u_fsm_dffr (
clk_i,
rst_n_i,
s_fsm_d,
s_fsm_q
);
dffr #(1) u_rib_mstr_valid_dffr (
clk_i,
rst_n_i,
s_rib_mst_valid_d,
s_rib_mst_valid_q
);
dffr #(32) u_rib_mst_addr_dffr (
clk_i,
rst_n_i,
s_rib_mst_addr_d,
s_rib_mst_addr_q
);
dffr #(32) u_rib_mst_wdata_dffr (
clk_i,
rst_n_i,
s_rib_mst_wdata_d,
s_rib_mst_wdata_q
);
dffr #(4) u_rib_mst_wstrb_dffr (
clk_i,
rst_n_i,
s_rib_mst_wstrb_d,
s_rib_mst_wstrb_q
);
dffr #(32) u_rib_mst_rdata_dffr (
clk_i,
rst_n_i,
s_rib_mst_rdata_d,
s_rib_mst_rdata_q
);
dffr #(1) u_rib_mst_ready_dffr (
clk_i,
rst_n_i,
s_rib_mst_ready_d,
s_rib_mst_ready_q
);
endmodule
rtl/ip/native/memory/opipsram.sv → rtl/ip/rib/memory/opipsram.sv
+5 -5
View File
@@ -32,11 +32,11 @@ interface opipsram_if ();
);
endinterface
module nmi_opipsram (
module rib_opipsram (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
nmi_if.slave nmi,
rib_if.slave rib,
opipsram_if.dut psram
// verilog_format: on
);
@@ -44,9 +44,9 @@ module nmi_opipsram (
wire dummy0 = clk_i;
wire dummy1 = rst_n_i;
// nmi
assign nmi.rdata = '0;
assign nmi.ready = '0;
// rib
assign rib.rdata = '0;
assign rib.ready = '0;
// psram
assign psram.sck_o = '0;
assign psram.ce_o = '0;
rtl/ip/native/memory/opipsram_core.sv → rtl/ip/rib/memory/opipsram_core.sv
View File
File renamed without changes.
rtl/ip/native/memory/psram.sv → rtl/ip/rib/memory/psram.sv
+36 -36
View File
@@ -36,13 +36,13 @@
// tSP(min: 2ns) is meet
// data keeps 6.94 / 2 = 3.47ns low at least befer sclk
`ifndef NMI_PSRAM_DEF_SV
`define NMI_PSRAM_DEF_SV
`ifndef RIB_PSRAM_DEF_SV
`define RIB_PSRAM_DEF_SV
// verilog_format: off
`define NMI_PSRAM_WAIT 8'h00
`define NMI_PSRAM_CHD 8'h04
`define NMI_PSRAM_INIT 8'h08
`define RIB_PSRAM_WAIT 8'h00
`define RIB_PSRAM_CHD 8'h04
`define RIB_PSRAM_INIT 8'h08
// verilog_format: on
`endif
@@ -69,11 +69,11 @@ interface psram_if ();
endinterface
module nmi_psram (
module rib_psram (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
nmi_if.slave nmi,
rib_if.slave rib,
psram_if.dut psram
// verilog_format: on
);
@@ -113,10 +113,10 @@ module nmi_psram (
// verilog_format: off
assign psram.nss_o[0] = (~s_init_done) || (s_init_done && nmi.addr[24:23] == 2'd0) ? s_psram_ce : 1'b1;
assign psram.nss_o[1] = (~s_init_done) || (s_init_done && nmi.addr[24:23] == 2'd1) ? s_psram_ce : 1'b1;
assign psram.nss_o[2] = (~s_init_done) || (s_init_done && nmi.addr[24:23] == 2'd2) ? s_psram_ce : 1'b1;
assign psram.nss_o[3] = (~s_init_done) || (s_init_done && nmi.addr[24:23] == 2'd3) ? s_psram_ce : 1'b1;
assign psram.nss_o[0] = (~s_init_done) || (s_init_done && rib.addr[24:23] == 2'd0) ? s_psram_ce : 1'b1;
assign psram.nss_o[1] = (~s_init_done) || (s_init_done && rib.addr[24:23] == 2'd1) ? s_psram_ce : 1'b1;
assign psram.nss_o[2] = (~s_init_done) || (s_init_done && rib.addr[24:23] == 2'd2) ? s_psram_ce : 1'b1;
assign psram.nss_o[3] = (~s_init_done) || (s_init_done && rib.addr[24:23] == 2'd3) ? s_psram_ce : 1'b1;
assign psram.io_oe_o[0] = ~s_psram_sio_oen;
assign psram.io_oe_o[1] = ~s_psram_sio_oen;
assign psram.io_oe_o[2] = ~s_psram_sio_oen;
@@ -125,48 +125,48 @@ module nmi_psram (
// verilog_format: on
assign s_mem_sel = `SOC_ADDR_IS_PSRAM(nmi.addr);
assign s_cfg_reg_sel = `SOC_ADDR_IS_NMI_PSRAM(nmi.addr);
assign nmi.ready = s_mem_sel ? s_mem_ready : 1'b1;
assign s_mem_sel = `SOC_ADDR_IS_PSRAM(rib.addr);
assign s_cfg_reg_sel = `SOC_ADDR_IS_RIB_PSRAM(rib.addr);
assign rib.ready = s_mem_sel ? s_mem_ready : 1'b1;
always_comb begin
nmi.rdata = '0;
rib.rdata = '0;
if (s_mem_sel) begin
nmi.rdata = s_mem_rdata;
end else if (nmi.addr[7:0] == `NMI_PSRAM_WAIT) begin
nmi.rdata = {27'd0, r_cfg_wait};
end else if (nmi.addr[7:0] == `NMI_PSRAM_CHD) begin
nmi.rdata = {29'd0, r_cfg_chd};
end else if (nmi.addr[7:0] == `NMI_PSRAM_INIT) begin
nmi.rdata = {31'd0, r_cfg_init};
rib.rdata = s_mem_rdata;
end else if (rib.addr[7:0] == `RIB_PSRAM_WAIT) begin
rib.rdata = {27'd0, r_cfg_wait};
end else if (rib.addr[7:0] == `RIB_PSRAM_CHD) begin
rib.rdata = {29'd0, r_cfg_chd};
end else if (rib.addr[7:0] == `RIB_PSRAM_INIT) begin
rib.rdata = {31'd0, r_cfg_init};
end
end
// wait cycles(mmio)
always_ff @(posedge clk_i, negedge rst_n_i) begin
if (~rst_n_i) r_cfg_wait <= 5'd18;
else if (nmi.valid && nmi.wstrb[0] && s_cfg_reg_sel && nmi.addr[7:0] == `NMI_PSRAM_WAIT) begin
r_cfg_wait <= nmi.wdata[4:0];
else if (rib.valid && rib.wstrb[0] && s_cfg_reg_sel && rib.addr[7:0] == `RIB_PSRAM_WAIT) begin
r_cfg_wait <= rib.wdata[4:0];
end
end
// extra cycle for tCHD(mmio)
always_ff @(posedge clk_i, negedge rst_n_i) begin
if (~rst_n_i) r_cfg_chd <= 3'd4;
else if (nmi.valid && nmi.wstrb[0] && s_cfg_reg_sel && nmi.addr[7:0] == `NMI_PSRAM_CHD) begin
r_cfg_chd <= nmi.wdata[2:0];
else if (rib.valid && rib.wstrb[0] && s_cfg_reg_sel && rib.addr[7:0] == `RIB_PSRAM_CHD) begin
r_cfg_chd <= rib.wdata[2:0];
end
end
// init device/switch qpi mode
always_ff @(posedge clk_i, negedge rst_n_i) begin
if (~rst_n_i) r_cfg_init <= '0;
else if (nmi.valid && nmi.wstrb[0] && s_cfg_reg_sel && nmi.addr[7:0] == `NMI_PSRAM_INIT) begin
r_cfg_init <= nmi.wdata[0];
else if (rib.valid && rib.wstrb[0] && s_cfg_reg_sel && rib.addr[7:0] == `RIB_PSRAM_INIT) begin
r_cfg_init <= rib.wdata[0];
end
end
edge_det_sync_re #(1) u_mem_valid_edge_det_sync_re (
clk_i,
rst_n_i,
nmi.valid,
rib.valid,
s_mem_valid_re
);
@@ -183,16 +183,16 @@ module nmi_psram (
/* verilator lint_off CASEINCOMPLETE */
case (r_fsm_state)
FSM_IDLE: begin
if (s_mem_valid_re && (|nmi.wstrb)) begin
if (s_mem_valid_re && (|rib.wstrb)) begin
r_fsm_state <= FSM_WE_ST;
r_xfer_data_bit_cnt <= s_disp_xfer_bit_cnt;
r_mem_addr <= {1'b0, nmi.addr[22:0]} + {22'd0, s_disp_addr_ofst};
r_mem_addr <= {1'b0, rib.addr[22:0]} + {22'd0, s_disp_addr_ofst};
r_mem_wdata <= s_disp_wdata;
end else if (s_mem_valid_re && (~(|nmi.wstrb))) begin
end else if (s_mem_valid_re && (~(|rib.wstrb))) begin
r_fsm_state <= FSM_RD_ST;
r_xfer_data_bit_cnt <= 8'd32;
r_mem_addr <= {1'b0, nmi.addr[22:0]};
r_mem_wdata <= nmi.wdata; // NOTE: no used
r_mem_addr <= {1'b0, rib.addr[22:0]};
r_mem_wdata <= rib.wdata; // NOTE: no used
end
end
FSM_WE_ST: begin
@@ -248,8 +248,8 @@ module nmi_psram (
);
wr_dispatcher u_wr_dispatcher (
.wstrb_i (nmi.wstrb),
.wdata_i (nmi.wdata),
.wstrb_i (rib.wstrb),
.wdata_i (rib.wdata),
.addr_ofst_o (s_disp_addr_ofst),
.xfer_bit_cnt_o(s_disp_xfer_bit_cnt),
.wdata_o (s_disp_wdata)
rtl/ip/native/memory/psram_core.sv → rtl/ip/rib/memory/psram_core.sv
View File
File renamed without changes.
rtl/ip/native/memory/sdram.sv → rtl/ip/rib/memory/sdram.sv
+20 -20
View File
@@ -42,11 +42,11 @@ interface sdram_if ();
endinterface
module nmi_sdram (
module rib_sdram (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
nmi_if.slave nmi,
rib_if.slave rib,
sdram_if.dut sdram
// verilog_format: on
);
@@ -58,34 +58,34 @@ module nmi_sdram (
logic s_sec_edge;
// interface
nmi_if u_reg_nmi_if ();
nmi_if u_mem_nmi_if ();
rib_if u_reg_rib_if ();
rib_if u_mem_rib_if ();
// nmi mux
assign s_sdram_reg_sel = `SOC_ADDR_IS_NMI_SDRAM(nmi.addr);
assign u_reg_nmi_if.valid = nmi.valid && s_sdram_reg_sel;
assign u_reg_nmi_if.addr = nmi.addr;
assign u_reg_nmi_if.wdata = nmi.wdata;
assign u_reg_nmi_if.wstrb = nmi.wstrb;
// rib mux
assign s_sdram_reg_sel = `SOC_ADDR_IS_RIB_SDRAM(rib.addr);
assign u_reg_rib_if.valid = rib.valid && s_sdram_reg_sel;
assign u_reg_rib_if.addr = rib.addr;
assign u_reg_rib_if.wdata = rib.wdata;
assign u_reg_rib_if.wstrb = rib.wstrb;
assign u_mem_nmi_if.valid = nmi.valid && (~s_sdram_reg_sel);
assign u_mem_nmi_if.addr = nmi.addr;
assign u_mem_nmi_if.wdata = nmi.wdata;
assign u_mem_nmi_if.wstrb = nmi.wstrb;
assign u_mem_rib_if.valid = rib.valid && (~s_sdram_reg_sel);
assign u_mem_rib_if.addr = rib.addr;
assign u_mem_rib_if.wdata = rib.wdata;
assign u_mem_rib_if.wstrb = rib.wstrb;
// verilog_format: off
assign nmi.ready = (u_reg_nmi_if.valid & u_reg_nmi_if.ready) |
(u_mem_nmi_if.valid & u_mem_nmi_if.ready);
assign rib.ready = (u_reg_rib_if.valid & u_reg_rib_if.ready) |
(u_mem_rib_if.valid & u_mem_rib_if.ready);
assign nmi.rdata = ({32{(u_reg_nmi_if.valid & u_reg_nmi_if.ready)}} & u_reg_nmi_if.rdata) |
({32{(u_mem_nmi_if.valid & u_mem_nmi_if.ready)}} & u_mem_nmi_if.rdata);
assign rib.rdata = ({32{(u_reg_rib_if.valid & u_reg_rib_if.ready)}} & u_reg_rib_if.rdata) |
({32{(u_mem_rib_if.valid & u_mem_rib_if.ready)}} & u_mem_rib_if.rdata);
// verilog_format: on
sdram_reg u_sdram_reg (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.nmi (u_reg_nmi_if),
.rib (u_reg_rib_if),
.clkdiv_o(s_sdram_clkdiv)
);
@@ -106,7 +106,7 @@ module nmi_sdram (
.fir_edge_i (s_fir_edge),
.sec_edge_i (s_sec_edge),
.sdram_clk_i(s_sdram_clk),
.nmi (u_mem_nmi_if),
.rib (u_mem_rib_if),
.sdram (sdram)
);
rtl/ip/native/memory/sdram_clkgen.sv → rtl/ip/rib/memory/sdram_clkgen.sv
View File
File renamed without changes.
rtl/ip/native/memory/sdram_core.sv → rtl/ip/rib/memory/sdram_core.sv
+33 -33
View File
@@ -36,7 +36,7 @@ module sdram_core (
input logic sdram_clk_i,
input logic fir_edge_i,
input logic sec_edge_i,
nmi_if.slave nmi,
rib_if.slave rib,
sdram_if.dut sdram
// verilog_format: on
);
@@ -135,15 +135,15 @@ module sdram_core (
logic s_cke_q, s_cke_d;
logic [12:0] s_addr_d, s_addr_q;
logic s_upd_ready_d, s_upd_ready_q;
// Registered NMI inputs (captured at IDLE→ACT)
logic [24:0] s_nmi_addr_d, s_nmi_addr_q; // addr[24:0] (relevant bits)
logic [31:0] s_nmi_wdata_d, s_nmi_wdata_q;
logic [3:0] s_nmi_wstrb_d, s_nmi_wstrb_q;
// Registered RIB inputs (captured at IDLE→ACT)
logic [24:0] s_rib_addr_d, s_rib_addr_q; // addr[24:0] (relevant bits)
logic [31:0] s_rib_wdata_d, s_rib_wdata_q;
logic [3:0] s_rib_wstrb_d, s_rib_wstrb_q;
// nmi
assign nmi.ready = s_ready_q;
assign nmi.rdata = s_rdata_q;
// rib
assign rib.ready = s_ready_q;
assign rib.rdata = s_rdata_q;
// sdram
assign sdram.clk_o = sdram_clk_i;
assign sdram.cke_o = s_cke_q;
@@ -171,9 +171,9 @@ module sdram_core (
s_cke_d = s_cke_q;
s_addr_d = s_addr_q;
s_upd_ready_d = s_upd_ready_q;
s_nmi_addr_d = s_nmi_addr_q;
s_nmi_wdata_d = s_nmi_wdata_q;
s_nmi_wstrb_d = s_nmi_wstrb_q;
s_rib_addr_d = s_rib_addr_q;
s_rib_wdata_d = s_rib_wdata_q;
s_rib_wstrb_d = s_rib_wstrb_q;
case (s_state_q)
RESET: begin
s_cke_d = 1'b0;
@@ -218,16 +218,16 @@ module sdram_core (
s_oe_d = 1'b0;
s_dqm_d = 2'b11;
s_ready_d = 1'b0;
if (nmi.valid && !s_ready_q) begin
// Capture NMI inputs into holding registers
s_nmi_addr_d = nmi.addr[24:0];
s_nmi_wdata_d = nmi.wdata;
s_nmi_wstrb_d = nmi.wstrb;
if (rib.valid && !s_ready_q) begin
// Capture RIB inputs into holding registers
s_rib_addr_d = rib.addr[24:0];
s_rib_wdata_d = rib.wdata;
s_rib_wstrb_d = rib.wstrb;
s_cmd_d = CMD_ACT;
s_ba_d = nmi.addr[22:21];
s_addr_d = {nmi.addr[24:23], nmi.addr[20:10]};
s_ba_d = rib.addr[22:21];
s_addr_d = {rib.addr[24:23], rib.addr[20:10]};
s_state_d = WAIT_STATE;
s_ret_state_d = |nmi.wstrb ? COL_WRITEL : COL_READ;
s_ret_state_d = |rib.wstrb ? COL_WRITEL : COL_READ;
s_wait_cnt_d = 16'(TRCD);
s_upd_ready_d = 1'b1;
end else begin
@@ -246,8 +246,8 @@ module sdram_core (
s_cmd_d = CMD_READ;
s_dqm_d = 2'b00;
// autoprecharge and column (use registered addr)
s_ba_d = s_nmi_addr_q[22:21];
s_addr_d = {3'b001, s_nmi_addr_q[10:2], 1'b0};
s_ba_d = s_rib_addr_q[22:21];
s_addr_d = {3'b001, s_rib_addr_q[10:2], 1'b0};
// $display("rd col addr: %0x", s_addr_d);
s_state_d = WAIT_STATE;
s_ret_state_d = COL_READL;
@@ -269,19 +269,19 @@ module sdram_core (
end
COL_WRITEL: begin
s_cmd_d = CMD_WRITE;
s_dqm_d = ~s_nmi_wstrb_q[1:0];
s_dqm_d = ~s_rib_wstrb_q[1:0];
// autoprecharge and column (use registered addr)
s_ba_d = s_nmi_addr_q[22:21];
s_addr_d = {3'b001, s_nmi_addr_q[10:2], 1'b0};
s_dq_d = s_nmi_wdata_q[15:0];
s_ba_d = s_rib_addr_q[22:21];
s_addr_d = {3'b001, s_rib_addr_q[10:2], 1'b0};
s_dq_d = s_rib_wdata_q[15:0];
s_oe_d = 1'b1;
s_state_d = COL_WRITEH;
end
COL_WRITEH: begin
s_cmd_d = CMD_NOP;
s_dqm_d = ~s_nmi_wstrb_q[3:2];
s_dqm_d = ~s_rib_wstrb_q[3:2];
// autoprecharge and column (use registered wdata)
s_dq_d = s_nmi_wdata_q[31:16];
s_dq_d = s_rib_wdata_q[31:16];
s_oe_d = 1'b1;
s_state_d = WAIT_STATE;
s_ret_state_d = IDLE;
@@ -330,9 +330,9 @@ module sdram_core (
s_cke_q <= '0;
s_addr_q <= '0;
s_upd_ready_q <= '0;
s_nmi_addr_q <= '0;
s_nmi_wdata_q <= '0;
s_nmi_wstrb_q <= '0;
s_rib_addr_q <= '0;
s_rib_wdata_q <= '0;
s_rib_wstrb_q <= '0;
end else begin
s_ready_q <= s_ready_d;
if (fir_edge_i) begin
@@ -351,9 +351,9 @@ module sdram_core (
s_cke_q <= s_cke_d;
s_addr_q <= s_addr_d;
s_upd_ready_q <= s_upd_ready_d;
s_nmi_addr_q <= s_nmi_addr_d;
s_nmi_wdata_q <= s_nmi_wdata_d;
s_nmi_wstrb_q <= s_nmi_wstrb_d;
s_rib_addr_q <= s_rib_addr_d;
s_rib_wdata_q <= s_rib_wdata_d;
s_rib_wstrb_q <= s_rib_wstrb_d;
end
end
end
rtl/ip/native/memory/sdram_reg.sv → rtl/ip/rib/memory/sdram_reg.sv
+31 -31
View File
@@ -8,12 +8,12 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef NMI_SDRAM_DEF_SV
`define NMI_SDRAM_DEF_SV
`ifndef RIB_SDRAM_DEF_SV
`define RIB_SDRAM_DEF_SV
// verilog_format: off
`define NMI_SDRAM_CLKDIV 8'h00
`define NMI_SDRAM_CFG 8'h04
`define RIB_SDRAM_CLKDIV 8'h00
`define RIB_SDRAM_CFG 8'h04
// verilog_format: on
`endif
@@ -22,30 +22,30 @@ module sdram_reg (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
nmi_if.slave nmi,
rib_if.slave rib,
output logic [1:0] clkdiv_o
// verilog_format: on
);
// nmi
logic s_nmi_wr_hdshk, s_nmi_rd_hdshk;
logic s_nmi_ready_d, s_nmi_ready_q;
logic s_nmi_rdata_en;
logic [31:0] s_nmi_rdata_d, s_nmi_rdata_q;
// rib
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
// register
logic s_sdram_clkdiv_en;
logic [1:0] s_sdram_clkdiv_d, s_sdram_clkdiv_q;
// nmi
assign s_nmi_wr_hdshk = nmi.valid && (~s_nmi_ready_q) && (|nmi.wstrb);
assign s_nmi_rd_hdshk = nmi.valid && (~s_nmi_ready_q) && (~(|nmi.wstrb));
assign nmi.ready = s_nmi_ready_q;
assign nmi.rdata = s_nmi_rdata_q;
// rib
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
// reg
assign clkdiv_o = s_sdram_clkdiv_q;
assign s_sdram_clkdiv_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_SDRAM_CLKDIV;
assign s_sdram_clkdiv_d = nmi.wdata[1:0];
assign s_sdram_clkdiv_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_SDRAM_CLKDIV;
assign s_sdram_clkdiv_d = rib.wdata[1:0];
dffer #(2) u_sdram_clkdiv_dffer (
clk_i,
rst_n_i,
@@ -55,30 +55,30 @@ module sdram_reg (
);
// nmi resp
assign s_nmi_ready_d = nmi.valid && (~s_nmi_ready_q);
dffr #(1) u_nmi_ready_dffr (
// rib resp
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
clk_i,
rst_n_i,
s_nmi_ready_d,
s_nmi_ready_q
s_rib_ready_d,
s_rib_ready_q
);
assign s_nmi_rdata_en = s_nmi_rd_hdshk;
assign s_rib_rdata_en = s_rib_rd_hdshk;
always_comb begin
s_nmi_rdata_d = s_nmi_rdata_q;
unique case (nmi.addr[7:0])
`NMI_SDRAM_CLKDIV: s_nmi_rdata_d = {30'd0, s_sdram_clkdiv_q};
default: s_nmi_rdata_d = s_nmi_rdata_q;
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_SDRAM_CLKDIV: s_rib_rdata_d = {30'd0, s_sdram_clkdiv_q};
default: s_rib_rdata_d = s_rib_rdata_q;
endcase
end
dffer #(32) u_nmi_rdata_dffer (
dffer #(32) u_rib_rdata_dffer (
clk_i,
rst_n_i,
s_nmi_rdata_en,
s_nmi_rdata_d,
s_nmi_rdata_q
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
);
endmodule
rtl/ip/native/multimedia/dvp.sv → rtl/ip/rib/multimedia/dvp.sv
+37 -37
View File
@@ -8,12 +8,12 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef NMI_DVP_DEF_SV
`define NMI_DVP_DEF_SV
`ifndef RIB_DVP_DEF_SV
`define RIB_DVP_DEF_SV
`define NMI_DVP_RECVEN 8'h00
`define NMI_DVP_RXDATA 8'h04
`define NMI_DVP_STATUS 8'h08
`define RIB_DVP_RECVEN 8'h00
`define RIB_DVP_RXDATA 8'h04
`define RIB_DVP_STATUS 8'h08
`endif
@@ -26,19 +26,19 @@ interface dvp_if ();
modport dut(input pclk_i, input href_i, input vsync_i, input dat_i);
endinterface
module nmi_dvp (
module rib_dvp (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
nmi_if.slave nmi,
rib_if.slave rib,
dvp_if.dut dvp
// verilog_format: on
);
// nmi
logic s_nmi_wr_hdshk, s_nmi_rd_hdshk;
logic s_nmi_ready_d, s_nmi_ready_q;
logic s_nmi_rdata_en;
logic [31:0] s_nmi_rdata_d, s_nmi_rdata_q;
// rib
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
// register
logic s_dvp_recven_en;
logic s_dvp_recven_d, s_dvp_recven_q;
@@ -53,15 +53,15 @@ module nmi_dvp (
logic [31:0] s_rx_push_data, s_rx_pop_data;
logic [7:0] s_rx_elem_num;
// nmi
assign s_nmi_wr_hdshk = nmi.valid && (~s_nmi_ready_q) && nmi.wstrb[0];
assign s_nmi_rd_hdshk = nmi.valid && (~s_nmi_ready_q) && (~(|nmi.wstrb));
assign nmi.ready = s_nmi_ready_q;
assign nmi.rdata = s_nmi_rdata_q;
// rib
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && rib.wstrb[0];
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
assign s_dvp_recven_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_DVP_RECVEN;
assign s_dvp_recven_d = nmi.wdata[0];
assign s_dvp_recven_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DVP_RECVEN;
assign s_dvp_recven_d = rib.wdata[0];
dffer #(1) u_dvp_recven_dffer (
clk_i,
rst_n_i,
@@ -78,37 +78,37 @@ module nmi_dvp (
s_dvp_status_q
);
assign s_nmi_ready_d = nmi.valid && (~s_nmi_ready_q);
dffr #(1) u_nmi_ready_dffr (
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
clk_i,
rst_n_i,
s_nmi_ready_d,
s_nmi_ready_q
s_rib_ready_d,
s_rib_ready_q
);
assign s_nmi_rdata_en = s_nmi_rd_hdshk;
assign s_rib_rdata_en = s_rib_rd_hdshk;
always_comb begin
s_rx_pop_valid = '0;
s_nmi_rdata_d = s_nmi_rdata_q;
unique case (nmi.addr[7:0])
`NMI_DVP_RECVEN: s_nmi_rdata_d = {31'd0, s_dvp_recven_q};
`NMI_DVP_RXDATA: begin
if (s_nmi_rd_hdshk) begin
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_DVP_RECVEN: s_rib_rdata_d = {31'd0, s_dvp_recven_q};
`RIB_DVP_RXDATA: begin
if (s_rib_rd_hdshk) begin
s_rx_pop_valid = 1'b1;
if (!s_rx_empty) s_nmi_rdata_d = s_rx_pop_data;
else s_nmi_rdata_d = '0;
if (!s_rx_empty) s_rib_rdata_d = s_rx_pop_data;
else s_rib_rdata_d = '0;
end
end
`NMI_DVP_STATUS: s_nmi_rdata_d = {31'd0, s_dvp_status_q};
default: s_nmi_rdata_d = s_nmi_rdata_q;
`RIB_DVP_STATUS: s_rib_rdata_d = {31'd0, s_dvp_status_q};
default: s_rib_rdata_d = s_rib_rdata_q;
endcase
end
dffer #(32) u_nmi_rdata_dffer (
dffer #(32) u_rib_rdata_dffer (
clk_i,
rst_n_i,
s_nmi_rdata_en,
s_nmi_rdata_d,
s_nmi_rdata_q
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
);
rtl/ip/native/multimedia/dvp_core.sv → rtl/ip/rib/multimedia/dvp_core.sv
View File
File renamed without changes.
rtl/ip/native/peripheral/clint.sv → rtl/ip/rib/peripheral/clint.sv
+49 -49
View File
@@ -12,12 +12,12 @@
`define CLINT_DEF_SV
// verilog_format: off
`define NATV_CLINT_MTIMEL 8'h00
`define NATV_CLINT_MTIMEH 8'h04
`define NATV_CLINT_MTIMECMPL 8'h08
`define NATV_CLINT_MTIMECMPH 8'h0C
`define NATV_CLINT_MSIP 8'h10
`define NATV_CLINT_CLKDIV 8'h14
`define RIB_CLINT_MTIMEL 8'h00
`define RIB_CLINT_MTIMEH 8'h04
`define RIB_CLINT_MTIMECMPL 8'h08
`define RIB_CLINT_MTIMECMPH 8'h0C
`define RIB_CLINT_MSIP 8'h10
`define RIB_CLINT_CLKDIV 8'h14
// verilog_format: on
`endif
@@ -29,19 +29,19 @@ interface simp_clint_if ();
modport dut(output tmr_irq_o, output sfr_irq_o);
endinterface
module nmi_clint (
module rib_clint (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
nmi_if.slave nmi,
rib_if.slave rib,
simp_clint_if.dut clint
// verilog_format: on
);
logic s_nmi_wr_hdshk, s_nmi_rd_hdshk;
logic s_nmi_ready_d, s_nmi_ready_q;
logic s_nmi_rdata_en;
logic [31:0] s_nmi_rdata_d, s_nmi_rdata_q;
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
logic s_clint_clkdiv_en;
logic [7:0] s_clint_clkdiv_d, s_clint_clkdiv_q;
@@ -57,10 +57,10 @@ module nmi_clint (
logic s_tmr_hi_gt, s_tmr_hi_eq, s_tmr_lo_ge;
logic s_tmr_irq_d, s_tmr_irq_q;
assign s_nmi_wr_hdshk = nmi.valid && (~s_nmi_ready_q) && (|nmi.wstrb);
assign s_nmi_rd_hdshk = nmi.valid && (~s_nmi_ready_q) && (~(|nmi.wstrb));
assign nmi.ready = s_nmi_ready_q;
assign nmi.rdata = s_nmi_rdata_q;
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
// pipelined 64-bit magnitude compare (registered output)
assign s_tmr_hi_gt = s_clint_mtime_q[63:32] > s_clint_mtimecmp_q[63:32];
@@ -77,8 +77,8 @@ module nmi_clint (
assign clint.sfr_irq_o = s_clint_msip_q;
assign s_clint_clkdiv_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_CLINT_CLKDIV;
assign s_clint_clkdiv_d = nmi.wdata[7:0];
assign s_clint_clkdiv_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_CLINT_CLKDIV;
assign s_clint_clkdiv_d = rib.wdata[7:0];
dffer #(8) u_clint_clkdiv_dffer (
clk_i,
rst_n_i,
@@ -114,19 +114,19 @@ module nmi_clint (
);
assign s_clint_mtimecmp_en = s_nmi_wr_hdshk && (nmi.addr[7:0] == `NATV_CLINT_MTIMECMPL || nmi.addr[7:0] == `NATV_CLINT_MTIMECMPH);
assign s_clint_mtimecmp_en = s_rib_wr_hdshk && (rib.addr[7:0] == `RIB_CLINT_MTIMECMPL || rib.addr[7:0] == `RIB_CLINT_MTIMECMPH);
always_comb begin
s_clint_mtimecmp_d = s_clint_mtimecmp_q;
if (nmi.addr[7:0] == `NATV_CLINT_MTIMECMPL) begin
if (nmi.wstrb[0]) s_clint_mtimecmp_d[7:0] = nmi.wdata[7:0];
if (nmi.wstrb[1]) s_clint_mtimecmp_d[15:8] = nmi.wdata[15:8];
if (nmi.wstrb[2]) s_clint_mtimecmp_d[23:16] = nmi.wdata[23:16];
if (nmi.wstrb[3]) s_clint_mtimecmp_d[31:24] = nmi.wdata[31:24];
end else if (nmi.addr[7:0] == `NATV_CLINT_MTIMECMPH) begin
if (nmi.wstrb[0]) s_clint_mtimecmp_d[39:32] = nmi.wdata[7:0];
if (nmi.wstrb[1]) s_clint_mtimecmp_d[47:40] = nmi.wdata[15:8];
if (nmi.wstrb[2]) s_clint_mtimecmp_d[55:48] = nmi.wdata[23:16];
if (nmi.wstrb[3]) s_clint_mtimecmp_d[63:56] = nmi.wdata[31:24];
if (rib.addr[7:0] == `RIB_CLINT_MTIMECMPL) begin
if (rib.wstrb[0]) s_clint_mtimecmp_d[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_clint_mtimecmp_d[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_clint_mtimecmp_d[23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_clint_mtimecmp_d[31:24] = rib.wdata[31:24];
end else if (rib.addr[7:0] == `RIB_CLINT_MTIMECMPH) begin
if (rib.wstrb[0]) s_clint_mtimecmp_d[39:32] = rib.wdata[7:0];
if (rib.wstrb[1]) s_clint_mtimecmp_d[47:40] = rib.wdata[15:8];
if (rib.wstrb[2]) s_clint_mtimecmp_d[55:48] = rib.wdata[23:16];
if (rib.wstrb[3]) s_clint_mtimecmp_d[63:56] = rib.wdata[31:24];
end
end
dfferh #(64) u_clint_mtimecmp_dfferh (
@@ -138,8 +138,8 @@ module nmi_clint (
);
assign s_clint_msip_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_CLINT_MSIP;
assign s_clint_msip_d = nmi.wdata[0];
assign s_clint_msip_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_CLINT_MSIP;
assign s_clint_msip_d = rib.wdata[0];
dffer #(1) u_clint_msip_dffer (
clk_i,
rst_n_i,
@@ -148,33 +148,33 @@ module nmi_clint (
s_clint_msip_q
);
assign s_nmi_ready_d = nmi.valid && (~s_nmi_ready_q);
dffr #(1) u_nmi_ready_dffr (
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
clk_i,
rst_n_i,
s_nmi_ready_d,
s_nmi_ready_q
s_rib_ready_d,
s_rib_ready_q
);
assign s_nmi_rdata_en = s_nmi_rd_hdshk;
assign s_rib_rdata_en = s_rib_rd_hdshk;
always_comb begin
s_nmi_rdata_d = s_nmi_rdata_q;
unique case (nmi.addr[7:0])
`NATV_CLINT_CLKDIV: s_nmi_rdata_d = {24'd0, s_clint_clkdiv_q};
`NATV_CLINT_MTIMEL: s_nmi_rdata_d = s_clint_mtime_q[31:0];
`NATV_CLINT_MTIMEH: s_nmi_rdata_d = s_clint_mtime_q[63:32];
`NATV_CLINT_MTIMECMPL: s_nmi_rdata_d = s_clint_mtimecmp_q[31:0];
`NATV_CLINT_MTIMECMPH: s_nmi_rdata_d = s_clint_mtimecmp_q[63:32];
`NATV_CLINT_MSIP: s_nmi_rdata_d = {31'd0, s_clint_msip_q};
default: s_nmi_rdata_d = s_nmi_rdata_q;
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_CLINT_CLKDIV: s_rib_rdata_d = {24'd0, s_clint_clkdiv_q};
`RIB_CLINT_MTIMEL: s_rib_rdata_d = s_clint_mtime_q[31:0];
`RIB_CLINT_MTIMEH: s_rib_rdata_d = s_clint_mtime_q[63:32];
`RIB_CLINT_MTIMECMPL: s_rib_rdata_d = s_clint_mtimecmp_q[31:0];
`RIB_CLINT_MTIMECMPH: s_rib_rdata_d = s_clint_mtimecmp_q[63:32];
`RIB_CLINT_MSIP: s_rib_rdata_d = {31'd0, s_clint_msip_q};
default: s_rib_rdata_d = s_rib_rdata_q;
endcase
end
dffer #(32) u_nmi_rdata_dffer (
dffer #(32) u_rib_rdata_dffer (
clk_i,
rst_n_i,
s_nmi_rdata_en,
s_nmi_rdata_d,
s_nmi_rdata_q
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
);
endmodule
rtl/ip/native/peripheral/dma.sv → rtl/ip/rib/peripheral/dma.sv
+76 -76
View File
@@ -8,23 +8,23 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef NATV_DMA_DEF_SV
`define NATV_DMA_DEF_SV
`ifndef RIB_DMA_DEF_SV
`define RIB_DMA_DEF_SV
// verilog_format: off
`define NATV_DMA_MODE 8'h00
`define NATV_DMA_SRCADDR 8'h04
`define NATV_DMA_SRCINCR 8'h08
`define NATV_DMA_DSTADDR 8'h0C
`define NATV_DMA_DSTINCR 8'h10
`define NATV_DMA_XFERLEN 8'h14
`define NATV_DMA_START 8'h18
`define NATV_DMA_STOP 8'h1C
`define NATV_DMA_RESET 8'h20
`define NATV_DMA_STATUS 8'h24
`define NATV_DMA_FSM 8'h28
`define NATV_DMA_ERROR_STATUS 8'h2C
`define NATV_DMA_ERROR_ADDR 8'h30
`define RIB_DMA_MODE 8'h00
`define RIB_DMA_SRCADDR 8'h04
`define RIB_DMA_SRCINCR 8'h08
`define RIB_DMA_DSTADDR 8'h0C
`define RIB_DMA_DSTINCR 8'h10
`define RIB_DMA_XFERLEN 8'h14
`define RIB_DMA_START 8'h18
`define RIB_DMA_STOP 8'h1C
`define RIB_DMA_RESET 8'h20
`define RIB_DMA_STATUS 8'h24
`define RIB_DMA_FSM 8'h28
`define RIB_DMA_ERROR_STATUS 8'h2C
`define RIB_DMA_ERROR_ADDR 8'h30
// verilog_format: on
interface dma_hw_trg_if ();
@@ -38,21 +38,21 @@ endinterface
`endif
module nmi_dma (
module rib_dma (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
output logic dma_xfer_done_o,
dma_hw_trg_if.dut hw_trg,
nmi_if.slave nmi,
soc_nmi_if.master nmi_dma
rib_if.slave rib,
soc_rib_if.master rib_dma
// verilog_format: on
);
logic s_nmi_wr_hdshk, s_nmi_rd_hdshk;
logic s_nmi_ready_d, s_nmi_ready_q;
logic s_nmi_rdata_en;
logic [31:0] s_nmi_rdata_d, s_nmi_rdata_q;
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
logic s_dma_mode_en;
logic [2:0] s_dma_mode_d, s_dma_mode_q;
@@ -78,16 +78,16 @@ module nmi_dma (
logic [31:0] s_xfer_error_addr;
assign s_nmi_wr_hdshk = nmi.valid && (~s_nmi_ready_q) && (|nmi.wstrb);
assign s_nmi_rd_hdshk = nmi.valid && (~s_nmi_ready_q) && (~(|nmi.wstrb));
assign nmi.ready = s_nmi_ready_q;
assign nmi.rdata = s_nmi_rdata_q;
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
assign dma_xfer_done_o = s_dma_status_q;
assign s_dma_mode_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_DMA_MODE;
assign s_dma_mode_d = nmi.wdata[2:0];
assign s_dma_mode_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DMA_MODE;
assign s_dma_mode_d = rib.wdata[2:0];
dffer #(3) u_dma_mode_dffer (
clk_i,
rst_n_i,
@@ -97,13 +97,13 @@ module nmi_dma (
);
assign s_dma_srcaddr_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_DMA_SRCADDR;
assign s_dma_srcaddr_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DMA_SRCADDR;
always_comb begin
s_dma_srcaddr_d = s_dma_srcaddr_q;
if (nmi.wstrb[0]) s_dma_srcaddr_d[7:0] = nmi.wdata[7:0];
if (nmi.wstrb[1]) s_dma_srcaddr_d[15:8] = nmi.wdata[15:8];
if (nmi.wstrb[2]) s_dma_srcaddr_d[23:16] = nmi.wdata[23:16];
if (nmi.wstrb[3]) s_dma_srcaddr_d[31:24] = nmi.wdata[31:24];
if (rib.wstrb[0]) s_dma_srcaddr_d[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_dma_srcaddr_d[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_dma_srcaddr_d[23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_dma_srcaddr_d[31:24] = rib.wdata[31:24];
end
dffer #(32) u_dma_srcaddr_dffer (
clk_i,
@@ -114,8 +114,8 @@ module nmi_dma (
);
assign s_dma_srcincr_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_DMA_SRCINCR;
assign s_dma_srcincr_d = nmi.wdata[0];
assign s_dma_srcincr_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DMA_SRCINCR;
assign s_dma_srcincr_d = rib.wdata[0];
dffer #(1) u_dma_srcincr_dffer (
clk_i,
rst_n_i,
@@ -125,13 +125,13 @@ module nmi_dma (
);
assign s_dma_dstaddr_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_DMA_DSTADDR;
assign s_dma_dstaddr_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DMA_DSTADDR;
always_comb begin
s_dma_dstaddr_d = s_dma_dstaddr_q;
if (nmi.wstrb[0]) s_dma_dstaddr_d[7:0] = nmi.wdata[7:0];
if (nmi.wstrb[1]) s_dma_dstaddr_d[15:8] = nmi.wdata[15:8];
if (nmi.wstrb[2]) s_dma_dstaddr_d[23:16] = nmi.wdata[23:16];
if (nmi.wstrb[3]) s_dma_dstaddr_d[31:24] = nmi.wdata[31:24];
if (rib.wstrb[0]) s_dma_dstaddr_d[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_dma_dstaddr_d[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_dma_dstaddr_d[23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_dma_dstaddr_d[31:24] = rib.wdata[31:24];
end
dffer #(32) u_dma_dstaddr_dffer (
clk_i,
@@ -141,8 +141,8 @@ module nmi_dma (
s_dma_dstaddr_q
);
assign s_dma_dstincr_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_DMA_DSTINCR;
assign s_dma_dstincr_d = nmi.wdata[0];
assign s_dma_dstincr_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DMA_DSTINCR;
assign s_dma_dstincr_d = rib.wdata[0];
dffer #(1) u_dma_dstincr_dffer (
clk_i,
rst_n_i,
@@ -151,13 +151,13 @@ module nmi_dma (
s_dma_dstincr_q
);
assign s_dma_xferlen_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_DMA_XFERLEN;
assign s_dma_xferlen_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DMA_XFERLEN;
always_comb begin
s_dma_xferlen_d = s_dma_xferlen_q;
if (nmi.wstrb[0]) s_dma_xferlen_d[7:0] = nmi.wdata[7:0];
if (nmi.wstrb[1]) s_dma_xferlen_d[15:8] = nmi.wdata[15:8];
if (nmi.wstrb[2]) s_dma_xferlen_d[23:16] = nmi.wdata[23:16];
if (nmi.wstrb[3]) s_dma_xferlen_d[31:24] = nmi.wdata[31:24];
if (rib.wstrb[0]) s_dma_xferlen_d[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_dma_xferlen_d[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_dma_xferlen_d[23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_dma_xferlen_d[31:24] = rib.wdata[31:24];
end
dffer #(32) u_dma_xferlen_dffer (
clk_i,
@@ -168,14 +168,14 @@ module nmi_dma (
);
assign s_xfer_start = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_DMA_START;
assign s_xfer_stop = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_DMA_STOP;
assign s_xfer_reset = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_DMA_RESET;
assign s_xfer_start = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DMA_START;
assign s_xfer_stop = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DMA_STOP;
assign s_xfer_reset = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DMA_RESET;
always_comb begin
s_dma_status_d = s_dma_status_q;
if (s_nmi_rd_hdshk && nmi.addr[7:0] == `NATV_DMA_STATUS) begin
if (s_rib_rd_hdshk && rib.addr[7:0] == `RIB_DMA_STATUS) begin
s_dma_status_d = '0;
end else if (s_xfer_done) begin
s_dma_status_d = 1'b1;
@@ -190,8 +190,8 @@ module nmi_dma (
always_comb begin
s_dma_error_status_d = s_dma_error_status_q;
if (s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_DMA_ERROR_STATUS && nmi.wstrb[0] &&
nmi.wdata[0]) begin
if (s_rib_wr_hdshk && rib.addr[7:0] == `RIB_DMA_ERROR_STATUS && rib.wstrb[0] &&
rib.wdata[0]) begin
s_dma_error_status_d = 1'b0;
end else if (s_xfer_error) begin
s_dma_error_status_d = 1'b1;
@@ -221,37 +221,37 @@ module nmi_dma (
);
assign s_nmi_ready_d = nmi.valid && (~s_nmi_ready_q);
dffr #(1) u_nmi_ready_dffr (
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
clk_i,
rst_n_i,
s_nmi_ready_d,
s_nmi_ready_q
s_rib_ready_d,
s_rib_ready_q
);
assign s_nmi_rdata_en = s_nmi_rd_hdshk;
assign s_rib_rdata_en = s_rib_rd_hdshk;
always_comb begin
s_nmi_rdata_d = s_nmi_rdata_q;
unique case (nmi.addr[7:0])
`NATV_DMA_MODE: s_nmi_rdata_d = {29'd0, s_dma_mode_q};
`NATV_DMA_SRCADDR: s_nmi_rdata_d = s_dma_srcaddr_q;
`NATV_DMA_SRCINCR: s_nmi_rdata_d = {31'd0, s_dma_srcincr_q};
`NATV_DMA_DSTADDR: s_nmi_rdata_d = s_dma_dstaddr_q;
`NATV_DMA_DSTINCR: s_nmi_rdata_d = {31'd0, s_dma_dstincr_q};
`NATV_DMA_XFERLEN: s_nmi_rdata_d = s_dma_xferlen_q;
`NATV_DMA_STATUS: s_nmi_rdata_d = {31'd0, s_dma_status_q};
`NATV_DMA_FSM: s_nmi_rdata_d = {30'd0, s_xfer_fsm};
`NATV_DMA_ERROR_STATUS: s_nmi_rdata_d = {28'd0, s_dma_error_code_q, s_dma_error_status_q};
`NATV_DMA_ERROR_ADDR: s_nmi_rdata_d = s_dma_error_addr_q;
default: s_nmi_rdata_d = s_nmi_rdata_q;
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_DMA_MODE: s_rib_rdata_d = {29'd0, s_dma_mode_q};
`RIB_DMA_SRCADDR: s_rib_rdata_d = s_dma_srcaddr_q;
`RIB_DMA_SRCINCR: s_rib_rdata_d = {31'd0, s_dma_srcincr_q};
`RIB_DMA_DSTADDR: s_rib_rdata_d = s_dma_dstaddr_q;
`RIB_DMA_DSTINCR: s_rib_rdata_d = {31'd0, s_dma_dstincr_q};
`RIB_DMA_XFERLEN: s_rib_rdata_d = s_dma_xferlen_q;
`RIB_DMA_STATUS: s_rib_rdata_d = {31'd0, s_dma_status_q};
`RIB_DMA_FSM: s_rib_rdata_d = {30'd0, s_xfer_fsm};
`RIB_DMA_ERROR_STATUS: s_rib_rdata_d = {28'd0, s_dma_error_code_q, s_dma_error_status_q};
`RIB_DMA_ERROR_ADDR: s_rib_rdata_d = s_dma_error_addr_q;
default: s_rib_rdata_d = s_rib_rdata_q;
endcase
end
dffer #(32) u_nmi_rdata_dffer (
dffer #(32) u_rib_rdata_dffer (
clk_i,
rst_n_i,
s_nmi_rdata_en,
s_nmi_rdata_d,
s_nmi_rdata_q
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
);
@@ -273,7 +273,7 @@ module nmi_dma (
.error_addr_o(s_xfer_error_addr),
.fsm_o (s_xfer_fsm),
.hw_trg (hw_trg),
.nmi (nmi_dma)
.rib (rib_dma)
);
endmodule
rtl/ip/native/peripheral/dma_core.sv → rtl/ip/rib/peripheral/dma_core.sv
+63 -63
View File
@@ -8,7 +8,7 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`include "soc_nmi_defs.svh"
`include "soc_rib_defs.svh"
module dma_core (
// verilog_format: off
@@ -29,7 +29,7 @@ module dma_core (
output logic [31:0] error_addr_o,
output logic [1:0] fsm_o,
dma_hw_trg_if.dut hw_trg,
soc_nmi_if.master nmi
soc_rib_if.master rib
// verilog_format: on
);
@@ -58,17 +58,17 @@ module dma_core (
logic s_xfer_type_d, s_xfer_type_q; // 0: rd 1: wr
logic s_xfer_done_d, s_xfer_done_q;
logic s_ctrl_stop_d, s_ctrl_stop_q;
// Registered NMI master outputs
logic s_nmi_valid_d, s_nmi_valid_q;
logic [31:0] s_nmi_addr_d, s_nmi_addr_q;
logic [31:0] s_nmi_wdata_d, s_nmi_wdata_q;
logic [3:0] s_nmi_wstrb_d, s_nmi_wstrb_q;
// Registered RIB master outputs
logic s_rib_valid_d, s_rib_valid_q;
logic [31:0] s_rib_addr_d, s_rib_addr_q;
logic [31:0] s_rib_wdata_d, s_rib_wdata_q;
logic [3:0] s_rib_wstrb_d, s_rib_wstrb_q;
assign fsm_o = s_fsm_q;
assign nmi.valid = s_nmi_valid_q;
assign nmi.addr = s_nmi_addr_q;
assign nmi.wdata = s_nmi_wdata_q;
assign nmi.wstrb = s_nmi_wstrb_q;
assign rib.valid = s_rib_valid_q;
assign rib.addr = s_rib_addr_q;
assign rib.wdata = s_rib_wdata_q;
assign rib.wstrb = s_rib_wstrb_q;
always_comb begin
s_fsm_d = s_fsm_q;
s_src_addr_d = s_src_addr_q;
@@ -77,16 +77,16 @@ module dma_core (
s_xfer_cnt_d = s_xfer_cnt_q;
s_xfer_type_d = s_xfer_type_q;
s_xfer_done_d = s_xfer_done_q;
// nmi if (registered outputs)
s_nmi_valid_d = '0;
s_nmi_addr_d = s_nmi_addr_q;
s_nmi_wdata_d = s_nmi_wdata_q;
s_nmi_wstrb_d = '0;
// rib if (registered outputs)
s_rib_valid_d = '0;
s_rib_addr_d = s_rib_addr_q;
s_rib_wdata_d = s_rib_wdata_q;
s_rib_wstrb_d = '0;
// common
done_o = '0;
error_o = 1'b0;
error_code_o = `SOC_NMI_RESP_OK;
error_addr_o = s_nmi_addr_q;
error_code_o = `SOC_RIB_RESP_OK;
error_addr_o = s_rib_addr_q;
unique case (s_fsm_q)
FSM_IDLE: begin
if (start_i) begin
@@ -103,51 +103,51 @@ module dma_core (
if (~s_xfer_type_q) begin
unique case (mode_i)
HWT_I2S_RX_TRG: begin
if (~hw_trg.i2s_rx_proc && s_xfer_done_q) s_nmi_valid_d = 1'b0;
else s_nmi_valid_d = 1'b1;
if (~hw_trg.i2s_rx_proc && s_xfer_done_q) s_rib_valid_d = 1'b0;
else s_rib_valid_d = 1'b1;
end
HWT_QSPI_RX_TRG: begin
if (~hw_trg.qspi_rx_proc && s_xfer_done_q) s_nmi_valid_d = 1'b0;
else s_nmi_valid_d = 1'b1;
if (~hw_trg.qspi_rx_proc && s_xfer_done_q) s_rib_valid_d = 1'b0;
else s_rib_valid_d = 1'b1;
end
default: s_nmi_valid_d = 1'b1;
default: s_rib_valid_d = 1'b1;
endcase
s_nmi_addr_d = s_src_addr_q;
if (nmi.valid && nmi.ready) begin
s_nmi_valid_d = 1'b0;
if (nmi.resp_err) begin
s_rib_addr_d = s_src_addr_q;
if (rib.valid && rib.ready) begin
s_rib_valid_d = 1'b0;
if (rib.resp_err) begin
s_fsm_d = FSM_IDLE;
error_o = 1'b1;
error_code_o = nmi.resp_code;
error_code_o = rib.resp_code;
end else begin
s_xfer_type_d = 1'b1;
s_xfer_done_d = 1'b1;
s_rd_data_d = nmi.rdata;
s_rd_data_d = rib.rdata;
end
end else if (nmi.valid) begin
end else if (rib.valid) begin
s_xfer_done_d = 1'b0;
end
end else begin
unique case (mode_i)
HWT_I2S_TX_TRG: begin
if (~hw_trg.i2s_tx_proc && s_xfer_done_q) s_nmi_valid_d = 1'b0;
else s_nmi_valid_d = 1'b1;
if (~hw_trg.i2s_tx_proc && s_xfer_done_q) s_rib_valid_d = 1'b0;
else s_rib_valid_d = 1'b1;
end
HWT_QSPI_TX_TRG: begin
if (~hw_trg.qspi_tx_proc && s_xfer_done_q) s_nmi_valid_d = 1'b0;
else s_nmi_valid_d = 1'b1;
if (~hw_trg.qspi_tx_proc && s_xfer_done_q) s_rib_valid_d = 1'b0;
else s_rib_valid_d = 1'b1;
end
default: s_nmi_valid_d = 1'b1;
default: s_rib_valid_d = 1'b1;
endcase
s_nmi_addr_d = s_dst_addr_q;
s_nmi_wdata_d = s_rd_data_q;
s_nmi_wstrb_d = '1;
if (nmi.valid && nmi.ready) begin
s_nmi_valid_d = 1'b0;
if (nmi.resp_err) begin
s_rib_addr_d = s_dst_addr_q;
s_rib_wdata_d = s_rd_data_q;
s_rib_wstrb_d = '1;
if (rib.valid && rib.ready) begin
s_rib_valid_d = 1'b0;
if (rib.resp_err) begin
s_fsm_d = FSM_IDLE;
error_o = 1'b1;
error_code_o = nmi.resp_code;
error_code_o = rib.resp_code;
end else begin
s_xfer_type_d = 1'b0;
s_xfer_done_d = 1'b1;
@@ -161,7 +161,7 @@ module dma_core (
if (dstincr_i) s_dst_addr_d = s_dst_addr_q + 32'd4;
end
end
end else if (nmi.valid) s_xfer_done_d = 1'b0;
end else if (rib.valid) s_xfer_done_d = 1'b0;
end
end else begin
if (reset_i) s_fsm_d = FSM_IDLE;
@@ -179,16 +179,16 @@ module dma_core (
s_xfer_cnt_d = s_xfer_cnt_q;
s_xfer_type_d = s_xfer_type_q;
s_xfer_done_d = s_xfer_done_q;
// nmi if
s_nmi_valid_d = '0;
s_nmi_addr_d = '0;
s_nmi_wdata_d = '0;
s_nmi_wstrb_d = '0;
// rib if
s_rib_valid_d = '0;
s_rib_addr_d = '0;
s_rib_wdata_d = '0;
s_rib_wstrb_d = '0;
// common
done_o = '0;
error_o = 1'b0;
error_code_o = `SOC_NMI_RESP_OK;
error_addr_o = s_nmi_addr_q;
error_code_o = `SOC_RIB_RESP_OK;
error_addr_o = s_rib_addr_q;
end
endcase
end
@@ -253,30 +253,30 @@ module dma_core (
s_ctrl_stop_q
);
// Registered NMI master outputs
dffr #(1) u_nmi_valid_dffr (
// Registered RIB master outputs
dffr #(1) u_rib_valid_dffr (
clk_i,
rst_n_i,
s_nmi_valid_d,
s_nmi_valid_q
s_rib_valid_d,
s_rib_valid_q
);
dffr #(32) u_nmi_addr_dffr (
dffr #(32) u_rib_addr_dffr (
clk_i,
rst_n_i,
s_nmi_addr_d,
s_nmi_addr_q
s_rib_addr_d,
s_rib_addr_q
);
dffr #(32) u_nmi_wdata_dffr (
dffr #(32) u_rib_wdata_dffr (
clk_i,
rst_n_i,
s_nmi_wdata_d,
s_nmi_wdata_q
s_rib_wdata_d,
s_rib_wdata_q
);
dffr #(4) u_nmi_wstrb_dffr (
dffr #(4) u_rib_wstrb_dffr (
clk_i,
rst_n_i,
s_nmi_wstrb_d,
s_nmi_wstrb_q
s_rib_wstrb_d,
s_rib_wstrb_q
);
endmodule
rtl/ip/native/peripheral/gpio.sv → rtl/ip/rib/peripheral/gpio.sv
+106 -106
View File
@@ -32,7 +32,7 @@
`include "gpio_define.svh"
interface gpio_if #(
parameter int DATA_WIDTH = `NMI_GPIO_NUM
parameter int DATA_WIDTH = `RIB_GPIO_NUM
) ();
logic [DATA_WIDTH-1:0] oe_o;
logic [DATA_WIDTH-1:0] cs_o;
@@ -66,7 +66,7 @@ interface gpio_if #(
endinterface
interface user_gpio_if #(
parameter int DATA_WIDTH = `NMI_GPIO_NUM
parameter int DATA_WIDTH = `RIB_GPIO_NUM
) ();
logic [DATA_WIDTH-1:0] do_o;
logic [DATA_WIDTH-1:0] oe_o;
@@ -76,80 +76,80 @@ interface user_gpio_if #(
modport padctrl(input do_o, input oe_o, output di_i);
endinterface
module nmi_gpio (
module rib_gpio (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
nmi_if.slave nmi,
rib_if.slave rib,
gpio_if.dut gpio,
user_gpio_if.padctrl user_gpio
// verilog_format: on
);
// nmi
logic s_nmi_wr_hdshk, s_nmi_rd_hdshk;
logic s_nmi_ready_d, s_nmi_ready_q;
logic s_nmi_rdata_en;
logic [31:0] s_nmi_rdata_d, s_nmi_rdata_q;
// rib
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
// reg
logic s_gpio_oe_en;
logic [`NMI_GPIO_NUM-1:0] s_gpio_oe_d, s_gpio_oe_q;
logic [`RIB_GPIO_NUM-1:0] s_gpio_oe_d, s_gpio_oe_q;
logic s_gpio_cs_en;
logic [`NMI_GPIO_NUM-1:0] s_gpio_cs_d, s_gpio_cs_q;
logic [`RIB_GPIO_NUM-1:0] s_gpio_cs_d, s_gpio_cs_q;
logic s_gpio_pu_en;
logic [`NMI_GPIO_NUM-1:0] s_gpio_pu_d, s_gpio_pu_q;
logic [`RIB_GPIO_NUM-1:0] s_gpio_pu_d, s_gpio_pu_q;
logic s_gpio_pd_en;
logic [`NMI_GPIO_NUM-1:0] s_gpio_pd_d, s_gpio_pd_q;
logic [`RIB_GPIO_NUM-1:0] s_gpio_pd_d, s_gpio_pd_q;
logic s_gpio_do_en;
logic [`NMI_GPIO_NUM-1:0] s_gpio_do_d, s_gpio_do_q;
logic [`NMI_GPIO_NUM-1:0] s_gpio_di;
logic [`RIB_GPIO_NUM-1:0] s_gpio_do_d, s_gpio_do_q;
logic [`RIB_GPIO_NUM-1:0] s_gpio_di;
logic s_gpio_ien_en;
logic [`NMI_GPIO_NUM-1:0] s_gpio_ien_d, s_gpio_ien_q;
logic [`RIB_GPIO_NUM-1:0] s_gpio_ien_d, s_gpio_ien_q;
logic s_gpio_itype0_en;
logic [`NMI_GPIO_NUM-1:0] s_gpio_itype0_d, s_gpio_itype0_q;
logic [`RIB_GPIO_NUM-1:0] s_gpio_itype0_d, s_gpio_itype0_q;
logic s_gpio_itype1_en;
logic [`NMI_GPIO_NUM-1:0] s_gpio_itype1_d, s_gpio_itype1_q;
logic [`RIB_GPIO_NUM-1:0] s_gpio_itype1_d, s_gpio_itype1_q;
logic s_gpio_istat_en;
logic [`NMI_GPIO_NUM-1:0] s_gpio_istat_d, s_gpio_istat_q;
logic [`RIB_GPIO_NUM-1:0] s_gpio_istat_d, s_gpio_istat_q;
logic s_gpio_iofcfg_en;
logic [`NMI_GPIO_NUM-1:0] s_gpio_iofcfg_d, s_gpio_iofcfg_q;
logic [`RIB_GPIO_NUM-1:0] s_gpio_iofcfg_d, s_gpio_iofcfg_q;
logic s_gpio_pinmux_en;
logic [`NMI_GPIO_NUM-1:0] s_gpio_pinmux_d, s_gpio_pinmux_q;
logic [`RIB_GPIO_NUM-1:0] s_gpio_pinmux_d, s_gpio_pinmux_q;
logic s_gpio_user_sel_en;
logic [`NMI_GPIO_NUM-1:0] s_gpio_user_sel_d, s_gpio_user_sel_q;
logic [`RIB_GPIO_NUM-1:0] s_gpio_user_sel_d, s_gpio_user_sel_q;
logic s_gpio_user_lock_en;
logic [`NMI_GPIO_NUM-1:0] s_gpio_user_lock_d, s_gpio_user_lock_q;
logic [`NMI_GPIO_NUM-1:0] s_gpio_user_handoff_d, s_gpio_user_handoff_q;
logic [`NMI_GPIO_NUM-1:0] s_gpio_user_status;
logic [`RIB_GPIO_NUM-1:0] s_gpio_user_lock_d, s_gpio_user_lock_q;
logic [`RIB_GPIO_NUM-1:0] s_gpio_user_handoff_d, s_gpio_user_handoff_q;
logic [`RIB_GPIO_NUM-1:0] s_gpio_user_status;
// irq
logic [`NMI_GPIO_NUM-1:0] s_gpio_di_re, s_gpio_di_fe, s_gpio_irq;
logic [`NMI_GPIO_NUM-1:0] s_irq_rise, s_irq_fall;
logic [`NMI_GPIO_NUM-1:0] s_irq_lev0, s_irq_lev1;
logic [`NMI_GPIO_NUM-1:0] s_irq_masked;
logic [`RIB_GPIO_NUM-1:0] s_gpio_di_re, s_gpio_di_fe, s_gpio_irq;
logic [`RIB_GPIO_NUM-1:0] s_irq_rise, s_irq_fall;
logic [`RIB_GPIO_NUM-1:0] s_irq_lev0, s_irq_lev1;
logic [`RIB_GPIO_NUM-1:0] s_irq_masked;
logic s_irq_trg, s_irq_stat;
// alt
logic [`NMI_GPIO_NUM-1:0] s_gpio_alt_out, s_gpio_alt_oe;
logic [`NMI_GPIO_NUM-1:0] s_gpio_native_out, s_gpio_native_oe;
logic [`RIB_GPIO_NUM-1:0] s_gpio_alt_out, s_gpio_alt_oe;
logic [`RIB_GPIO_NUM-1:0] s_gpio_native_out, s_gpio_native_oe;
// shake
assign s_nmi_wr_hdshk = nmi.valid && (~s_nmi_ready_q) && (|nmi.wstrb);
assign s_nmi_rd_hdshk = nmi.valid && (~s_nmi_ready_q) && (~(|nmi.wstrb));
assign nmi.ready = s_nmi_ready_q;
assign nmi.rdata = s_nmi_rdata_q;
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
// gpio
assign gpio.cs_o = s_gpio_cs_q; // 1: CMOS 0: SCHMI
assign gpio.pu_o = s_gpio_pu_q;
assign gpio.pd_o = s_gpio_pd_q;
for (genvar i = 0; i < `NMI_GPIO_NUM; i++) begin : ALT_PINMUX_BLOCK
for (genvar i = 0; i < `RIB_GPIO_NUM; i++) begin : ALT_PINMUX_BLOCK
assign s_gpio_alt_oe[i] = s_gpio_pinmux_q[i] ? gpio.alt1_oe_i[i] : gpio.alt0_oe_i[i];
assign s_gpio_alt_out[i] = s_gpio_pinmux_q[i] ? gpio.alt1_do_i[i] : gpio.alt0_do_i[i];
end
for (genvar i = 0; i < `NMI_GPIO_NUM; i++) begin : IOF_PINMUX_BLOCK
for (genvar i = 0; i < `RIB_GPIO_NUM; i++) begin : IOF_PINMUX_BLOCK
assign s_gpio_native_oe[i] = s_gpio_iofcfg_q[i] ? s_gpio_alt_oe[i] : s_gpio_oe_q[i];
assign s_gpio_native_out[i] = s_gpio_iofcfg_q[i] ? s_gpio_alt_out[i] : s_gpio_do_q[i];
end
assign user_gpio.di_i = gpio.di_i;
for (genvar i = 0; i < `NMI_GPIO_NUM; i++) begin : USER_GPIO_MUX_BLOCK
for (genvar i = 0; i < `RIB_GPIO_NUM; i++) begin : USER_GPIO_MUX_BLOCK
assign gpio.oe_o[i] = s_gpio_user_handoff_q[i]
? 1'b0
: (s_gpio_user_sel_q[i] ? user_gpio.oe_o[i] : s_gpio_native_oe[i]);
@@ -171,7 +171,7 @@ module nmi_gpio (
edge_det #(
.STAGE (2),
.DATA_WIDTH(`NMI_GPIO_NUM)
.DATA_WIDTH(`RIB_GPIO_NUM)
) u_gpio_di_edge_det (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
@@ -182,9 +182,9 @@ module nmi_gpio (
);
// register
assign s_gpio_oe_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_GPIO_OE;
assign s_gpio_oe_d = nmi.wdata[`NMI_GPIO_NUM-1:0];
dffer #(`NMI_GPIO_NUM) u_gpio_oe_dffer (
assign s_gpio_oe_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_OE;
assign s_gpio_oe_d = rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_oe_dffer (
clk_i,
rst_n_i,
s_gpio_oe_en,
@@ -193,9 +193,9 @@ module nmi_gpio (
);
assign s_gpio_cs_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_GPIO_CS;
assign s_gpio_cs_d = nmi.wdata[`NMI_GPIO_NUM-1:0];
dffer #(`NMI_GPIO_NUM) u_gpio_cs_dffer (
assign s_gpio_cs_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_CS;
assign s_gpio_cs_d = rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_cs_dffer (
clk_i,
rst_n_i,
s_gpio_cs_en,
@@ -204,9 +204,9 @@ module nmi_gpio (
);
assign s_gpio_pu_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_GPIO_PU;
assign s_gpio_pu_d = nmi.wdata[`NMI_GPIO_NUM-1:0];
dffer #(`NMI_GPIO_NUM) u_gpio_pu_dffer (
assign s_gpio_pu_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_PU;
assign s_gpio_pu_d = rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_pu_dffer (
clk_i,
rst_n_i,
s_gpio_pu_en,
@@ -215,9 +215,9 @@ module nmi_gpio (
);
assign s_gpio_pd_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_GPIO_PD;
assign s_gpio_pd_d = nmi.wdata[`NMI_GPIO_NUM-1:0];
dffer #(`NMI_GPIO_NUM) u_gpio_pd_dffer (
assign s_gpio_pd_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_PD;
assign s_gpio_pd_d = rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_pd_dffer (
clk_i,
rst_n_i,
s_gpio_pd_en,
@@ -226,9 +226,9 @@ module nmi_gpio (
);
assign s_gpio_do_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_GPIO_DO;
assign s_gpio_do_d = nmi.wdata[`NMI_GPIO_NUM-1:0];
dffer #(`NMI_GPIO_NUM) u_gpio_do_dffer (
assign s_gpio_do_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_DO;
assign s_gpio_do_d = rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_do_dffer (
clk_i,
rst_n_i,
s_gpio_do_en,
@@ -237,9 +237,9 @@ module nmi_gpio (
);
assign s_gpio_ien_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_GPIO_IEN;
assign s_gpio_ien_d = nmi.wdata[`NMI_GPIO_NUM-1:0];
dffer #(`NMI_GPIO_NUM) u_gpio_ien_dffer (
assign s_gpio_ien_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_IEN;
assign s_gpio_ien_d = rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_ien_dffer (
clk_i,
rst_n_i,
s_gpio_ien_en,
@@ -248,9 +248,9 @@ module nmi_gpio (
);
assign s_gpio_itype0_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_GPIO_ITYPE0;
assign s_gpio_itype0_d = nmi.wdata[`NMI_GPIO_NUM-1:0];
dffer #(`NMI_GPIO_NUM) u_gpio_itype0_dffer (
assign s_gpio_itype0_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_ITYPE0;
assign s_gpio_itype0_d = rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_itype0_dffer (
clk_i,
rst_n_i,
s_gpio_itype0_en,
@@ -259,9 +259,9 @@ module nmi_gpio (
);
assign s_gpio_itype1_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_GPIO_ITYPE1;
assign s_gpio_itype1_d = nmi.wdata[`NMI_GPIO_NUM-1:0];
dffer #(`NMI_GPIO_NUM) u_gpio_itype1_dffer (
assign s_gpio_itype1_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_ITYPE1;
assign s_gpio_itype1_d = rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_itype1_dffer (
clk_i,
rst_n_i,
s_gpio_itype1_en,
@@ -270,9 +270,9 @@ module nmi_gpio (
);
assign s_gpio_iofcfg_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_GPIO_IOFCFG;
assign s_gpio_iofcfg_d = nmi.wdata[`NMI_GPIO_NUM-1:0];
dffer #(`NMI_GPIO_NUM) u_gpio_iocfg_dffer (
assign s_gpio_iofcfg_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_IOFCFG;
assign s_gpio_iofcfg_d = rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_iocfg_dffer (
clk_i,
rst_n_i,
s_gpio_iofcfg_en,
@@ -284,7 +284,7 @@ module nmi_gpio (
always_comb begin
s_gpio_istat_en = 1'b0;
s_gpio_istat_d = s_gpio_istat_q;
if (s_irq_stat && s_nmi_rd_hdshk && nmi.addr[7:0] == `NMI_GPIO_ISTAT) begin
if (s_irq_stat && s_rib_rd_hdshk && rib.addr[7:0] == `RIB_GPIO_ISTAT) begin
s_gpio_istat_en = 1'b1;
// HACK: clear all irq
s_gpio_istat_d = '0;
@@ -293,7 +293,7 @@ module nmi_gpio (
s_gpio_istat_d = s_irq_masked;
end
end
dffer #(`NMI_GPIO_NUM) u_gpio_istat_dffer (
dffer #(`RIB_GPIO_NUM) u_gpio_istat_dffer (
clk_i,
rst_n_i,
s_gpio_istat_en,
@@ -302,9 +302,9 @@ module nmi_gpio (
);
assign s_gpio_pinmux_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_GPIO_PINMUX;
assign s_gpio_pinmux_d = nmi.wdata[`NMI_GPIO_NUM-1:0];
dffer #(`NMI_GPIO_NUM) u_gpio_pinmux_dffer (
assign s_gpio_pinmux_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_PINMUX;
assign s_gpio_pinmux_d = rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_pinmux_dffer (
clk_i,
rst_n_i,
s_gpio_pinmux_en,
@@ -312,10 +312,10 @@ module nmi_gpio (
s_gpio_pinmux_q
);
assign s_gpio_user_sel_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_GPIO_USER_SEL;
assign s_gpio_user_sel_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_USER_SEL;
assign s_gpio_user_sel_d = (s_gpio_user_sel_q & s_gpio_user_lock_q) |
(nmi.wdata[`NMI_GPIO_NUM-1:0] & ~s_gpio_user_lock_q);
dffer #(`NMI_GPIO_NUM) u_gpio_user_sel_dffer (
(rib.wdata[`RIB_GPIO_NUM-1:0] & ~s_gpio_user_lock_q);
dffer #(`RIB_GPIO_NUM) u_gpio_user_sel_dffer (
clk_i,
rst_n_i,
s_gpio_user_sel_en,
@@ -323,9 +323,9 @@ module nmi_gpio (
s_gpio_user_sel_q
);
assign s_gpio_user_lock_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_GPIO_USER_LOCK;
assign s_gpio_user_lock_d = s_gpio_user_lock_q | nmi.wdata[`NMI_GPIO_NUM-1:0];
dffer #(`NMI_GPIO_NUM) u_gpio_user_lock_dffer (
assign s_gpio_user_lock_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_GPIO_USER_LOCK;
assign s_gpio_user_lock_d = s_gpio_user_lock_q | rib.wdata[`RIB_GPIO_NUM-1:0];
dffer #(`RIB_GPIO_NUM) u_gpio_user_lock_dffer (
clk_i,
rst_n_i,
s_gpio_user_lock_en,
@@ -334,7 +334,7 @@ module nmi_gpio (
);
assign s_gpio_user_handoff_d = s_gpio_user_sel_en ? (s_gpio_user_sel_d ^ s_gpio_user_sel_q) : '0;
dffr #(`NMI_GPIO_NUM) u_gpio_user_handoff_dffr (
dffr #(`RIB_GPIO_NUM) u_gpio_user_handoff_dffr (
clk_i,
rst_n_i,
s_gpio_user_handoff_d,
@@ -343,43 +343,43 @@ module nmi_gpio (
assign s_gpio_user_status = s_gpio_user_sel_q & ~s_gpio_user_handoff_q;
// nmi resp
assign s_nmi_ready_d = nmi.valid && (~s_nmi_ready_q);
dffr #(1) u_nmi_ready_dffr (
// rib resp
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
clk_i,
rst_n_i,
s_nmi_ready_d,
s_nmi_ready_q
s_rib_ready_d,
s_rib_ready_q
);
assign s_nmi_rdata_en = s_nmi_rd_hdshk;
assign s_rib_rdata_en = s_rib_rd_hdshk;
always_comb begin
s_nmi_rdata_d = s_nmi_rdata_q;
unique case (nmi.addr[7:0])
`NMI_GPIO_OE: s_nmi_rdata_d = {{(32 - `NMI_GPIO_NUM) {1'b0}}, s_gpio_oe_q};
`NMI_GPIO_CS: s_nmi_rdata_d = {{(32 - `NMI_GPIO_NUM) {1'b0}}, s_gpio_cs_q};
`NMI_GPIO_PU: s_nmi_rdata_d = {{(32 - `NMI_GPIO_NUM) {1'b0}}, s_gpio_pu_q};
`NMI_GPIO_PD: s_nmi_rdata_d = {{(32 - `NMI_GPIO_NUM) {1'b0}}, s_gpio_pd_q};
`NMI_GPIO_DO: s_nmi_rdata_d = {{(32 - `NMI_GPIO_NUM) {1'b0}}, s_gpio_do_q};
`NMI_GPIO_DI: s_nmi_rdata_d = {{(32 - `NMI_GPIO_NUM) {1'b0}}, s_gpio_di};
`NMI_GPIO_IEN: s_nmi_rdata_d = {{(32 - `NMI_GPIO_NUM) {1'b0}}, s_gpio_ien_q};
`NMI_GPIO_ITYPE0: s_nmi_rdata_d = {{(32 - `NMI_GPIO_NUM) {1'b0}}, s_gpio_itype0_q};
`NMI_GPIO_ITYPE1: s_nmi_rdata_d = {{(32 - `NMI_GPIO_NUM) {1'b0}}, s_gpio_itype1_q};
`NMI_GPIO_ISTAT: s_nmi_rdata_d = {{(32 - `NMI_GPIO_NUM) {1'b0}}, s_gpio_istat_q};
`NMI_GPIO_IOFCFG: s_nmi_rdata_d = {{(32 - `NMI_GPIO_NUM) {1'b0}}, s_gpio_iofcfg_q};
`NMI_GPIO_PINMUX: s_nmi_rdata_d = {{(32 - `NMI_GPIO_NUM) {1'b0}}, s_gpio_pinmux_q};
`NMI_GPIO_USER_SEL: s_nmi_rdata_d = {{(32 - `NMI_GPIO_NUM) {1'b0}}, s_gpio_user_sel_q};
`NMI_GPIO_USER_LOCK: s_nmi_rdata_d = {{(32 - `NMI_GPIO_NUM) {1'b0}}, s_gpio_user_lock_q};
`NMI_GPIO_USER_STATUS: s_nmi_rdata_d = {{(32 - `NMI_GPIO_NUM) {1'b0}}, s_gpio_user_status};
default: s_nmi_rdata_d = s_nmi_rdata_q;
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_GPIO_OE: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_oe_q};
`RIB_GPIO_CS: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_cs_q};
`RIB_GPIO_PU: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_pu_q};
`RIB_GPIO_PD: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_pd_q};
`RIB_GPIO_DO: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_do_q};
`RIB_GPIO_DI: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_di};
`RIB_GPIO_IEN: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_ien_q};
`RIB_GPIO_ITYPE0: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_itype0_q};
`RIB_GPIO_ITYPE1: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_itype1_q};
`RIB_GPIO_ISTAT: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_istat_q};
`RIB_GPIO_IOFCFG: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_iofcfg_q};
`RIB_GPIO_PINMUX: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_pinmux_q};
`RIB_GPIO_USER_SEL: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_user_sel_q};
`RIB_GPIO_USER_LOCK: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_user_lock_q};
`RIB_GPIO_USER_STATUS: s_rib_rdata_d = {{(32 - `RIB_GPIO_NUM) {1'b0}}, s_gpio_user_status};
default: s_rib_rdata_d = s_rib_rdata_q;
endcase
end
dffer #(32) u_nmi_rdata_dffer (
dffer #(32) u_rib_rdata_dffer (
clk_i,
rst_n_i,
s_nmi_rdata_en,
s_nmi_rdata_d,
s_nmi_rdata_q
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
);
endmodule
rtl/ip/rib/peripheral/gpio_define.svh
+32
View File
@@ -0,0 +1,32 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIB_GPIO_DEF_SV
`define RIB_GPIO_DEF_SV
// verilog_format: off
`define RIB_GPIO_NUM 32
`define RIB_GPIO_OE 8'h00 // rw
`define RIB_GPIO_CS 8'h04 // rw
`define RIB_GPIO_PU 8'h08 // rw
`define RIB_GPIO_PD 8'h0C // rw
`define RIB_GPIO_DO 8'h10 // rw
`define RIB_GPIO_DI 8'h14 // ro
`define RIB_GPIO_IEN 8'h18 // rw
`define RIB_GPIO_ITYPE0 8'h1c // rw
`define RIB_GPIO_ITYPE1 8'h20 // rw
`define RIB_GPIO_ISTAT 8'h24 // ro
`define RIB_GPIO_IOFCFG 8'h28 // rw
`define RIB_GPIO_PINMUX 8'h2c // rw
`define RIB_GPIO_USER_SEL 8'h30 // rw
`define RIB_GPIO_USER_LOCK 8'h34 // rw1s
`define RIB_GPIO_USER_STATUS 8'h38 // ro
// verilog_format: on
`endif
rtl/ip/native/peripheral/pll_ctrl_if.sv → rtl/ip/rib/peripheral/pll_ctrl_if.sv
View File
File renamed without changes.
rtl/ip/native/peripheral/sysctrl.sv → rtl/ip/rib/peripheral/sysctrl.sv
+93 -93
View File
@@ -10,7 +10,7 @@
`include "user_extensions.svh"
`include "mmap_define.svh"
`include "soc_nmi_defs.svh"
`include "soc_rib_defs.svh"
interface sysctrl_if ();
logic [`USER_CORESEL_WIDTH-1:0] core_sel_o;
@@ -25,7 +25,7 @@ interface sysctrl_if ();
logic [ 63:0] perf_mgmt_wait_i;
logic [ 63:0] perf_user_wait_i;
logic [ 63:0] perf_dma_wait_i;
logic [ 63:0] perf_natv_wait_i;
logic [ 63:0] perf_rib_wait_i;
logic [ 63:0] perf_apb_wait_i;
logic [ 63:0] perf_sdram_wait_i;
logic [ 63:0] perf_psram_wait_i;
@@ -40,7 +40,7 @@ interface sysctrl_if ();
input perf_mgmt_wait_i,
input perf_user_wait_i,
input perf_dma_wait_i,
input perf_natv_wait_i,
input perf_rib_wait_i,
input perf_apb_wait_i,
input perf_sdram_wait_i,
input perf_psram_wait_i,
@@ -54,7 +54,7 @@ interface sysctrl_if ();
);
endinterface
module nmi_sysctrl (
module rib_sysctrl (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
@@ -62,7 +62,7 @@ module nmi_sysctrl (
input logic [31:0] fault_addr_i,
input logic [3:0] fault_wstrb_i,
input logic fault_reserved_i,
nmi_if.slave nmi,
rib_if.slave rib,
sysctrl_if.dut sysctrl,
pll_ctrl_if.sysctrl pll_ctrl
// verilog_format: on
@@ -99,10 +99,10 @@ module nmi_sysctrl (
sysctrl_offset_t'(`SOC_SYSCTRL_PERF_DMA_WAIT_LO_OFFSET);
localparam sysctrl_offset_t SYSCTRL_PERF_DMA_WAIT_HI_OFFSET =
sysctrl_offset_t'(`SOC_SYSCTRL_PERF_DMA_WAIT_HI_OFFSET);
localparam sysctrl_offset_t SYSCTRL_PERF_NATV_WAIT_LO_OFFSET =
sysctrl_offset_t'(`SOC_SYSCTRL_PERF_NATV_WAIT_LO_OFFSET);
localparam sysctrl_offset_t SYSCTRL_PERF_NATV_WAIT_HI_OFFSET =
sysctrl_offset_t'(`SOC_SYSCTRL_PERF_NATV_WAIT_HI_OFFSET);
localparam sysctrl_offset_t SYSCTRL_PERF_RIB_WAIT_LO_OFFSET =
sysctrl_offset_t'(`SOC_SYSCTRL_PERF_RIB_WAIT_LO_OFFSET);
localparam sysctrl_offset_t SYSCTRL_PERF_RIB_WAIT_HI_OFFSET =
sysctrl_offset_t'(`SOC_SYSCTRL_PERF_RIB_WAIT_HI_OFFSET);
localparam sysctrl_offset_t SYSCTRL_PERF_APB_WAIT_LO_OFFSET =
sysctrl_offset_t'(`SOC_SYSCTRL_PERF_APB_WAIT_LO_OFFSET);
localparam sysctrl_offset_t SYSCTRL_PERF_APB_WAIT_HI_OFFSET =
@@ -120,10 +120,10 @@ module nmi_sysctrl (
localparam sysctrl_offset_t SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET =
sysctrl_offset_t'(`SOC_SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET);
logic s_nmi_wr_hdshk, s_nmi_rd_hdshk;
logic s_nmi_ready_d, s_nmi_ready_q;
logic s_nmi_rdata_en;
logic [31:0] s_nmi_rdata_d, s_nmi_rdata_q;
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
logic [`USER_CORESEL_WIDTH-1:0] s_sysctrl_coresel_d, s_sysctrl_coresel_q;
logic s_sysctrl_coresel_en;
@@ -163,16 +163,16 @@ module nmi_sysctrl (
logic [63:0] s_perf_mgmt_wait_q;
logic [63:0] s_perf_user_wait_q;
logic [63:0] s_perf_dma_wait_q;
logic [63:0] s_perf_natv_wait_q;
logic [63:0] s_perf_rib_wait_q;
logic [63:0] s_perf_apb_wait_q;
logic [63:0] s_perf_sdram_wait_q;
logic [63:0] s_perf_psram_wait_q;
logic [63:0] s_perf_flash_wait_q;
assign s_nmi_wr_hdshk = nmi.valid && (~s_nmi_ready_q) && (|nmi.wstrb);
assign s_nmi_rd_hdshk = nmi.valid && (~s_nmi_ready_q) && (~(|nmi.wstrb));
assign nmi.ready = s_nmi_ready_q;
assign nmi.rdata = s_nmi_rdata_q;
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
assign sysctrl.ip_sel_o = s_sysctrl_ipsel_q;
assign sysctrl.core_sel_o = s_sysctrl_coresel_q;
@@ -184,11 +184,11 @@ module nmi_sysctrl (
assign pll_ctrl.req_valid_o = s_pll_req_valid_q;
assign pll_ctrl.rsp_ready_o = 1'b1;
assign s_sysctrl_coresel_write_valid = nmi.wdata[`USER_CORESEL_WIDTH-1:0] < `USER_CORE_COUNT;
assign s_sysctrl_coresel_en = s_nmi_wr_hdshk && nmi.addr[7:0] == SYSCTRL_CORESEL_OFFSET &&
nmi.wstrb[0] && s_sysctrl_coresel_write_valid &&
assign s_sysctrl_coresel_write_valid = rib.wdata[`USER_CORESEL_WIDTH-1:0] < `USER_CORE_COUNT;
assign s_sysctrl_coresel_en = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_CORESEL_OFFSET &&
rib.wstrb[0] && s_sysctrl_coresel_write_valid &&
(&s_user_reset_q) && sysctrl.user_bus_idle_i && ~s_user_running_q;
assign s_sysctrl_coresel_d = nmi.wdata[`USER_CORESEL_WIDTH-1:0];
assign s_sysctrl_coresel_d = rib.wdata[`USER_CORESEL_WIDTH-1:0];
dffer #(`USER_CORESEL_WIDTH) u_sysctrl_coresel_dffer (
clk_i,
rst_n_i,
@@ -197,15 +197,15 @@ module nmi_sysctrl (
s_sysctrl_coresel_q
);
assign s_user_reset_write_data = nmi.wdata[`USER_CORE_COUNT-1:0];
assign s_user_reset_write_data = rib.wdata[`USER_CORE_COUNT-1:0];
assign s_user_reset_write_legal = (&s_user_reset_write_data) ||
((s_sysctrl_coresel_q < `USER_CORE_COUNT) &&
((~s_user_reset_write_data) ==
({{(`USER_CORE_COUNT - 1){1'b0}}, 1'b1} << s_sysctrl_coresel_q)));
assign s_user_reset_en = s_nmi_wr_hdshk && nmi.addr[7:0] == SYSCTRL_USER_CORE_RESET_OFFSET &&
nmi.wstrb[0];
assign s_user_config_error_clear = s_nmi_wr_hdshk &&
nmi.addr[7:0] == SYSCTRL_USER_CORE_STATUS_OFFSET && nmi.wstrb[1] && nmi.wdata[11];
assign s_user_reset_en = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_USER_CORE_RESET_OFFSET &&
rib.wstrb[0];
assign s_user_config_error_clear = s_rib_wr_hdshk &&
rib.addr[7:0] == SYSCTRL_USER_CORE_STATUS_OFFSET && rib.wstrb[1] && rib.wdata[11];
always_comb begin
s_user_reset_d = s_user_reset_q;
@@ -215,7 +215,7 @@ module nmi_sysctrl (
if (s_user_config_error_clear) begin
s_user_config_error_d = 1'b0;
end
if (s_nmi_wr_hdshk && nmi.addr[7:0] == SYSCTRL_CORESEL_OFFSET && ~s_sysctrl_coresel_en) begin
if (s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_CORESEL_OFFSET && ~s_sysctrl_coresel_en) begin
s_user_config_error_d = 1'b1;
end
if (s_user_reset_en) begin
@@ -267,8 +267,8 @@ module nmi_sysctrl (
s_user_config_error_q
);
assign s_sysctrl_ipsel_en = s_nmi_wr_hdshk && nmi.addr[7:0] == SYSCTRL_IPSEL_OFFSET;
assign s_sysctrl_ipsel_d = nmi.wdata[`USER_IPSEL_WIDTH-1:0];
assign s_sysctrl_ipsel_en = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_IPSEL_OFFSET;
assign s_sysctrl_ipsel_d = rib.wdata[`USER_IPSEL_WIDTH-1:0];
dffer #(`USER_IPSEL_WIDTH) u_sysctrl_ipsel_dffer (
clk_i,
rst_n_i,
@@ -277,8 +277,8 @@ module nmi_sysctrl (
s_sysctrl_ipsel_q
);
assign s_pll_cfg_en = s_nmi_wr_hdshk && nmi.addr[7:0] == SYSCTRL_PLL_CFG_OFFSET && nmi.wstrb[0];
assign s_pll_cfg_d = nmi.wdata[2:0];
assign s_pll_cfg_en = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_PLL_CFG_OFFSET && rib.wstrb[0];
assign s_pll_cfg_d = rib.wdata[2:0];
dffer #(3) u_pll_cfg_dffer (
clk_i,
rst_n_i,
@@ -287,10 +287,10 @@ module nmi_sysctrl (
s_pll_cfg_q
);
assign s_pll_apply = s_nmi_wr_hdshk && nmi.addr[7:0] == SYSCTRL_PLL_CMD_OFFSET &&
nmi.wstrb[0] && nmi.wdata[0];
assign s_pll_clear_error = s_nmi_wr_hdshk && nmi.addr[7:0] == SYSCTRL_PLL_CMD_OFFSET &&
nmi.wstrb[0] && nmi.wdata[1];
assign s_pll_apply = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_PLL_CMD_OFFSET &&
rib.wstrb[0] && rib.wdata[0];
assign s_pll_clear_error = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_PLL_CMD_OFFSET &&
rib.wstrb[0] && rib.wdata[1];
assign s_pll_rsp_accept = pll_ctrl.rsp_valid_i && pll_ctrl.rsp_ready_o;
always_comb begin
@@ -382,11 +382,11 @@ module nmi_sysctrl (
s_pll_lock_q
);
assign s_perf_enable_en = s_nmi_wr_hdshk && nmi.addr[7:0] == SYSCTRL_PERF_CTRL_OFFSET &&
nmi.wstrb[0];
assign s_perf_enable_d = nmi.wdata[0];
assign s_perf_clear = s_perf_enable_en && nmi.wdata[1];
assign s_perf_snapshot = s_perf_enable_en && nmi.wdata[2];
assign s_perf_enable_en = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_PERF_CTRL_OFFSET &&
rib.wstrb[0];
assign s_perf_enable_d = rib.wdata[0];
assign s_perf_clear = s_perf_enable_en && rib.wdata[1];
assign s_perf_snapshot = s_perf_enable_en && rib.wdata[2];
dffer #(1) u_perf_enable_dffer (
clk_i,
rst_n_i,
@@ -415,12 +415,12 @@ module nmi_sysctrl (
sysctrl.perf_dma_wait_i,
s_perf_dma_wait_q
);
dffer #(64) u_perf_natv_wait_dffer (
dffer #(64) u_perf_rib_wait_dffer (
clk_i,
rst_n_i,
s_perf_snapshot,
sysctrl.perf_natv_wait_i,
s_perf_natv_wait_q
sysctrl.perf_rib_wait_i,
s_perf_rib_wait_q
);
dffer #(64) u_perf_apb_wait_dffer (
clk_i,
@@ -451,9 +451,9 @@ module nmi_sysctrl (
s_perf_flash_wait_q
);
assign s_fault_status_clear = s_nmi_wr_hdshk &&
nmi.addr[7:0] == SYSCTRL_FAULT_STATUS_OFFSET &&
nmi.wstrb[0] && nmi.wdata[0];
assign s_fault_status_clear = s_rib_wr_hdshk &&
rib.addr[7:0] == SYSCTRL_FAULT_STATUS_OFFSET &&
rib.wstrb[0] && rib.wdata[0];
always_comb begin
s_fault_pending_d = s_fault_pending_q;
s_fault_write_d = s_fault_write_q;
@@ -469,13 +469,13 @@ module nmi_sysctrl (
if (~s_fault_pending_q || s_fault_status_clear) begin
s_fault_write_d = |fault_wstrb_i;
s_fault_detail_d = |sysctrl.fault_code_i ? sysctrl.fault_code_i :
sysctrl.fault_access_i ? `SOC_NMI_RESP_PROTERR :
fault_reserved_i ? `SOC_NMI_RESP_RESERVED : `SOC_NMI_RESP_DECERR;
sysctrl.fault_access_i ? `SOC_RIB_RESP_PROTERR :
fault_reserved_i ? `SOC_RIB_RESP_RESERVED : `SOC_RIB_RESP_DECERR;
unique case (s_fault_detail_d)
`SOC_NMI_RESP_RESERVED: s_fault_reason_d = 3'd2;
`SOC_NMI_RESP_PROTERR: s_fault_reason_d = 3'd3;
`SOC_NMI_RESP_SLVERR: s_fault_reason_d = 3'd4;
`SOC_NMI_RESP_TIMEOUT: s_fault_reason_d = 3'd5;
`SOC_RIB_RESP_RESERVED: s_fault_reason_d = 3'd2;
`SOC_RIB_RESP_PROTERR: s_fault_reason_d = 3'd3;
`SOC_RIB_RESP_SLVERR: s_fault_reason_d = 3'd4;
`SOC_RIB_RESP_TIMEOUT: s_fault_reason_d = 3'd5;
default: s_fault_reason_d = 3'd1;
endcase
s_fault_addr_d = fault_addr_i;
@@ -534,26 +534,26 @@ module nmi_sysctrl (
s_fault_master_q
);
assign s_nmi_ready_d = nmi.valid && (~s_nmi_ready_q);
dffr #(1) u_nmi_ready_dffr (
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
clk_i,
rst_n_i,
s_nmi_ready_d,
s_nmi_ready_q
s_rib_ready_d,
s_rib_ready_q
);
assign s_nmi_rdata_en = s_nmi_rd_hdshk;
assign s_rib_rdata_en = s_rib_rd_hdshk;
always_comb begin
s_nmi_rdata_d = s_nmi_rdata_q;
unique case (nmi.addr[7:0])
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
// verilog_format: off
SYSCTRL_CORESEL_OFFSET: s_nmi_rdata_d = {{(32 - `USER_CORESEL_WIDTH) {1'b0}}, s_sysctrl_coresel_q};
SYSCTRL_IPSEL_OFFSET: s_nmi_rdata_d = {{(32 - `USER_IPSEL_WIDTH) {1'b0}}, s_sysctrl_ipsel_q};
SYSCTRL_PLL_CFG_OFFSET: s_nmi_rdata_d = {29'd0, s_pll_cfg_q};
SYSCTRL_FAULT_STATUS_OFFSET: s_nmi_rdata_d = {27'd0, s_fault_reason_q, s_fault_write_q, s_fault_pending_q};
SYSCTRL_FAULT_ADDR_OFFSET: s_nmi_rdata_d = s_fault_addr_q;
SYSCTRL_FAULT_COUNT_OFFSET: s_nmi_rdata_d = s_fault_count_q;
SYSCTRL_PLL_STATUS_OFFSET: s_nmi_rdata_d = {
SYSCTRL_CORESEL_OFFSET: s_rib_rdata_d = {{(32 - `USER_CORESEL_WIDTH) {1'b0}}, s_sysctrl_coresel_q};
SYSCTRL_IPSEL_OFFSET: s_rib_rdata_d = {{(32 - `USER_IPSEL_WIDTH) {1'b0}}, s_sysctrl_ipsel_q};
SYSCTRL_PLL_CFG_OFFSET: s_rib_rdata_d = {29'd0, s_pll_cfg_q};
SYSCTRL_FAULT_STATUS_OFFSET: s_rib_rdata_d = {27'd0, s_fault_reason_q, s_fault_write_q, s_fault_pending_q};
SYSCTRL_FAULT_ADDR_OFFSET: s_rib_rdata_d = s_fault_addr_q;
SYSCTRL_FAULT_COUNT_OFFSET: s_rib_rdata_d = s_fault_count_q;
SYSCTRL_PLL_STATUS_OFFSET: s_rib_rdata_d = {
21'd0,
pll_ctrl.capable_i,
s_pll_lock_q,
@@ -564,8 +564,8 @@ module nmi_sysctrl (
s_pll_active_valid_q,
s_pll_active_sel_q
};
SYSCTRL_USER_CORE_RESET_OFFSET: s_nmi_rdata_d = {{(32 - `USER_CORE_COUNT) {1'b0}}, s_user_reset_q};
SYSCTRL_USER_CORE_STATUS_OFFSET: s_nmi_rdata_d = {
SYSCTRL_USER_CORE_RESET_OFFSET: s_rib_rdata_d = {{(32 - `USER_CORE_COUNT) {1'b0}}, s_user_reset_q};
SYSCTRL_USER_CORE_STATUS_OFFSET: s_rib_rdata_d = {
20'd0,
s_user_config_error_q,
s_user_draining_q,
@@ -574,35 +574,35 @@ module nmi_sysctrl (
{ (8 - `USER_CORESEL_WIDTH) {1'b0} },
s_sysctrl_coresel_q
};
SYSCTRL_FAULT_MASTER_OFFSET: s_nmi_rdata_d = {30'd0, s_fault_master_q};
SYSCTRL_FAULT_DETAIL_OFFSET: s_nmi_rdata_d = {29'd0, s_fault_detail_q};
SYSCTRL_PERF_CTRL_OFFSET: s_nmi_rdata_d = {31'd0, s_perf_enable_q};
SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET: s_nmi_rdata_d = s_perf_mgmt_wait_q[31:0];
SYSCTRL_PERF_MGMT_WAIT_HI_OFFSET: s_nmi_rdata_d = s_perf_mgmt_wait_q[63:32];
SYSCTRL_PERF_USER_WAIT_LO_OFFSET: s_nmi_rdata_d = s_perf_user_wait_q[31:0];
SYSCTRL_PERF_USER_WAIT_HI_OFFSET: s_nmi_rdata_d = s_perf_user_wait_q[63:32];
SYSCTRL_PERF_DMA_WAIT_LO_OFFSET: s_nmi_rdata_d = s_perf_dma_wait_q[31:0];
SYSCTRL_PERF_DMA_WAIT_HI_OFFSET: s_nmi_rdata_d = s_perf_dma_wait_q[63:32];
SYSCTRL_PERF_NATV_WAIT_LO_OFFSET: s_nmi_rdata_d = s_perf_natv_wait_q[31:0];
SYSCTRL_PERF_NATV_WAIT_HI_OFFSET: s_nmi_rdata_d = s_perf_natv_wait_q[63:32];
SYSCTRL_PERF_APB_WAIT_LO_OFFSET: s_nmi_rdata_d = s_perf_apb_wait_q[31:0];
SYSCTRL_PERF_APB_WAIT_HI_OFFSET: s_nmi_rdata_d = s_perf_apb_wait_q[63:32];
SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET: s_nmi_rdata_d = s_perf_sdram_wait_q[31:0];
SYSCTRL_PERF_SDRAM_WAIT_HI_OFFSET: s_nmi_rdata_d = s_perf_sdram_wait_q[63:32];
SYSCTRL_PERF_PSRAM_WAIT_LO_OFFSET: s_nmi_rdata_d = s_perf_psram_wait_q[31:0];
SYSCTRL_PERF_PSRAM_WAIT_HI_OFFSET: s_nmi_rdata_d = s_perf_psram_wait_q[63:32];
SYSCTRL_PERF_FLASH_WAIT_LO_OFFSET: s_nmi_rdata_d = s_perf_flash_wait_q[31:0];
SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET: s_nmi_rdata_d = s_perf_flash_wait_q[63:32];
default: s_nmi_rdata_d = s_nmi_rdata_q;
SYSCTRL_FAULT_MASTER_OFFSET: s_rib_rdata_d = {30'd0, s_fault_master_q};
SYSCTRL_FAULT_DETAIL_OFFSET: s_rib_rdata_d = {29'd0, s_fault_detail_q};
SYSCTRL_PERF_CTRL_OFFSET: s_rib_rdata_d = {31'd0, s_perf_enable_q};
SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_mgmt_wait_q[31:0];
SYSCTRL_PERF_MGMT_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_mgmt_wait_q[63:32];
SYSCTRL_PERF_USER_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_user_wait_q[31:0];
SYSCTRL_PERF_USER_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_user_wait_q[63:32];
SYSCTRL_PERF_DMA_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_dma_wait_q[31:0];
SYSCTRL_PERF_DMA_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_dma_wait_q[63:32];
SYSCTRL_PERF_RIB_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_rib_wait_q[31:0];
SYSCTRL_PERF_RIB_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_rib_wait_q[63:32];
SYSCTRL_PERF_APB_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_apb_wait_q[31:0];
SYSCTRL_PERF_APB_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_apb_wait_q[63:32];
SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_sdram_wait_q[31:0];
SYSCTRL_PERF_SDRAM_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_sdram_wait_q[63:32];
SYSCTRL_PERF_PSRAM_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_psram_wait_q[31:0];
SYSCTRL_PERF_PSRAM_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_psram_wait_q[63:32];
SYSCTRL_PERF_FLASH_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_flash_wait_q[31:0];
SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_flash_wait_q[63:32];
default: s_rib_rdata_d = s_rib_rdata_q;
endcase
// verilog_format: on
end
dffer #(32) u_nmi_rdata_dffer (
dffer #(32) u_rib_rdata_dffer (
clk_i,
rst_n_i,
s_nmi_rdata_en,
s_nmi_rdata_d,
s_nmi_rdata_q
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
);
endmodule
rtl/ip/native/peripheral/timer.sv → rtl/ip/rib/peripheral/timer.sv
+44 -44
View File
@@ -30,32 +30,32 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef NMI_TIMER_DEF_SV
`define NMI_TIMER_DEF_SV
`ifndef RIB_TIMER_DEF_SV
`define RIB_TIMER_DEF_SV
// verilog_format: off
`define NMI_TIMER_CFG 8'h00
`define NMI_TIMER_RLD 8'h04
`define NMI_TIMER_VAL 8'h08
`define RIB_TIMER_CFG 8'h00
`define RIB_TIMER_RLD 8'h04
`define RIB_TIMER_VAL 8'h08
// verilog_format: on
`endif
module nmi_timer (
module rib_timer (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
nmi_if.slave nmi,
rib_if.slave rib,
output logic irq_o
// verilog_format: on
);
// nmi
// rib
logic s_irq_d, s_irq_q;
logic s_nmi_wr_hdshk, s_nmi_rd_hdshk;
logic s_nmi_ready_d, s_nmi_ready_q;
logic s_nmi_rdata_en;
logic [31:0] s_nmi_rdata_d, s_nmi_rdata_q;
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
// register
logic s_tim_cfg_en;
logic [3:0] s_tim_cfg_d, s_tim_cfg_q;
@@ -71,10 +71,10 @@ module nmi_timer (
// irq
assign irq_o = s_irq_q;
assign s_nmi_wr_hdshk = nmi.valid && (~s_nmi_ready_q) && (|nmi.wstrb);
assign s_nmi_rd_hdshk = nmi.valid && (~s_nmi_ready_q) && (~(|nmi.wstrb));
assign nmi.ready = s_nmi_ready_q;
assign nmi.rdata = s_nmi_rdata_q;
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
assign s_bit_en = s_tim_cfg_q[0];
assign s_bit_oneshot = s_tim_cfg_q[1];
@@ -82,24 +82,24 @@ module nmi_timer (
assign s_bit_irq_en = s_tim_cfg_q[3];
// register
assign s_tim_cfg_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_TIMER_CFG;
assign s_tim_cfg_d = nmi.wdata[3:0];
assign s_tim_cfg_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_TIMER_CFG;
assign s_tim_cfg_d = rib.wdata[3:0];
dffer #(4) u_tim_cfg_dffer (
clk_i,
rst_n_i,
s_tim_cfg_en && nmi.wstrb[0],
s_tim_cfg_en && rib.wstrb[0],
s_tim_cfg_d,
s_tim_cfg_q
);
assign s_tim_rld_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_TIMER_RLD;
assign s_tim_rld_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_TIMER_RLD;
always_comb begin
s_tim_rld_d = s_tim_rld_q;
if (nmi.wstrb[0]) s_tim_rld_d[7:0] = nmi.wdata[7:0];
if (nmi.wstrb[1]) s_tim_rld_d[15:8] = nmi.wdata[15:8];
if (nmi.wstrb[2]) s_tim_rld_d[23:16] = nmi.wdata[23:16];
if (nmi.wstrb[3]) s_tim_rld_d[31:24] = nmi.wdata[31:24];
if (rib.wstrb[0]) s_tim_rld_d[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_tim_rld_d[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_tim_rld_d[23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_tim_rld_d[31:24] = rib.wdata[31:24];
end
dffer #(32) u_tim_rld_dffer (
clk_i,
@@ -113,11 +113,11 @@ module nmi_timer (
always_comb begin
s_tim_val_d = s_tim_val_q;
s_irq_d = s_irq_q;
if (s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_TIMER_VAL) begin
if (nmi.wstrb[0]) s_tim_val_d[7:0] = nmi.wdata[7:0];
if (nmi.wstrb[1]) s_tim_val_d[15:8] = nmi.wdata[15:8];
if (nmi.wstrb[2]) s_tim_val_d[23:16] = nmi.wdata[23:16];
if (nmi.wstrb[3]) s_tim_val_d[31:24] = nmi.wdata[31:24];
if (s_rib_wr_hdshk && rib.addr[7:0] == `RIB_TIMER_VAL) begin
if (rib.wstrb[0]) s_tim_val_d[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_tim_val_d[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_tim_val_d[23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_tim_val_d[31:24] = rib.wdata[31:24];
end else if (s_bit_en) begin
if (s_bit_updown) begin
if (s_tim_val_q == s_tim_rld_q) begin
@@ -153,30 +153,30 @@ module nmi_timer (
);
assign s_nmi_ready_d = nmi.valid && (~s_nmi_ready_q);
dffr #(1) u_nmi_ready_dffr (
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
clk_i,
rst_n_i,
s_nmi_ready_d,
s_nmi_ready_q
s_rib_ready_d,
s_rib_ready_q
);
assign s_nmi_rdata_en = s_nmi_rd_hdshk;
assign s_rib_rdata_en = s_rib_rd_hdshk;
always_comb begin
s_nmi_rdata_d = s_nmi_rdata_q;
unique case (nmi.addr[7:0])
`NMI_TIMER_CFG: s_nmi_rdata_d = {28'd0, s_tim_cfg_q};
`NMI_TIMER_RLD: s_nmi_rdata_d = s_tim_rld_q;
`NMI_TIMER_VAL: s_nmi_rdata_d = s_tim_val_q;
default: s_nmi_rdata_d = s_nmi_rdata_q;
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_TIMER_CFG: s_rib_rdata_d = {28'd0, s_tim_cfg_q};
`RIB_TIMER_RLD: s_rib_rdata_d = s_tim_rld_q;
`RIB_TIMER_VAL: s_rib_rdata_d = s_tim_val_q;
default: s_rib_rdata_d = s_rib_rdata_q;
endcase
end
dffer #(32) u_nmi_rdata_dffer (
dffer #(32) u_rib_rdata_dffer (
clk_i,
rst_n_i,
s_nmi_rdata_en,
s_nmi_rdata_d,
s_nmi_rdata_q
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
);
endmodule
rtl/ip/native/serial/i2c.sv → rtl/ip/rib/serial/i2c.sv
+54 -54
View File
@@ -8,35 +8,35 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef NATV_I2C_DEF_SV
`define NATV_I2C_DEF_SV
`ifndef RIB_I2C_DEF_SV
`define RIB_I2C_DEF_SV
// verilog_format: off
`define NATV_I2C_CLKDIV 8'h00
`define NATV_I2C_DEVADDR 8'h04
`define NATV_I2C_REGADDR 8'h08
`define NATV_I2C_TXDATA 8'h0C
`define NATV_I2C_RXDATA 8'h10
`define NATV_I2C_XFER 8'h14
`define NATV_I2C_CFG 8'h18
`define NATV_I2C_STATUS 8'h1C
`define RIB_I2C_CLKDIV 8'h00
`define RIB_I2C_DEVADDR 8'h04
`define RIB_I2C_REGADDR 8'h08
`define RIB_I2C_TXDATA 8'h0C
`define RIB_I2C_RXDATA 8'h10
`define RIB_I2C_XFER 8'h14
`define RIB_I2C_CFG 8'h18
`define RIB_I2C_STATUS 8'h1C
// verilog_format: on
`endif
module nmi_i2c (
module rib_i2c (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
nmi_if.slave nmi,
rib_if.slave rib,
i2c_if.dut i2c
// verilog_format: on
);
logic s_nmi_wr_hdshk, s_nmi_rd_hdshk;
logic s_nmi_ready_d, s_nmi_ready_q;
logic s_nmi_rdata_en;
logic [31:0] s_nmi_rdata_d, s_nmi_rdata_q;
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
//2^7=128
logic s_i2c_clkdiv_en;
@@ -63,14 +63,14 @@ module nmi_i2c (
assign s_bit_start = s_i2c_xfer_q[1];
assign s_bit_extn_addr = s_i2c_cfg_q;
assign s_nmi_wr_hdshk = nmi.valid && (~s_nmi_ready_q) && (|nmi.wstrb);
assign s_nmi_rd_hdshk = nmi.valid && (~s_nmi_ready_q) && (~(|nmi.wstrb));
assign nmi.ready = s_nmi_ready_q;
assign nmi.rdata = s_nmi_rdata_q;
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
assign s_i2c_clkdiv_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_I2C_CLKDIV;
assign s_i2c_clkdiv_d = nmi.wdata[6:0];
assign s_i2c_clkdiv_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2C_CLKDIV;
assign s_i2c_clkdiv_d = rib.wdata[6:0];
dffer #(7) u_i2c_clkdiv_dffer (
clk_i,
rst_n_i,
@@ -79,8 +79,8 @@ module nmi_i2c (
s_i2c_clkdiv_q
);
assign s_i2c_devaddr_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_I2C_DEVADDR;
assign s_i2c_devaddr_d = nmi.wdata[6:0];
assign s_i2c_devaddr_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2C_DEVADDR;
assign s_i2c_devaddr_d = rib.wdata[6:0];
dffer #(7) u_i2c_devaddr_dffer (
clk_i,
rst_n_i,
@@ -90,11 +90,11 @@ module nmi_i2c (
);
assign s_i2c_regaddr_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_I2C_REGADDR;
assign s_i2c_regaddr_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2C_REGADDR;
always_comb begin
s_i2c_regaddr_d = s_i2c_regaddr_q;
if (nmi.wstrb[0]) s_i2c_regaddr_d[7:0] = nmi.wdata[7:0];
if (nmi.wstrb[1]) s_i2c_regaddr_d[15:8] = nmi.wdata[15:8];
if (rib.wstrb[0]) s_i2c_regaddr_d[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_i2c_regaddr_d[15:8] = rib.wdata[15:8];
end
dffer #(16) u_i2c_regaddr_dffer (
clk_i,
@@ -105,8 +105,8 @@ module nmi_i2c (
);
assign s_i2c_txdata_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_I2C_TXDATA;
assign s_i2c_txdata_d = nmi.wdata[7:0];
assign s_i2c_txdata_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2C_TXDATA;
assign s_i2c_txdata_d = rib.wdata[7:0];
dffer #(8) u_i2c_txdata_dffer (
clk_i,
rst_n_i,
@@ -118,8 +118,8 @@ module nmi_i2c (
always_comb begin
s_i2c_xfer_d = s_i2c_xfer_q;
if (s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_I2C_XFER) begin
s_i2c_xfer_d = nmi.wdata[1:0];
if (s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2C_XFER) begin
s_i2c_xfer_d = rib.wdata[1:0];
end else if (s_oper_clk_pos && (|s_i2c_xfer_q)) begin
s_i2c_xfer_d = '0;
end
@@ -132,8 +132,8 @@ module nmi_i2c (
);
assign s_i2c_cfg_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_I2C_CFG;
assign s_i2c_cfg_d = nmi.wdata[0];
assign s_i2c_cfg_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2C_CFG;
assign s_i2c_cfg_d = rib.wdata[0];
dffer #(1) u_i2c_cfg_dffer (
clk_i,
rst_n_i,
@@ -152,7 +152,7 @@ module nmi_i2c (
always_comb begin
s_i2c_status_d = s_i2c_status_q;
if (s_bit_end_re) s_i2c_status_d = 1'b1;
else if (s_nmi_rd_hdshk && nmi.addr[7:0] == `NATV_I2C_STATUS) begin
else if (s_rib_rd_hdshk && rib.addr[7:0] == `RIB_I2C_STATUS) begin
s_i2c_status_d = 1'b0;
end
end
@@ -164,35 +164,35 @@ module nmi_i2c (
);
assign s_nmi_ready_d = nmi.valid && (~s_nmi_ready_q);
dffr #(1) u_nmi_ready_dffr (
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
clk_i,
rst_n_i,
s_nmi_ready_d,
s_nmi_ready_q
s_rib_ready_d,
s_rib_ready_q
);
assign s_nmi_rdata_en = s_nmi_rd_hdshk;
assign s_rib_rdata_en = s_rib_rd_hdshk;
always_comb begin
s_nmi_rdata_d = s_nmi_rdata_q;
unique case (nmi.addr[7:0])
`NATV_I2C_CLKDIV: s_nmi_rdata_d = {25'd0, s_i2c_clkdiv_q};
`NATV_I2C_DEVADDR: s_nmi_rdata_d = {25'd0, s_i2c_devaddr_q};
`NATV_I2C_REGADDR: s_nmi_rdata_d = {16'd0, s_i2c_regaddr_q};
`NATV_I2C_TXDATA: s_nmi_rdata_d = {24'd0, s_i2c_txdata_q};
`NATV_I2C_RXDATA: s_nmi_rdata_d = {24'd0, s_i2c_rxdata};
`NATV_I2C_XFER: s_nmi_rdata_d = {30'd0, s_i2c_xfer_q};
`NATV_I2C_CFG: s_nmi_rdata_d = {31'd0, s_i2c_cfg_q};
`NATV_I2C_STATUS: s_nmi_rdata_d = {31'd0, s_i2c_status_q};
default: s_nmi_rdata_d = s_nmi_rdata_q;
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_I2C_CLKDIV: s_rib_rdata_d = {25'd0, s_i2c_clkdiv_q};
`RIB_I2C_DEVADDR: s_rib_rdata_d = {25'd0, s_i2c_devaddr_q};
`RIB_I2C_REGADDR: s_rib_rdata_d = {16'd0, s_i2c_regaddr_q};
`RIB_I2C_TXDATA: s_rib_rdata_d = {24'd0, s_i2c_txdata_q};
`RIB_I2C_RXDATA: s_rib_rdata_d = {24'd0, s_i2c_rxdata};
`RIB_I2C_XFER: s_rib_rdata_d = {30'd0, s_i2c_xfer_q};
`RIB_I2C_CFG: s_rib_rdata_d = {31'd0, s_i2c_cfg_q};
`RIB_I2C_STATUS: s_rib_rdata_d = {31'd0, s_i2c_status_q};
default: s_rib_rdata_d = s_rib_rdata_q;
endcase
end
dffer #(32) u_nmi_rdata_dffer (
dffer #(32) u_rib_rdata_dffer (
clk_i,
rst_n_i,
s_nmi_rdata_en,
s_nmi_rdata_d,
s_nmi_rdata_q
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
);
rtl/ip/native/serial/i2c_core.sv → rtl/ip/rib/serial/i2c_core.sv
View File
File renamed without changes.
rtl/ip/native/serial/i2s.sv → rtl/ip/rib/serial/i2s.sv
+3 -3
View File
@@ -29,7 +29,7 @@ interface i2s_if ();
endinterface
module nmi_i2s (
module rib_i2s (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
@@ -37,7 +37,7 @@ module nmi_i2s (
input logic rst_aud_n_i,
output logic dma_tx_stall_o,
output logic dma_rx_stall_o,
nmi_if.slave nmi,
rib_if.slave rib,
i2s_if.dut i2s
// verilog_format: on
);
@@ -60,7 +60,7 @@ module nmi_i2s (
i2s_reg u_i2s_reg (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.nmi (nmi),
.rib (rib),
.mode_o (s_i2s_mode),
.format_o (s_i2s_format),
.recven_o (s_i2s_recven),
rtl/ip/native/serial/i2s_clkgen.sv → rtl/ip/rib/serial/i2s_clkgen.sv
View File
File renamed without changes.
rtl/ip/native/serial/i2s_core.sv → rtl/ip/rib/serial/i2s_core.sv
View File
File renamed without changes.
rtl/ip/native/serial/i2s_define.svh → rtl/ip/rib/serial/i2s_define.svh
+10 -10
View File
@@ -8,18 +8,18 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef NMI_I2S_DEF_SV
`define NMI_I2S_DEF_SV
`ifndef RIB_I2S_DEF_SV
`define RIB_I2S_DEF_SV
// verilog_format: off
`define NMI_I2S_MODE 8'h00
`define NMI_I2S_FORMAT 8'h04
`define NMI_I2S_UPBOUND 8'h08
`define NMI_I2S_LOWBOUND 8'h0C
`define NMI_I2S_RECVEN 8'h10
`define NMI_I2S_TXDATA 8'h14
`define NMI_I2S_RXDATA 8'h18
`define NMI_I2S_STATUS 8'h1C
`define RIB_I2S_MODE 8'h00
`define RIB_I2S_FORMAT 8'h04
`define RIB_I2S_UPBOUND 8'h08
`define RIB_I2S_LOWBOUND 8'h0C
`define RIB_I2S_RECVEN 8'h10
`define RIB_I2S_TXDATA 8'h14
`define RIB_I2S_RXDATA 8'h18
`define RIB_I2S_STATUS 8'h1C
// verilog_format: on
`define I2S_16b_48K 2'd0
rtl/ip/native/serial/i2s_recv.sv → rtl/ip/rib/serial/i2s_recv.sv
View File
File renamed without changes.
rtl/ip/native/serial/i2s_reg.sv → rtl/ip/rib/serial/i2s_reg.sv
+45 -45
View File
@@ -14,7 +14,7 @@ module i2s_reg (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
nmi_if.slave nmi,
rib_if.slave rib,
output logic mode_o,
output logic [ 1:0] format_o,
output logic recven_o,
@@ -31,11 +31,11 @@ module i2s_reg (
// verilog_format: on
);
// nmi
logic s_nmi_wr_hdshk, s_nmi_rd_hdshk;
logic s_nmi_ready_d, s_nmi_ready_q;
logic s_nmi_rdata_en;
logic [31:0] s_nmi_rdata_d, s_nmi_rdata_q;
// rib
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
// register
logic s_i2s_mode_en;
logic s_i2s_mode_d, s_i2s_mode_q;
@@ -53,11 +53,11 @@ module i2s_reg (
logic s_rx_fifo_stall_d, s_rx_fifo_stall_q;
// nmi
assign s_nmi_wr_hdshk = nmi.valid && (~s_nmi_ready_q) && (|nmi.wstrb);
assign s_nmi_rd_hdshk = nmi.valid && (~s_nmi_ready_q) && (~(|nmi.wstrb));
assign nmi.ready = s_nmi_ready_q;
assign nmi.rdata = s_nmi_rdata_q;
// rib
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
// reg
assign mode_o = s_i2s_mode_q;
assign format_o = s_i2s_format_q;
@@ -67,8 +67,8 @@ module i2s_reg (
assign dma_rx_stall_o = s_rx_fifo_stall_q;
assign s_i2s_mode_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_I2S_MODE;
assign s_i2s_mode_d = nmi.wdata[0];
assign s_i2s_mode_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2S_MODE;
assign s_i2s_mode_d = rib.wdata[0];
dffer #(1) u_i2s_mode_dffer (
clk_i,
rst_n_i,
@@ -78,8 +78,8 @@ module i2s_reg (
);
assign s_i2s_format_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_I2S_FORMAT;
assign s_i2s_format_d = nmi.wdata[1:0];
assign s_i2s_format_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2S_FORMAT;
assign s_i2s_format_d = rib.wdata[1:0];
dffer #(2) u_i2s_format_dffer (
clk_i,
rst_n_i,
@@ -89,8 +89,8 @@ module i2s_reg (
);
assign s_i2s_upbound_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_I2S_UPBOUND;
assign s_i2s_upbound_d = nmi.wdata[7:0];
assign s_i2s_upbound_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2S_UPBOUND;
assign s_i2s_upbound_d = rib.wdata[7:0];
dfferh #(8) u_i2s_upbound_dfferh (
clk_i,
rst_n_i,
@@ -100,8 +100,8 @@ module i2s_reg (
);
assign s_i2s_lowbound_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_I2S_LOWBOUND;
assign s_i2s_lowbound_d = nmi.wdata[7:0];
assign s_i2s_lowbound_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2S_LOWBOUND;
assign s_i2s_lowbound_d = rib.wdata[7:0];
dffer #(8) u_i2s_lowbound_dffer (
clk_i,
rst_n_i,
@@ -111,8 +111,8 @@ module i2s_reg (
);
assign s_i2s_recven_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_I2S_RECVEN;
assign s_i2s_recven_d = nmi.wdata[0];
assign s_i2s_recven_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2S_RECVEN;
assign s_i2s_recven_d = rib.wdata[0];
dffer #(1) u_i2s_recven_dffer (
clk_i,
rst_n_i,
@@ -158,12 +158,12 @@ module i2s_reg (
always_comb begin
tx_push_valid_o = 1'b0;
tx_push_data_o = '0;
if (s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_I2S_TXDATA) begin
if (s_rib_wr_hdshk && rib.addr[7:0] == `RIB_I2S_TXDATA) begin
tx_push_valid_o = 1'b1;
if (nmi.wstrb[0]) tx_push_data_o[7:0] = nmi.wdata[7:0];
if (nmi.wstrb[1]) tx_push_data_o[15:8] = nmi.wdata[15:8];
if (nmi.wstrb[2]) tx_push_data_o[23:16] = nmi.wdata[23:16];
if (nmi.wstrb[3]) tx_push_data_o[31:24] = nmi.wdata[31:24];
if (rib.wstrb[0]) tx_push_data_o[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) tx_push_data_o[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) tx_push_data_o[23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) tx_push_data_o[31:24] = rib.wdata[31:24];
end
end
@@ -179,38 +179,38 @@ module i2s_reg (
s_i2s_status_q
);
assign s_nmi_ready_d = nmi.valid && (~s_nmi_ready_q);
dffr #(1) u_nmi_ready_dffr (
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
clk_i,
rst_n_i,
s_nmi_ready_d,
s_nmi_ready_q
s_rib_ready_d,
s_rib_ready_q
);
assign s_nmi_rdata_en = s_nmi_rd_hdshk;
assign s_rib_rdata_en = s_rib_rd_hdshk;
always_comb begin
rx_pop_valid_o = 1'b0;
s_nmi_rdata_d = s_nmi_rdata_q;
unique case (nmi.addr[7:0])
`NMI_I2S_MODE: s_nmi_rdata_d = {31'd0, s_i2s_mode_q};
`NMI_I2S_FORMAT: s_nmi_rdata_d = {30'd0, s_i2s_format_q};
`NMI_I2S_RXDATA: begin
if (s_nmi_rd_hdshk) begin
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_I2S_MODE: s_rib_rdata_d = {31'd0, s_i2s_mode_q};
`RIB_I2S_FORMAT: s_rib_rdata_d = {30'd0, s_i2s_format_q};
`RIB_I2S_RXDATA: begin
if (s_rib_rd_hdshk) begin
rx_pop_valid_o = 1'b1;
if (!rx_empty_i) s_nmi_rdata_d = rx_pop_data_i;
else s_nmi_rdata_d = '0;
if (!rx_empty_i) s_rib_rdata_d = rx_pop_data_i;
else s_rib_rdata_d = '0;
end
end
`NMI_I2S_STATUS: s_nmi_rdata_d = {30'd0, s_i2s_status_q};
default: s_nmi_rdata_d = s_nmi_rdata_q;
`RIB_I2S_STATUS: s_rib_rdata_d = {30'd0, s_i2s_status_q};
default: s_rib_rdata_d = s_rib_rdata_q;
endcase
end
dffer #(32) u_nmi_rdata_dffer (
dffer #(32) u_rib_rdata_dffer (
clk_i,
rst_n_i,
s_nmi_rdata_en,
s_nmi_rdata_d,
s_nmi_rdata_q
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
);
endmodule
rtl/ip/native/serial/i2s_send.sv → rtl/ip/rib/serial/i2s_send.sv
View File
File renamed without changes.
rtl/ip/native/serial/onewire.sv → rtl/ip/rib/serial/onewire.sv
+49 -49
View File
@@ -12,13 +12,13 @@
`define ONEWIRE_DEF_SV
// verilog_format: off
`define NATV_ONEWIRE_CLKDIV 8'h00
`define NATV_ONEWIRE_ZEROCNT 8'h04
`define NATV_ONEWIRE_ONECNT 8'h08
`define NATV_ONEWIRE_RSTCNT 8'h0C
`define NATV_ONEWIRE_TXDATA 8'h10
`define NATV_ONEWIRE_CTRL 8'h14
`define NATV_ONEWIRE_STATUS 8'h18
`define RIB_ONEWIRE_CLKDIV 8'h00
`define RIB_ONEWIRE_ZEROCNT 8'h04
`define RIB_ONEWIRE_ONECNT 8'h08
`define RIB_ONEWIRE_RSTCNT 8'h0C
`define RIB_ONEWIRE_TXDATA 8'h10
`define RIB_ONEWIRE_CTRL 8'h14
`define RIB_ONEWIRE_STATUS 8'h18
// verilog_format: on
`endif
@@ -30,19 +30,19 @@ interface onewire_if ();
endinterface
// generate 1250ns for ws2812x only
module nmi_onewire (
module rib_onewire (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
nmi_if.slave nmi,
rib_if.slave rib,
onewire_if.dut onewire
// verilog_format: on
);
logic s_nmi_wr_hdshk, s_nmi_rd_hdshk;
logic s_nmi_ready_d, s_nmi_ready_q;
logic s_nmi_rdata_en;
logic [31:0] s_nmi_rdata_d, s_nmi_rdata_q;
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
logic s_onewire_clkdiv_en;
logic [7:0] s_onewire_clkdiv_d, s_onewire_clkdiv_q;
@@ -61,14 +61,14 @@ module nmi_onewire (
logic s_done;
assign s_nmi_wr_hdshk = nmi.valid && (~s_nmi_ready_q) && (|nmi.wstrb);
assign s_nmi_rd_hdshk = nmi.valid && (~s_nmi_ready_q) && (~(|nmi.wstrb));
assign nmi.ready = s_nmi_ready_q;
assign nmi.rdata = s_nmi_rdata_q;
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
assign s_onewire_clkdiv_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_ONEWIRE_CLKDIV;
assign s_onewire_clkdiv_d = nmi.wdata[7:0];
assign s_onewire_clkdiv_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_ONEWIRE_CLKDIV;
assign s_onewire_clkdiv_d = rib.wdata[7:0];
dffer #(8) u_onewire_clkdiv_dffer (
clk_i,
rst_n_i,
@@ -77,8 +77,8 @@ module nmi_onewire (
s_onewire_clkdiv_q
);
assign s_onewire_zerocnt_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_ONEWIRE_ZEROCNT;
assign s_onewire_zerocnt_d = nmi.wdata[7:0];
assign s_onewire_zerocnt_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_ONEWIRE_ZEROCNT;
assign s_onewire_zerocnt_d = rib.wdata[7:0];
dffer #(8) u_onewire_zerocnt_dffer (
clk_i,
rst_n_i,
@@ -87,8 +87,8 @@ module nmi_onewire (
s_onewire_zerocnt_q
);
assign s_onewire_onecnt_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_ONEWIRE_ONECNT;
assign s_onewire_onecnt_d = nmi.wdata[7:0];
assign s_onewire_onecnt_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_ONEWIRE_ONECNT;
assign s_onewire_onecnt_d = rib.wdata[7:0];
dffer #(8) u_onewire_onecnt_dffer (
clk_i,
rst_n_i,
@@ -97,8 +97,8 @@ module nmi_onewire (
s_onewire_onecnt_q
);
assign s_onewire_rstcnt_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_ONEWIRE_RSTCNT;
assign s_onewire_rstcnt_d = nmi.wdata[7:0];
assign s_onewire_rstcnt_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_ONEWIRE_RSTCNT;
assign s_onewire_rstcnt_d = rib.wdata[7:0];
dffer #(8) u_onewire_rstcnt_dffer (
clk_i,
rst_n_i,
@@ -110,11 +110,11 @@ module nmi_onewire (
always_comb begin
s_tx_push_valid = 1'b0;
s_tx_push_data = '0;
if (s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_ONEWIRE_TXDATA) begin
if (s_rib_wr_hdshk && rib.addr[7:0] == `RIB_ONEWIRE_TXDATA) begin
s_tx_push_valid = 1'b1;
if (nmi.wstrb[0]) s_tx_push_data[7:0] = nmi.wdata[7:0];
if (nmi.wstrb[1]) s_tx_push_data[15:8] = nmi.wdata[15:8];
if (nmi.wstrb[2]) s_tx_push_data[23:16] = nmi.wdata[23:16];
if (rib.wstrb[0]) s_tx_push_data[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_tx_push_data[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_tx_push_data[23:16] = rib.wdata[23:16];
end
end
@@ -138,8 +138,8 @@ module nmi_onewire (
// [0] clear fifo [1] start
always_comb begin
if (s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_ONEWIRE_CTRL) begin
s_onewire_ctrl_d = nmi.wdata[1:0];
if (s_rib_wr_hdshk && rib.addr[7:0] == `RIB_ONEWIRE_CTRL) begin
s_onewire_ctrl_d = rib.wdata[1:0];
end else begin
s_onewire_ctrl_d = '0;
end
@@ -159,7 +159,7 @@ module nmi_onewire (
s_onewire_status_d[2] = s_tx_empty;
if (s_done) begin
s_onewire_status_d[0] = 1'b1;
end else if (s_nmi_rd_hdshk && nmi.addr[7:0] == `NATV_ONEWIRE_STATUS) begin
end else if (s_rib_rd_hdshk && rib.addr[7:0] == `RIB_ONEWIRE_STATUS) begin
s_onewire_status_d[0] = 1'b0;
end
end
@@ -170,32 +170,32 @@ module nmi_onewire (
s_onewire_status_q
);
assign s_nmi_ready_d = nmi.valid && (~s_nmi_ready_q);
dffr #(1) u_nmi_ready_dffr (
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
clk_i,
rst_n_i,
s_nmi_ready_d,
s_nmi_ready_q
s_rib_ready_d,
s_rib_ready_q
);
assign s_nmi_rdata_en = s_nmi_rd_hdshk;
assign s_rib_rdata_en = s_rib_rd_hdshk;
always_comb begin
s_nmi_rdata_d = s_nmi_rdata_q;
unique case (nmi.addr[7:0])
`NATV_ONEWIRE_CLKDIV: s_nmi_rdata_d = {24'd0, s_onewire_clkdiv_q};
`NATV_ONEWIRE_ZEROCNT: s_nmi_rdata_d = {24'd0, s_onewire_zerocnt_q};
`NATV_ONEWIRE_ONECNT: s_nmi_rdata_d = {24'd0, s_onewire_onecnt_q};
`NATV_ONEWIRE_RSTCNT: s_nmi_rdata_d = {24'd0, s_onewire_rstcnt_q};
`NATV_ONEWIRE_STATUS: s_nmi_rdata_d = {29'd0, s_onewire_status_q};
default: s_nmi_rdata_d = s_nmi_rdata_q;
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_ONEWIRE_CLKDIV: s_rib_rdata_d = {24'd0, s_onewire_clkdiv_q};
`RIB_ONEWIRE_ZEROCNT: s_rib_rdata_d = {24'd0, s_onewire_zerocnt_q};
`RIB_ONEWIRE_ONECNT: s_rib_rdata_d = {24'd0, s_onewire_onecnt_q};
`RIB_ONEWIRE_RSTCNT: s_rib_rdata_d = {24'd0, s_onewire_rstcnt_q};
`RIB_ONEWIRE_STATUS: s_rib_rdata_d = {29'd0, s_onewire_status_q};
default: s_rib_rdata_d = s_rib_rdata_q;
endcase
end
dffer #(32) u_nmi_rdata_dffer (
dffer #(32) u_rib_rdata_dffer (
clk_i,
rst_n_i,
s_nmi_rdata_en,
s_nmi_rdata_d,
s_nmi_rdata_q
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
);
onewire_core u_onewire_core (
rtl/ip/native/serial/onewire_core.sv → rtl/ip/rib/serial/onewire_core.sv
View File
File renamed without changes.
rtl/ip/native/serial/uart.sv → rtl/ip/rib/serial/uart.sv
+38 -38
View File
@@ -29,29 +29,29 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef NMI_UART_DEF_SV
`define NMI_UART_DEF_SV
`ifndef RIB_UART_DEF_SV
`define RIB_UART_DEF_SV
// verilog_format: off
`define NMI_UART_DIV 8'h00
`define NMI_UART_DAT 8'h04
`define RIB_UART_DIV 8'h00
`define RIB_UART_DAT 8'h04
// verilog_format: on
`endif
module nmi_uart (
module rib_uart (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
nmi_if.slave nmi,
rib_if.slave rib,
uart_if.dut uart
// verilog_format: on
);
logic s_nmi_wr_hdshk, s_nmi_rd_hdshk;
logic s_nmi_ready_d, s_nmi_ready_q;
logic s_nmi_rdata_en;
logic [31:0] s_nmi_rdata_d, s_nmi_rdata_q;
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
logic s_uart_div_en;
logic [31:0] s_uart_div_d, s_uart_div_q;
@@ -69,21 +69,21 @@ module nmi_uart (
logic r_send_dummy;
assign s_nmi_wr_hdshk = nmi.valid && (~s_nmi_ready_q) && (|nmi.wstrb);
assign s_nmi_rd_hdshk = nmi.valid && (~s_nmi_ready_q) && (~(|nmi.wstrb));
assign nmi.ready = s_nmi_ready_q;
assign nmi.rdata = s_nmi_rdata_q;
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
assign uart.tx_o = r_send_pattern[0];
assign uart.irq_o = r_recv_buf_valid;
assign s_uart_div_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_UART_DIV;
assign s_uart_div_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_UART_DIV;
always_comb begin
s_uart_div_d = s_uart_div_q;
if (nmi.wstrb[0]) s_uart_div_d[7:0] = nmi.wdata[7:0];
if (nmi.wstrb[1]) s_uart_div_d[15:8] = nmi.wdata[15:8];
if (nmi.wstrb[2]) s_uart_div_d[23:16] = nmi.wdata[23:16];
if (nmi.wstrb[3]) s_uart_div_d[31:24] = nmi.wdata[31:24];
if (rib.wstrb[0]) s_uart_div_d[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_uart_div_d[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_uart_div_d[23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_uart_div_d[31:24] = rib.wdata[31:24];
end
dfferh #(32) u_uart_div_dfferh (
clk_i,
@@ -93,31 +93,31 @@ module nmi_uart (
s_uart_div_q
);
assign s_uart_dat_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_UART_DAT;
assign s_send_dat_wait = s_uart_dat_en && nmi.wstrb[0] && ((|r_send_bitcnt) || r_send_dummy);
assign s_nmi_ready_d = nmi.valid && (~s_nmi_ready_q) && (~s_send_dat_wait);
dffr #(1) u_nmi_ready_dffr (
assign s_uart_dat_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_UART_DAT;
assign s_send_dat_wait = s_uart_dat_en && rib.wstrb[0] && ((|r_send_bitcnt) || r_send_dummy);
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q) && (~s_send_dat_wait);
dffr #(1) u_rib_ready_dffr (
clk_i,
rst_n_i,
s_nmi_ready_d,
s_nmi_ready_q
s_rib_ready_d,
s_rib_ready_q
);
assign s_nmi_rdata_en = s_nmi_rd_hdshk;
assign s_rib_rdata_en = s_rib_rd_hdshk;
always_comb begin
s_nmi_rdata_d = s_nmi_rdata_q;
unique case (nmi.addr[7:0])
`NMI_UART_DIV: s_nmi_rdata_d = s_uart_div_q;
`NMI_UART_DAT: s_nmi_rdata_d = r_recv_buf_valid ? {24'd0, r_recv_buf_data} : '1;
default: s_nmi_rdata_d = s_nmi_rdata_q;
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_UART_DIV: s_rib_rdata_d = s_uart_div_q;
`RIB_UART_DAT: s_rib_rdata_d = r_recv_buf_valid ? {24'd0, r_recv_buf_data} : '1;
default: s_rib_rdata_d = s_rib_rdata_q;
endcase
end
dffer #(32) u_nmi_rdata_dffer (
dffer #(32) u_rib_rdata_dffer (
clk_i,
rst_n_i,
s_nmi_rdata_en,
s_nmi_rdata_d,
s_nmi_rdata_q
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
);
@@ -175,11 +175,11 @@ module nmi_uart (
r_send_bitcnt <= 4'd15;
r_send_divcnt <= '0;
r_send_dummy <= '0;
end else if (s_uart_dat_en && nmi.wstrb[0] && (~(|r_send_bitcnt))) begin
r_send_pattern <= {1'b1, nmi.wdata[7:0], 1'b0};
end else if (s_uart_dat_en && rib.wstrb[0] && (~(|r_send_bitcnt))) begin
r_send_pattern <= {1'b1, rib.wdata[7:0], 1'b0};
`ifndef SYNTHESIS
`ifdef SIMU_VERILATOR
$write("%c", nmi.wdata[7:0]); // NOTE: just for verilator sim
$write("%c", rib.wdata[7:0]); // NOTE: just for verilator sim
`endif
`endif
r_send_bitcnt <= 4'd10;
rtl/ip/native/storage/sdio.sv → rtl/ip/rib/storage/sdio.sv
+5 -5
View File
@@ -31,20 +31,20 @@ interface sdio_if ();
endinterface
module nmi_sdio (
module rib_sdio (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
nmi_if.slave nmi,
rib_if.slave rib,
sdio_if.dut sdio
// verilog_format: on
);
wire dummy0 = clk_i;
wire dummy1 = rst_n_i;
// nmi
assign nmi.rdata = '0;
assign nmi.ready = '0;
// rib
assign rib.rdata = '0;
assign rib.ready = '0;
// sdio
assign sdio.sck_o = '0;
assign sdio.cmd_oe_o = '0;
rtl/ip/native/storage/spisd.sv → rtl/ip/rib/storage/spisd.sv
+28 -28
View File
@@ -14,11 +14,11 @@
`include "mmap_define.svh"
module nmi_spisd (
module rib_spisd (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
nmi_if.slave nmi,
rib_if.slave rib,
spi_if.dut spi
// verilog_format: on
);
@@ -40,25 +40,25 @@ module nmi_spisd (
logic [ 7:0] s_sd_wr_data;
logic s_sd_wr_busy;
nmi_if u_cfg_nmi_if ();
nmi_if u_cache_nmi_if ();
nmi_if u_cache_mem_nmi_if ();
nmi_if u_cache_byp_nmi_if ();
rib_if u_cfg_rib_if ();
rib_if u_cache_rib_if ();
rib_if u_cache_mem_rib_if ();
rib_if u_cache_byp_rib_if ();
// verilog_format: off
assign s_cfg_reg_sel = `SOC_ADDR_IS_NMI_SPISD(nmi.addr);
assign u_cfg_nmi_if.valid = nmi.valid && s_cfg_reg_sel;
assign u_cfg_nmi_if.addr = nmi.addr;
assign u_cfg_nmi_if.wdata = nmi.wdata;
assign u_cfg_nmi_if.wstrb = nmi.wstrb;
assign s_cfg_reg_sel = `SOC_ADDR_IS_RIB_SPISD(rib.addr);
assign u_cfg_rib_if.valid = rib.valid && s_cfg_reg_sel;
assign u_cfg_rib_if.addr = rib.addr;
assign u_cfg_rib_if.wdata = rib.wdata;
assign u_cfg_rib_if.wstrb = rib.wstrb;
assign u_cache_mem_nmi_if.valid = nmi.valid && (~s_cfg_reg_sel);
assign u_cache_mem_nmi_if.addr = nmi.addr;
assign u_cache_mem_nmi_if.wdata = nmi.wdata;
assign u_cache_mem_nmi_if.wstrb = nmi.wstrb;
assign u_cache_mem_rib_if.valid = rib.valid && (~s_cfg_reg_sel);
assign u_cache_mem_rib_if.addr = rib.addr;
assign u_cache_mem_rib_if.wdata = rib.wdata;
assign u_cache_mem_rib_if.wstrb = rib.wstrb;
assign nmi.ready = s_cfg_reg_sel ? u_cfg_nmi_if.ready : u_cache_mem_nmi_if.ready;
assign nmi.rdata = s_cfg_reg_sel ? u_cfg_nmi_if.rdata : u_cache_mem_nmi_if.rdata;
assign rib.ready = s_cfg_reg_sel ? u_cfg_rib_if.ready : u_cache_mem_rib_if.ready;
assign rib.rdata = s_cfg_reg_sel ? u_cfg_rib_if.rdata : u_cache_mem_rib_if.rdata;
// verilog_format: on
spisd_reg u_spisd_reg (
@@ -69,20 +69,20 @@ module nmi_spisd (
.wr_sync_done_i(s_wr_sync_done),
.mode_o (s_mode),
.clkdiv_o (s_clkdiv),
.nmi (u_cfg_nmi_if),
.byp_nmi (u_cache_byp_nmi_if)
.rib (u_cfg_rib_if),
.byp_rib (u_cache_byp_rib_if)
);
assign u_cache_nmi_if.valid = s_mode ? u_cache_byp_nmi_if.valid : u_cache_mem_nmi_if.valid;
assign u_cache_nmi_if.addr = s_mode ? u_cache_byp_nmi_if.addr : u_cache_mem_nmi_if.addr;
assign u_cache_nmi_if.wdata = s_mode ? u_cache_byp_nmi_if.wdata : u_cache_mem_nmi_if.wdata;
assign u_cache_nmi_if.wstrb = s_mode ? u_cache_byp_nmi_if.wstrb : u_cache_mem_nmi_if.wstrb;
assign u_cache_rib_if.valid = s_mode ? u_cache_byp_rib_if.valid : u_cache_mem_rib_if.valid;
assign u_cache_rib_if.addr = s_mode ? u_cache_byp_rib_if.addr : u_cache_mem_rib_if.addr;
assign u_cache_rib_if.wdata = s_mode ? u_cache_byp_rib_if.wdata : u_cache_mem_rib_if.wdata;
assign u_cache_rib_if.wstrb = s_mode ? u_cache_byp_rib_if.wstrb : u_cache_mem_rib_if.wstrb;
assign u_cache_byp_nmi_if.ready = s_mode ? u_cache_nmi_if.ready : '0;
assign u_cache_byp_nmi_if.rdata = s_mode ? u_cache_nmi_if.rdata : '0;
assign u_cache_mem_nmi_if.ready = ~s_mode ? u_cache_nmi_if.ready : '0;
assign u_cache_mem_nmi_if.rdata = ~s_mode ? u_cache_nmi_if.rdata : '0;
assign u_cache_byp_rib_if.ready = s_mode ? u_cache_rib_if.ready : '0;
assign u_cache_byp_rib_if.rdata = s_mode ? u_cache_rib_if.rdata : '0;
assign u_cache_mem_rib_if.ready = ~s_mode ? u_cache_rib_if.ready : '0;
assign u_cache_mem_rib_if.rdata = ~s_mode ? u_cache_rib_if.rdata : '0;
spisd_cache u_spisd_cache (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
@@ -100,7 +100,7 @@ module nmi_spisd (
.sd_wr_data_req_i(s_sd_wr_data_req),
.sd_wr_data_o (s_sd_wr_data),
.sd_wr_busy_i (s_sd_wr_busy),
.nmi (u_cache_nmi_if)
.rib (u_cache_rib_if)
);
assign spi.irq_o = 1'b0; // TODO:
rtl/ip/native/storage/spisd_cache.sv → rtl/ip/rib/storage/spisd_cache.sv
+18 -18
View File
@@ -26,7 +26,7 @@ module spisd_cache (
input logic sd_wr_data_req_i,
output logic [7:0] sd_wr_data_o,
input logic sd_wr_busy_i,
nmi_if.slave nmi
rib_if.slave rib
// verilog_format: on
);
@@ -56,11 +56,11 @@ module spisd_cache (
// io
assign sd_wr_data_o = s_sd_wr_data_q;
assign nmi.rdata = s_cache_data_q[s_cache_index];
assign rib.rdata = s_cache_data_q[s_cache_index];
// cache
assign s_cache_index = nmi.addr[8:2];
assign s_cache_mem_hit = ~mode_i && (nmi.addr[27:9] == s_cache_tag_q[18:0]);
assign s_cache_byp_hit = mode_i && (nmi.addr == s_cache_tag_q);
assign s_cache_index = rib.addr[8:2];
assign s_cache_mem_hit = ~mode_i && (rib.addr[27:9] == s_cache_tag_q[18:0]);
assign s_cache_byp_hit = mode_i && (rib.addr == s_cache_tag_q);
always_comb begin
// cache
@@ -79,13 +79,13 @@ module spisd_cache (
s_sd_wr_data_d = s_sd_wr_data_q;
sd_addr_o = '0;
// mem_if
nmi.ready = '0;
rib.ready = '0;
// wr sync
wr_sync_done_o = '0;
unique case (s_cache_fsm_q)
FSM_IDLE: begin
if (init_done_i) begin
if (nmi.valid) s_cache_fsm_d = FSM_COMP_TAG;
if (rib.valid) s_cache_fsm_d = FSM_COMP_TAG;
// sw wr sync
else if (wr_sync_i && s_cache_dirty_q) begin
s_cache_fsm_d = FSM_WR_BACK;
@@ -98,26 +98,26 @@ module spisd_cache (
if ((s_cache_mem_hit || s_cache_byp_hit) && s_cache_valid_q) begin
if (s_wr_sync_q) wr_sync_done_o = 1'b1; // wr sync oper
else begin
nmi.ready = 1'b1; // nomral oper
rib.ready = 1'b1; // nomral oper
// write oper, set dirty
if (|nmi.wstrb) begin
if (|rib.wstrb) begin
s_cache_dirty_d = 1'b1;
if (nmi.wstrb[0]) s_cache_data_d[s_cache_index][7:0] = nmi.wdata[7:0];
if (nmi.wstrb[1]) s_cache_data_d[s_cache_index][15:8] = nmi.wdata[15:8];
if (nmi.wstrb[2]) s_cache_data_d[s_cache_index][23:16] = nmi.wdata[23:16];
if (nmi.wstrb[3]) s_cache_data_d[s_cache_index][31:24] = nmi.wdata[31:24];
if (rib.wstrb[0]) s_cache_data_d[s_cache_index][7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_cache_data_d[s_cache_index][15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_cache_data_d[s_cache_index][23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_cache_data_d[s_cache_index][31:24] = rib.wdata[31:24];
end
end
s_cache_fsm_d = FSM_IDLE;
end else begin
// need to update tag line info
s_cache_valid_d = 1'b1;
s_cache_dirty_d = |nmi.wstrb;
s_cache_dirty_d = |rib.wstrb;
// tag line is clean
if (s_cache_valid_q == 1'b0 || s_cache_dirty_q == 1'b0) begin
s_cache_fsm_d = FSM_ALLOC;
if (~mode_i) s_cache_tag_d = {13'd0, nmi.addr[27:9]};
else s_cache_tag_d = nmi.addr;
if (~mode_i) s_cache_tag_d = {13'd0, rib.addr[27:9]};
else s_cache_tag_d = rib.addr;
end else begin
// need to flush data into sd card sectors
s_cache_fsm_d = FSM_WR_BACK;
@@ -159,8 +159,8 @@ module spisd_cache (
s_word_data_d = s_cache_data_q[s_line_cnt_d];
if (s_line_cnt_q == 7'd127) begin
s_cache_fsm_d = FSM_ALLOC;
if (~mode_i) s_cache_tag_d = {13'd0, nmi.addr[27:9]};
else s_cache_tag_d = nmi.addr;
if (~mode_i) s_cache_tag_d = {13'd0, rib.addr[27:9]};
else s_cache_tag_d = rib.addr;
end
end else begin
s_word_cnt_d = s_word_cnt_q + 1'b1;
rtl/ip/native/storage/spisd_core.sv → rtl/ip/rib/storage/spisd_core.sv
View File
File renamed without changes.
rtl/ip/native/storage/spisd_data.sv → rtl/ip/rib/storage/spisd_data.sv
View File
File renamed without changes.
rtl/ip/native/storage/spisd_init.sv → rtl/ip/rib/storage/spisd_init.sv
View File
File renamed without changes.
rtl/ip/native/storage/spisd_read.sv → rtl/ip/rib/storage/spisd_read.sv
View File
File renamed without changes.
rtl/ip/rib/storage/spisd_reg.sv
+157
View File
@@ -0,0 +1,157 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIB_SPISD_DEF_SV
`define RIB_SPISD_DEF_SV
// verilog_format: off
`define RIB_SPISD_MODE 8'h00
`define RIB_SPISD_CLKDIV 8'h04
`define RIB_SPISD_ADDR 8'h08
`define RIB_SPISD_TXDATA 8'h0C
`define RIB_SPISD_RXDATA 8'h10
`define RIB_SPISD_STATUS 8'h14
`define RIB_SPISD_SYNC 8'h18
// verilog_format: on
`endif
module spisd_reg (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
input logic init_done_i,
output logic wr_sync_o,
input logic wr_sync_done_i,
output logic mode_o,
output logic [1:0] clkdiv_o,
rib_if.slave rib,
rib_if.master byp_rib
// verilog_format: on
);
// rib
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
// reg
logic s_spisd_mode_en;
logic s_spisd_mode_d, s_spisd_mode_q;
logic s_spisd_clkdiv_en;
logic [1:0] s_spisd_clkdiv_d, s_spisd_clkdiv_q;
logic s_spisd_addr_en;
logic [31:0] s_spisd_addr_d, s_spisd_addr_q;
logic [1:0] s_spisd_status_d, s_spisd_status_q;
// common
logic s_wr_byp, s_rd_byp;
// rib
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign s_wr_byp = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_SPISD_TXDATA;
assign s_rd_byp = s_rib_rd_hdshk && rib.addr[7:0] == `RIB_SPISD_RXDATA;
assign rib.ready = (s_wr_byp || s_rd_byp) ? byp_rib.ready : s_rib_ready_q;
assign rib.rdata = (s_wr_byp || s_rd_byp) ? byp_rib.rdata : s_rib_rdata_q;
// common
assign mode_o = s_spisd_mode_q;
assign clkdiv_o = s_spisd_clkdiv_q;
// byp
assign byp_rib.valid = s_wr_byp || s_rd_byp;
assign byp_rib.addr = s_spisd_addr_q;
assign byp_rib.wdata = rib.wdata;
assign byp_rib.wstrb = rib.wstrb;
assign s_spisd_mode_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_SPISD_MODE;
assign s_spisd_mode_d = rib.wdata[0];
dffer #(1) u_spisd_mode_dffer (
clk_i,
rst_n_i,
s_spisd_mode_en,
s_spisd_mode_d,
s_spisd_mode_q
);
assign s_spisd_clkdiv_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_SPISD_CLKDIV;
assign s_spisd_clkdiv_d = rib.wdata[1:0];
dffer #(2) u_spisd_clkdiv_dffer (
clk_i,
rst_n_i,
s_spisd_clkdiv_en,
s_spisd_clkdiv_d,
s_spisd_clkdiv_q
);
assign s_spisd_addr_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_SPISD_ADDR;
always_comb begin
s_spisd_addr_d = s_spisd_addr_q;
if (rib.wstrb[0]) s_spisd_addr_d[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_spisd_addr_d[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_spisd_addr_d[23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_spisd_addr_d[31:24] = rib.wdata[31:24];
end
dffer #(32) u_spisd_addr_dffer (
clk_i,
rst_n_i,
s_spisd_addr_en,
s_spisd_addr_d,
s_spisd_addr_q
);
// 0: init done
// 1: wr sync done
always_comb begin
s_spisd_status_d = s_spisd_status_q;
s_spisd_status_d[0] = init_done_i;
if (wr_sync_done_i && ~s_spisd_status_q[1]) begin
s_spisd_status_d[1] = 1'b1;
end else if (s_spisd_status_q[1] && s_rib_rd_hdshk && rib.addr[7:0] == `RIB_SPISD_STATUS) begin
s_spisd_status_d[1] = 1'b0;
end
end
dffr #(2) u_spisd_status_dffr (
clk_i,
rst_n_i,
s_spisd_status_d,
s_spisd_status_q
);
// software wr sync
assign wr_sync_o = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_SPISD_SYNC;
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
clk_i,
rst_n_i,
s_rib_ready_d,
s_rib_ready_q
);
assign s_rib_rdata_en = s_rib_rd_hdshk;
always_comb begin
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_SPISD_MODE: s_rib_rdata_d = {31'd0, s_spisd_mode_q};
`RIB_SPISD_CLKDIV: s_rib_rdata_d = {30'd0, s_spisd_clkdiv_q};
`RIB_SPISD_ADDR: s_rib_rdata_d = s_spisd_addr_q;
`RIB_SPISD_STATUS: s_rib_rdata_d = {30'd0, s_spisd_status_q};
default: s_rib_rdata_d = s_rib_rdata_q;
endcase
end
dffer #(32) u_rib_rdata_dffer (
clk_i,
rst_n_i,
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
);
endmodule
rtl/ip/native/storage/spisd_write.sv → rtl/ip/rib/storage/spisd_write.sv
View File
File renamed without changes.
rtl/ip/native/storage/xpi.sv → rtl/ip/rib/storage/xpi.sv
+24 -24
View File
@@ -29,14 +29,14 @@ interface xpi_if ();
);
endinterface
module nmi_xpi (
module rib_xpi (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
input logic dma_xfer_done_i,
output logic dma_tx_stall_o,
output logic dma_rx_stall_o,
nmi_if.slave nmi,
rib_if.slave rib,
xpi_if.dut xpi
// verilog_format: on
);
@@ -102,28 +102,28 @@ module nmi_xpi (
// ctrl
logic s_reg_xfer_start, s_xfer_done;
// interface
nmi_if u_reg_nmi_if ();
nmi_if u_mm_nmi_if ();
rib_if u_reg_rib_if ();
rib_if u_mm_rib_if ();
// nmi mux
assign s_xpi_mm_sel = `SOC_ADDR_IS_FLASH(nmi.addr) || `SOC_ADDR_IS_XPI(nmi.addr);
assign u_reg_nmi_if.valid = nmi.valid && (~s_xpi_mm_sel);
assign u_reg_nmi_if.addr = nmi.addr;
assign u_reg_nmi_if.wdata = nmi.wdata;
assign u_reg_nmi_if.wstrb = nmi.wstrb;
// rib mux
assign s_xpi_mm_sel = `SOC_ADDR_IS_FLASH(rib.addr) || `SOC_ADDR_IS_XPI(rib.addr);
assign u_reg_rib_if.valid = rib.valid && (~s_xpi_mm_sel);
assign u_reg_rib_if.addr = rib.addr;
assign u_reg_rib_if.wdata = rib.wdata;
assign u_reg_rib_if.wstrb = rib.wstrb;
assign u_mm_nmi_if.valid = nmi.valid && s_xpi_mm_sel;
assign u_mm_nmi_if.addr = nmi.addr;
assign u_mm_nmi_if.wdata = nmi.wdata;
assign u_mm_nmi_if.wstrb = nmi.wstrb;
assign u_mm_rib_if.valid = rib.valid && s_xpi_mm_sel;
assign u_mm_rib_if.addr = rib.addr;
assign u_mm_rib_if.wdata = rib.wdata;
assign u_mm_rib_if.wstrb = rib.wstrb;
// verilog_format: off
assign nmi.ready = (u_reg_nmi_if.valid & u_reg_nmi_if.ready) |
(u_mm_nmi_if.valid & u_mm_nmi_if.ready);
assign rib.ready = (u_reg_rib_if.valid & u_reg_rib_if.ready) |
(u_mm_rib_if.valid & u_mm_rib_if.ready);
assign nmi.rdata = ({32{(u_reg_nmi_if.valid & u_reg_nmi_if.ready)}} & u_reg_nmi_if.rdata) |
({32{(u_mm_nmi_if.valid & u_mm_nmi_if.ready)}} & u_mm_nmi_if.rdata);
assign rib.rdata = ({32{(u_reg_rib_if.valid & u_reg_rib_if.ready)}} & u_reg_rib_if.rdata) |
({32{(u_mm_rib_if.valid & u_mm_rib_if.ready)}} & u_mm_rib_if.rdata);
// verilog_format: on
// reg/mm mode nss
@@ -181,7 +181,7 @@ module nmi_xpi (
// dma
.dma_tx_stall_o (dma_tx_stall_o),
.dma_rx_stall_o (dma_rx_stall_o),
.nmi (u_reg_nmi_if)
.rib (u_reg_rib_if)
);
@@ -206,7 +206,7 @@ module nmi_xpi (
.rx_pop_ready_i (s_rx_pop_ready),
// ctrl
.xfer_done_i (s_xfer_done),
.nmi (u_mm_nmi_if)
.rib (u_mm_rib_if)
);
@@ -255,7 +255,7 @@ module nmi_xpi (
.nss_i(s_xpi_nss),
.mode_i(s_xpi_mode[s_xpi_nss]),
.clkdiv_i(s_xpi_clkdiv[s_xpi_nss]),
.rdwr_i(u_mm_nmi_if.valid ? s_xpi_mm_rdwr : s_xpi_rdwr[s_xpi_nss]),
.rdwr_i(u_mm_rib_if.valid ? s_xpi_mm_rdwr : s_xpi_rdwr[s_xpi_nss]),
.revdat_i(s_xpi_revdat[s_xpi_nss]),
.cmdtyp_i(s_xpi_cmdtyp[s_xpi_nss]),
.cmdlen_i(s_xpi_cmdlen[s_xpi_nss]),
@@ -263,12 +263,12 @@ module nmi_xpi (
.adrtyp_i(s_xpi_adrtyp[s_xpi_nss]),
.adrlen_i(s_xpi_adrlen[s_xpi_nss]),
// HACK:
.adrdat_i(u_mm_nmi_if.valid ? {s_xpi_mm_addr[23:0], 8'hF0} : s_xpi_adrdat[s_xpi_nss]),
.adrdat_i(u_mm_rib_if.valid ? {s_xpi_mm_addr[23:0], 8'hF0} : s_xpi_adrdat[s_xpi_nss]),
.tdulen_i(s_xpi_tdulen[s_xpi_nss]),
.rdulen_i(s_xpi_rdulen[s_xpi_nss]),
.dattyp_i(s_xpi_dattyp[s_xpi_nss]),
.datlen_i(s_xpi_datlen[s_xpi_nss]), // NOTE:
.datbit_i(u_mm_nmi_if.valid ? s_xpi_mm_xfer_byte : s_xpi_datbit[s_xpi_nss]),
.datbit_i(u_mm_rib_if.valid ? s_xpi_mm_xfer_byte : s_xpi_datbit[s_xpi_nss]),
.hlvlen_i(s_xpi_hlvlen[s_xpi_nss]),
.tx_data_req_o(s_tx_pop_valid),
.tx_data_rdy_i(s_tx_pop_ready),
@@ -276,7 +276,7 @@ module nmi_xpi (
.rx_data_req_o(s_rx_push_valid),
.rx_data_rdy_i(s_rx_push_ready),
.rx_data_o(s_rx_push_data),
.start_i(u_mm_nmi_if.valid ? s_xpi_mm_req : s_reg_xfer_start),
.start_i(u_mm_rib_if.valid ? s_xpi_mm_req : s_reg_xfer_start),
.done_o(s_xfer_done),
.tx_elem_num_i(s_tx_elem_num[7:0]),
.dma_xfer_done_i(dma_xfer_done_i),
rtl/ip/native/storage/xpi_clkgen.sv → rtl/ip/rib/storage/xpi_clkgen.sv
View File
File renamed without changes.
rtl/ip/native/storage/xpi_core.sv → rtl/ip/rib/storage/xpi_core.sv
View File
File renamed without changes.
rtl/ip/rib/storage/xpi_define.svh
+58
View File
@@ -0,0 +1,58 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RIB_XPI_DEF_SV
`define RIB_XPI_DEF_SV
// verilog_format: off
`define RIB_XPI_CFGIDX 8'h00
`define RIB_XPI_ACCMD 8'h04
`define RIB_XPI_MMSTAD 8'h08
`define RIB_XPI_MMOFFST 8'h0C
`define RIB_XPI_MODE 8'h10
`define RIB_XPI_NSS 8'h14
`define RIB_XPI_CLKDIV 8'h18
`define RIB_XPI_RDWR 8'h1C
`define RIB_XPI_REVDAT 8'h20
`define RIB_XPI_TXUPB 8'h24
`define RIB_XPI_TXLOWB 8'h28
`define RIB_XPI_RXUPB 8'h2C
`define RIB_XPI_RXLOWB 8'h30
`define RIB_XPI_FLUSH 8'h34
`define RIB_XPI_CMDTYP 8'h38
`define RIB_XPI_CMDLEN 8'h3C
`define RIB_XPI_CMDDAT 8'h40
`define RIB_XPI_ADRTYP 8'h44
`define RIB_XPI_ADRLEN 8'h48
`define RIB_XPI_ADRDAT 8'h4C
`define RIB_XPI_ALTTYP 8'h50
`define RIB_XPI_ALTLEN 8'h54
`define RIB_XPI_ALTDAT 8'h58
`define RIB_XPI_TDULEN 8'h5C
`define RIB_XPI_RDULEN 8'h60
`define RIB_XPI_DATTYP 8'h64
`define RIB_XPI_DATLEN 8'h68
`define RIB_XPI_DATBIT 8'h6C
`define RIB_XPI_HLVLEN 8'h70
`define RIB_XPI_TXDATA 8'h74
`define RIB_XPI_RXDATA 8'h78
`define RIB_XPI_XST 8'h7C
`define RIB_XPI_STATUS 8'h80
`define XPI_TYPE_NONE 2'd0
`define XPI_TYPE_SNGL 2'd1
`define XPI_TYPE_DUAL 2'd2
`define XPI_TYPE_QUAD 2'd3
`define XPI_NSS_NUM 4
`define XPI_LNS_NUM $clog2(`XPI_NSS_NUM)
// verilog_format: on
`endif
rtl/ip/native/storage/xpi_mm.sv → rtl/ip/rib/storage/xpi_mm.sv
+33 -33
View File
@@ -32,7 +32,7 @@ module xpi_mm (
input logic rx_pop_ready_i,
// ctrl
input logic xfer_done_i,
nmi_if.slave nmi
rib_if.slave rib
// verilog_format: on
);
// verilog_format: off
@@ -43,11 +43,11 @@ module xpi_mm (
localparam FSM_RD = 3'd4;
// verilog_format: on
// nmi
logic s_nmi_wr_hdshk, s_nmi_rd_hdshk;
logic s_nmi_ready_d, s_nmi_ready_q;
logic s_nmi_rdata_en;
logic [31:0] s_nmi_rdata_d, s_nmi_rdata_q;
// rib
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
// ctrl
logic r_rd_st;
logic r_wr_st;
@@ -62,34 +62,34 @@ module xpi_mm (
logic s_mem_valid_re;
logic [`XPI_LNS_NUM-1:0] s_nss_d, s_nss_q;
// nmi
assign s_nmi_wr_hdshk = nmi.valid && (~s_nmi_ready_q) && (|nmi.wstrb);
assign s_nmi_rd_hdshk = nmi.valid && (~s_nmi_ready_q) && (~(|nmi.wstrb));
assign nmi.ready = s_nmi_ready_q;
assign nmi.rdata = s_nmi_rdata_q;
// nmi rd
// rib
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
// rib rd
always_comb begin
if (s_nmi_rd_hdshk) s_nmi_ready_d = rx_pop_ready_i;
else if (s_nmi_wr_hdshk) s_nmi_ready_d = xfer_done_i;
else s_nmi_ready_d = 1'b0;
if (s_rib_rd_hdshk) s_rib_ready_d = rx_pop_ready_i;
else if (s_rib_wr_hdshk) s_rib_ready_d = xfer_done_i;
else s_rib_ready_d = 1'b0;
end
dffr #(1) u_nmi_ready_dffr (
dffr #(1) u_rib_ready_dffr (
clk_i,
rst_n_i,
s_nmi_ready_d,
s_nmi_ready_q
s_rib_ready_d,
s_rib_ready_q
);
assign rx_pop_valid_o = s_nmi_rd_hdshk;
assign s_nmi_rdata_en = s_nmi_rd_hdshk;
assign s_nmi_rdata_d = (nmi.valid && rx_pop_ready_i) ? rx_pop_data_i : s_nmi_rdata_q;
dffer #(32) u_nmi_rdata_dffer (
assign rx_pop_valid_o = s_rib_rd_hdshk;
assign s_rib_rdata_en = s_rib_rd_hdshk;
assign s_rib_rdata_d = (rib.valid && rx_pop_ready_i) ? rx_pop_data_i : s_rib_rdata_q;
dffer #(32) u_rib_rdata_dffer (
clk_i,
rst_n_i,
s_nmi_rdata_en,
s_nmi_rdata_d,
s_nmi_rdata_q
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
);
@@ -109,7 +109,7 @@ module xpi_mm (
always_comb begin
s_nss_d = s_nss_q;
for (int i = 0; i < `XPI_NSS_NUM; i++) begin
if (xpi_mmstad_i[i] <= nmi.addr && nmi.addr <= xpi_mmstad_i[i] + xpi_mmoffst_i[i]) begin
if (xpi_mmstad_i[i] <= rib.addr && rib.addr <= xpi_mmstad_i[i] + xpi_mmoffst_i[i]) begin
s_nss_d = `XPI_LNS_NUM'(i);
break;
end
@@ -128,7 +128,7 @@ module xpi_mm (
edge_det_sync_re #(1) u_mem_valid_edge_det_sync_re (
clk_i,
rst_n_i,
nmi.valid,
rib.valid,
s_mem_valid_re
);
@@ -145,15 +145,15 @@ module xpi_mm (
unique case (r_fsm_state)
FSM_IDLE: begin
if (s_mem_valid_re) begin
if (|nmi.wstrb) begin
if (|rib.wstrb) begin
r_fsm_state <= FSM_WE_ST;
r_addr <= {4'd0, nmi.addr[27:0]} + {30'd0, s_disp_addr_ofst};
r_addr <= {4'd0, rib.addr[27:0]} + {30'd0, s_disp_addr_ofst};
r_wr_data <= s_disp_wdata;
r_xfer_byte_cnt <= s_disp_byte_cnt;
end else begin
r_fsm_state <= FSM_RD_ST;
r_addr <= {4'd0, nmi.addr[27:0]};
r_wr_data <= nmi.wdata; // NOTE: no used
r_addr <= {4'd0, rib.addr[27:0]};
r_wr_data <= rib.wdata; // NOTE: no used
r_xfer_byte_cnt <= 3'd4;
end
end
@@ -192,8 +192,8 @@ module xpi_mm (
end
xfer_dispatcher u_xfer_dispatcher (
.wstrb_i (nmi.wstrb),
.wdata_i (nmi.wdata),
.wstrb_i (rib.wstrb),
.wdata_i (rib.wdata),
.addr_ofst_o (s_disp_addr_ofst),
.xfer_byte_cnt_o(s_disp_byte_cnt),
.wdata_o (s_disp_wdata)
rtl/ip/native/storage/xpi_reg.sv → rtl/ip/rib/storage/xpi_reg.sv
+137 -137
View File
@@ -58,15 +58,15 @@ module xpi_reg (
// dma
output logic dma_tx_stall_o,
output logic dma_rx_stall_o,
nmi_if.slave nmi
rib_if.slave rib
// verilog_format: on
);
// nmi
logic s_nmi_wr_hdshk, s_nmi_rd_hdshk;
logic s_nmi_ready_d, s_nmi_ready_q;
logic s_nmi_rdata_en;
logic [31:0] s_nmi_rdata_d, s_nmi_rdata_q;
// rib
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
logic s_rib_ready_d, s_rib_ready_q;
logic s_rib_rdata_en;
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
// cfgidx
logic s_xpi_cfgidx_en;
logic [`XPI_LNS_NUM-1:0] s_xpi_cfgidx_d;
@@ -189,11 +189,11 @@ module xpi_reg (
logic s_tx_fifo_stall_d, s_tx_fifo_stall_q;
logic s_rx_fifo_stall_d, s_rx_fifo_stall_q;
// nmi
assign s_nmi_wr_hdshk = nmi.valid && (~s_nmi_ready_q) && (|nmi.wstrb);
assign s_nmi_rd_hdshk = nmi.valid && (~s_nmi_ready_q) && (~(|nmi.wstrb));
assign nmi.ready = s_nmi_ready_q;
assign nmi.rdata = s_nmi_rdata_q;
// rib
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
assign rib.ready = s_rib_ready_q;
assign rib.rdata = s_rib_rdata_q;
// reg
assign xpi_accmd_o = s_xpi_accmd_q;
assign xpi_mmstad_o = s_xpi_mmstad_q;
@@ -225,8 +225,8 @@ module xpi_reg (
assign dma_rx_stall_o = s_rx_fifo_stall_q;
assign s_xpi_cfgidx_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_CFGIDX;
assign s_xpi_cfgidx_d = nmi.wdata[`XPI_LNS_NUM-1:0];
assign s_xpi_cfgidx_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_CFGIDX;
assign s_xpi_cfgidx_d = rib.wdata[`XPI_LNS_NUM-1:0];
dffer #(`XPI_LNS_NUM) u_xpi_cfgidx_dffer (
clk_i,
rst_n_i,
@@ -237,8 +237,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ACCMD_BLOCK
assign s_xpi_accmd_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_ACCMD && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_accmd_d[i] = nmi.wdata[0];
assign s_xpi_accmd_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_ACCMD && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_accmd_d[i] = rib.wdata[0];
end
dfferm #(`XPI_NSS_NUM, 1, 1'b1) u_xpi_accmd_dfferm (
clk_i,
@@ -251,13 +251,13 @@ module xpi_reg (
// 5000_0000 - 5FFF_FFFF
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_MMSTAD_BLOCK
assign s_xpi_mmstad_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_MMSTAD && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_mmstad_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_MMSTAD && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
always_comb begin
s_xpi_mmstad_d[i] = s_xpi_mmstad_q[i];
if (nmi.wstrb[0]) s_xpi_mmstad_d[i][7:0] = nmi.wdata[7:0];
if (nmi.wstrb[1]) s_xpi_mmstad_d[i][15:8] = nmi.wdata[15:8];
if (nmi.wstrb[2]) s_xpi_mmstad_d[i][23:16] = nmi.wdata[23:16];
if (nmi.wstrb[3]) s_xpi_mmstad_d[i][31:24] = nmi.wdata[31:24];
if (rib.wstrb[0]) s_xpi_mmstad_d[i][7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_xpi_mmstad_d[i][15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_xpi_mmstad_d[i][23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_xpi_mmstad_d[i][31:24] = rib.wdata[31:24];
end
end
dfferm #(`XPI_NSS_NUM, 32, 32'd0) u_xpi_mmdstad_dfferm (
@@ -270,13 +270,13 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_MMOFFST_BLOCK
assign s_xpi_mmoffst_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_MMOFFST && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_mmoffst_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_MMOFFST && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
always_comb begin
s_xpi_mmoffst_d[i] = s_xpi_mmoffst_q[i];
if (nmi.wstrb[0]) s_xpi_mmoffst_d[i][7:0] = nmi.wdata[7:0];
if (nmi.wstrb[1]) s_xpi_mmoffst_d[i][15:8] = nmi.wdata[15:8];
if (nmi.wstrb[2]) s_xpi_mmoffst_d[i][23:16] = nmi.wdata[23:16];
if (nmi.wstrb[3]) s_xpi_mmoffst_d[i][31:24] = nmi.wdata[31:24];
if (rib.wstrb[0]) s_xpi_mmoffst_d[i][7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_xpi_mmoffst_d[i][15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_xpi_mmoffst_d[i][23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_xpi_mmoffst_d[i][31:24] = rib.wdata[31:24];
end
end
dfferm #(`XPI_NSS_NUM, 32, 32'h0200_0000) u_xpi_mmoffst_dfferm (
@@ -289,8 +289,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_MODE_BLOCK
assign s_xpi_mode_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_MODE && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_mode_d[i] = nmi.wdata[0];
assign s_xpi_mode_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_MODE && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_mode_d[i] = rib.wdata[0];
end
dfferm #(`XPI_NSS_NUM, 1, 1'b0) u_xpi_mode_dfferm (
clk_i,
@@ -301,8 +301,8 @@ module xpi_reg (
);
assign s_xpi_nss_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_NSS;
assign s_xpi_nss_d = nmi.wdata[`XPI_LNS_NUM-1:0];
assign s_xpi_nss_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_NSS;
assign s_xpi_nss_d = rib.wdata[`XPI_LNS_NUM-1:0];
dffer #(`XPI_LNS_NUM) u_xpi_nss_dffer (
clk_i,
rst_n_i,
@@ -313,8 +313,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_CLKDIV_BLOCK
assign s_xpi_clkdiv_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_CLKDIV && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_clkdiv_d[i] = nmi.wdata[7:0];
assign s_xpi_clkdiv_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_CLKDIV && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_clkdiv_d[i] = rib.wdata[7:0];
end
dfferm #(`XPI_NSS_NUM, 8, 8'd0) u_xpi_clkdiv_dfferm (
clk_i,
@@ -326,8 +326,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_RDWR_BLOCK
assign s_xpi_rdwr_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_RDWR && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_rdwr_d[i] = nmi.wdata[0];
assign s_xpi_rdwr_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_RDWR && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_rdwr_d[i] = rib.wdata[0];
end
dfferm #(`XPI_NSS_NUM, 1, 1'b1) u_xpi_rdwr_dfferm (
clk_i,
@@ -339,8 +339,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_REVDAT_BLOCK
assign s_xpi_revdat_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_REVDAT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_revdat_d[i] = nmi.wdata[0];
assign s_xpi_revdat_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_REVDAT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_revdat_d[i] = rib.wdata[0];
end
dfferm #(`XPI_NSS_NUM, 1, 1'b0) u_xpi_revdat_dfferm (
clk_i,
@@ -352,8 +352,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_TXUPB_BLOCK
assign s_xpi_txupb_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_TXUPB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_txupb_d[i] = nmi.wdata[7:0];
assign s_xpi_txupb_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_TXUPB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_txupb_d[i] = rib.wdata[7:0];
end
dfferm #(`XPI_NSS_NUM, 8, 8'd0) u_xpi_txupb_dfferm (
clk_i,
@@ -365,8 +365,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_TXLOWB_BLOCK
assign s_xpi_txlowb_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_TXLOWB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_txlowb_d[i] = nmi.wdata[7:0];
assign s_xpi_txlowb_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_TXLOWB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_txlowb_d[i] = rib.wdata[7:0];
end
dfferm #(`XPI_NSS_NUM, 8, 8'd0) u_xpi_txlowb_dfferm (
clk_i,
@@ -378,8 +378,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_RXUPB_BLOCK
assign s_xpi_rxupb_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_RXUPB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_rxupb_d[i] = nmi.wdata[5:0];
assign s_xpi_rxupb_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_RXUPB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_rxupb_d[i] = rib.wdata[5:0];
end
dfferm #(`XPI_NSS_NUM, 6, 6'd0) u_xpi_rxupb_dfferm (
clk_i,
@@ -391,8 +391,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_RXLOWB_BLOCK
assign s_xpi_rxlowb_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_RXLOWB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_rxlowb_d[i] = nmi.wdata[5:0];
assign s_xpi_rxlowb_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_RXLOWB && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_rxlowb_d[i] = rib.wdata[5:0];
end
dfferm #(`XPI_NSS_NUM, 6, 6'd0) u_xpi_rxlowb_dfferm (
clk_i,
@@ -403,13 +403,13 @@ module xpi_reg (
);
assign s_xpi_flush = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_FLUSH;
assign s_xpi_flush_val = nmi.wdata[0];
assign s_xpi_flush = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_FLUSH;
assign s_xpi_flush_val = rib.wdata[0];
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_CMDTYP_BLOCK
assign s_xpi_cmdtyp_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_CMDTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_cmdtyp_d[i] = nmi.wdata[1:0];
assign s_xpi_cmdtyp_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_CMDTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_cmdtyp_d[i] = rib.wdata[1:0];
end
dfferm #(`XPI_NSS_NUM, 2, 2'd1) u_xpi_cmdtyp_dfferm (
clk_i,
@@ -421,8 +421,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_CMDLEN_BLOCK
assign s_xpi_cmdlen_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_CMDLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_cmdlen_d[i] = nmi.wdata[2:0];
assign s_xpi_cmdlen_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_CMDLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_cmdlen_d[i] = rib.wdata[2:0];
end
dfferm #(`XPI_NSS_NUM, 3, 3'd1) u_xpi_cmdlen_dfferm (
clk_i,
@@ -434,13 +434,13 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_CMDDAT_BLOCK
assign s_xpi_cmddat_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_CMDDAT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_cmddat_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_CMDDAT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
always_comb begin
s_xpi_cmddat_d[i] = s_xpi_cmddat_q[i];
if (nmi.wstrb[0]) s_xpi_cmddat_d[i][7:0] = nmi.wdata[7:0];
if (nmi.wstrb[1]) s_xpi_cmddat_d[i][15:8] = nmi.wdata[15:8];
if (nmi.wstrb[2]) s_xpi_cmddat_d[i][23:16] = nmi.wdata[23:16];
if (nmi.wstrb[3]) s_xpi_cmddat_d[i][31:24] = nmi.wdata[31:24];
if (rib.wstrb[0]) s_xpi_cmddat_d[i][7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_xpi_cmddat_d[i][15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_xpi_cmddat_d[i][23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_xpi_cmddat_d[i][31:24] = rib.wdata[31:24];
end
end
dfferm #(`XPI_NSS_NUM, 32, 32'hEB00_0000) u_xpi_cmddat_dfferm (
@@ -453,8 +453,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ADRTYP_BLOCK
assign s_xpi_adrtyp_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_ADRTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_adrtyp_d[i] = nmi.wdata[1:0];
assign s_xpi_adrtyp_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_ADRTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_adrtyp_d[i] = rib.wdata[1:0];
end
dfferm #(`XPI_NSS_NUM, 2, 2'd3) u_xpi_adrtyp_dfferm (
clk_i,
@@ -466,8 +466,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ADRLEN_BLOCK
assign s_xpi_adrlen_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_ADRLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_adrlen_d[i] = nmi.wdata[2:0];
assign s_xpi_adrlen_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_ADRLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_adrlen_d[i] = rib.wdata[2:0];
end
dfferm #(`XPI_NSS_NUM, 3, 3'd4) u_xpi_adrlen_dfferm (
clk_i,
@@ -479,13 +479,13 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ADRDAT_BLOCK
assign s_xpi_adrdat_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_ADRDAT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_adrdat_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_ADRDAT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
always_comb begin
s_xpi_adrdat_d[i] = s_xpi_adrdat_q[i];
if (nmi.wstrb[0]) s_xpi_adrdat_d[i][7:0] = nmi.wdata[7:0];
if (nmi.wstrb[1]) s_xpi_adrdat_d[i][15:8] = nmi.wdata[15:8];
if (nmi.wstrb[2]) s_xpi_adrdat_d[i][23:16] = nmi.wdata[23:16];
if (nmi.wstrb[3]) s_xpi_adrdat_d[i][31:24] = nmi.wdata[31:24];
if (rib.wstrb[0]) s_xpi_adrdat_d[i][7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_xpi_adrdat_d[i][15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_xpi_adrdat_d[i][23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_xpi_adrdat_d[i][31:24] = rib.wdata[31:24];
end
end
dfferm #(`XPI_NSS_NUM, 32, 32'd0) u_xpi_adrdat_dfferm (
@@ -498,8 +498,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ALTTYP_BLOCK
assign s_xpi_alttyp_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_ALTTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_alttyp_d[i] = nmi.wdata[1:0];
assign s_xpi_alttyp_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_ALTTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_alttyp_d[i] = rib.wdata[1:0];
end
dfferm #(`XPI_NSS_NUM, 2, 2'd0) u_xpi_alttyp_dfferm (
clk_i,
@@ -511,8 +511,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ALTLEN_BLOCK
assign s_xpi_altlen_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_ALTLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_altlen_d[i] = nmi.wdata[2:0];
assign s_xpi_altlen_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_ALTLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_altlen_d[i] = rib.wdata[2:0];
end
dfferm #(`XPI_NSS_NUM, 3, 3'd0) u_xpi_altlen_dfferm (
clk_i,
@@ -524,13 +524,13 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ALTDAT_BLOCK
assign s_xpi_altdat_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_ALTDAT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_altdat_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_ALTDAT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
always_comb begin
s_xpi_altdat_d[i] = s_xpi_altdat_q[i];
if (nmi.wstrb[0]) s_xpi_altdat_d[i][7:0] = nmi.wdata[7:0];
if (nmi.wstrb[1]) s_xpi_altdat_d[i][15:8] = nmi.wdata[15:8];
if (nmi.wstrb[2]) s_xpi_altdat_d[i][23:16] = nmi.wdata[23:16];
if (nmi.wstrb[3]) s_xpi_altdat_d[i][31:24] = nmi.wdata[31:24];
if (rib.wstrb[0]) s_xpi_altdat_d[i][7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) s_xpi_altdat_d[i][15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) s_xpi_altdat_d[i][23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) s_xpi_altdat_d[i][31:24] = rib.wdata[31:24];
end
end
dfferm #(`XPI_NSS_NUM, 32, 32'd0) u_xpi_altdat_dfferm (
@@ -543,8 +543,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_TDULEN_BLOCK
assign s_xpi_tdulen_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_TDULEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_tdulen_d[i] = nmi.wdata[7:0];
assign s_xpi_tdulen_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_TDULEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_tdulen_d[i] = rib.wdata[7:0];
end
dfferm #(`XPI_NSS_NUM, 8, 8'd4) u_xpi_tdulen_dfferm (
clk_i,
@@ -556,8 +556,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_RDULEN_BLOCK
assign s_xpi_rdulen_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_RDULEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_rdulen_d[i] = nmi.wdata[7:0];
assign s_xpi_rdulen_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_RDULEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_rdulen_d[i] = rib.wdata[7:0];
end
dfferm #(`XPI_NSS_NUM, 8, 8'd4) u_xpi_rdulen_dfferm (
clk_i,
@@ -569,8 +569,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_DATTYP_BLOCK
assign s_xpi_dattyp_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_DATTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_dattyp_d[i] = nmi.wdata[1:0];
assign s_xpi_dattyp_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_DATTYP && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_dattyp_d[i] = rib.wdata[1:0];
end
dfferm #(`XPI_NSS_NUM, 2, 2'd3) u_xpi_dattyp_dfferm (
clk_i,
@@ -582,8 +582,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_DATLEN_BLOCK
assign s_xpi_datlen_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_DATLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_datlen_d[i] = nmi.wdata[7:0];
assign s_xpi_datlen_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_DATLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_datlen_d[i] = rib.wdata[7:0];
end
dfferm #(`XPI_NSS_NUM, 8, 8'd1) u_xpi_datlen_dfferm (
clk_i,
@@ -595,8 +595,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_DATBIT_BLOCK
assign s_xpi_datbit_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_DATBIT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_datbit_d[i] = nmi.wdata[2:0];
assign s_xpi_datbit_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_DATBIT && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_datbit_d[i] = rib.wdata[2:0];
end
dfferm #(`XPI_NSS_NUM, 3, 3'd4) u_xpi_datbit_dfferm (
clk_i,
@@ -608,8 +608,8 @@ module xpi_reg (
for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_HLVLEN_BLOCK
assign s_xpi_hlvlen_en[i] = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_HLVLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_hlvlen_d[i] = nmi.wdata[7:0];
assign s_xpi_hlvlen_en[i] = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_HLVLEN && `XPI_LNS_NUM'(i) == s_xpi_cfgidx_q;
assign s_xpi_hlvlen_d[i] = rib.wdata[7:0];
end
dfferm #(`XPI_NSS_NUM, 8, 8'd2) u_xpi_hlvlen_dfferm (
clk_i,
@@ -624,17 +624,17 @@ module xpi_reg (
always_comb begin
tx_push_valid_o = 1'b0;
tx_push_data_o = '0;
if (s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_TXDATA) begin
if (s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_TXDATA) begin
tx_push_valid_o = 1'b1;
if (nmi.wstrb[0]) tx_push_data_o[7:0] = nmi.wdata[7:0];
if (nmi.wstrb[1]) tx_push_data_o[15:8] = nmi.wdata[15:8];
if (nmi.wstrb[2]) tx_push_data_o[23:16] = nmi.wdata[23:16];
if (nmi.wstrb[3]) tx_push_data_o[31:24] = nmi.wdata[31:24];
if (rib.wstrb[0]) tx_push_data_o[7:0] = rib.wdata[7:0];
if (rib.wstrb[1]) tx_push_data_o[15:8] = rib.wdata[15:8];
if (rib.wstrb[2]) tx_push_data_o[23:16] = rib.wdata[23:16];
if (rib.wstrb[3]) tx_push_data_o[31:24] = rib.wdata[31:24];
end
end
// start
assign xfer_start_o = s_nmi_wr_hdshk && nmi.addr[7:0] == `NMI_XPI_XST;
assign xfer_start_o = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_XPI_XST;
// status
// [20:14] rx elem num
@@ -654,7 +654,7 @@ module xpi_reg (
s_xpi_status_d[20:14] = rx_elem_num_i;
if (xfer_done_i) begin
s_xpi_status_d[0] = 1'b1;
end else if (s_nmi_rd_hdshk && nmi.addr[7:0] == `NMI_XPI_STATUS) begin
end else if (s_rib_rd_hdshk && rib.addr[7:0] == `RIB_XPI_STATUS) begin
s_xpi_status_d[0] = 1'b0;
end
end
@@ -699,67 +699,67 @@ module xpi_reg (
);
// nmi rd
assign s_nmi_ready_d = nmi.valid && (~s_nmi_ready_q);
dffr #(1) u_nmi_ready_dffr (
// rib rd
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
dffr #(1) u_rib_ready_dffr (
clk_i,
rst_n_i,
s_nmi_ready_d,
s_nmi_ready_q
s_rib_ready_d,
s_rib_ready_q
);
// verilog_format: off
assign s_nmi_rdata_en = s_nmi_rd_hdshk;
assign s_rib_rdata_en = s_rib_rd_hdshk;
always_comb begin
rx_pop_valid_o = '0;
s_nmi_rdata_d = s_nmi_rdata_q;
unique case (nmi.addr[7:0])
`NMI_XPI_CFGIDX: s_nmi_rdata_d = {{(32 - `XPI_LNS_NUM) {1'b0}}, s_xpi_cfgidx_q};
`NMI_XPI_ACCMD: s_nmi_rdata_d = {31'd0, s_xpi_accmd_q[s_xpi_cfgidx_q]};
`NMI_XPI_MMSTAD: s_nmi_rdata_d = s_xpi_mmstad_q[s_xpi_cfgidx_q];
`NMI_XPI_MMOFFST: s_nmi_rdata_d = s_xpi_mmoffst_q[s_xpi_cfgidx_q];
`NMI_XPI_MODE: s_nmi_rdata_d = {31'd0, s_xpi_mode_q[s_xpi_cfgidx_q]};
`NMI_XPI_NSS: s_nmi_rdata_d = {{(32 - `XPI_LNS_NUM) {1'b0}}, s_xpi_nss_q};
`NMI_XPI_CLKDIV: s_nmi_rdata_d = {24'd0, s_xpi_clkdiv_q[s_xpi_cfgidx_q]};
`NMI_XPI_RDWR: s_nmi_rdata_d = {31'd0, s_xpi_rdwr_q[s_xpi_cfgidx_q]};
`NMI_XPI_REVDAT: s_nmi_rdata_d = {31'd0, s_xpi_revdat_q[s_xpi_cfgidx_q]};
`NMI_XPI_TXUPB: s_nmi_rdata_d = {24'd0, s_xpi_txupb_q[s_xpi_cfgidx_q]};
`NMI_XPI_TXLOWB: s_nmi_rdata_d = {24'd0, s_xpi_txlowb_q[s_xpi_cfgidx_q]};
`NMI_XPI_RXUPB: s_nmi_rdata_d = {26'd0, s_xpi_rxupb_q[s_xpi_cfgidx_q]};
`NMI_XPI_RXLOWB: s_nmi_rdata_d = {26'd0, s_xpi_rxlowb_q[s_xpi_cfgidx_q]};
`NMI_XPI_CMDTYP: s_nmi_rdata_d = {30'd0, s_xpi_cmdtyp_q[s_xpi_cfgidx_q]};
`NMI_XPI_CMDLEN: s_nmi_rdata_d = {29'd0, s_xpi_cmdlen_q[s_xpi_cfgidx_q]};
`NMI_XPI_CMDDAT: s_nmi_rdata_d = s_xpi_cmddat_q[s_xpi_cfgidx_q];
`NMI_XPI_ADRTYP: s_nmi_rdata_d = {30'd0, s_xpi_adrtyp_q[s_xpi_cfgidx_q]};
`NMI_XPI_ADRLEN: s_nmi_rdata_d = {29'd0, s_xpi_adrlen_q[s_xpi_cfgidx_q]};
`NMI_XPI_ADRDAT: s_nmi_rdata_d = s_xpi_adrdat_q[s_xpi_cfgidx_q];
`NMI_XPI_ALTTYP: s_nmi_rdata_d = {30'd0, s_xpi_alttyp_q[s_xpi_cfgidx_q]};
`NMI_XPI_ALTLEN: s_nmi_rdata_d = {29'd0, s_xpi_altlen_q[s_xpi_cfgidx_q]};
`NMI_XPI_ALTDAT: s_nmi_rdata_d = s_xpi_altdat_q[s_xpi_cfgidx_q];
`NMI_XPI_TDULEN: s_nmi_rdata_d = {24'd0, s_xpi_tdulen_q[s_xpi_cfgidx_q]};
`NMI_XPI_RDULEN: s_nmi_rdata_d = {24'd0, s_xpi_rdulen_q[s_xpi_cfgidx_q]};
`NMI_XPI_DATTYP: s_nmi_rdata_d = {30'd0, s_xpi_dattyp_q[s_xpi_cfgidx_q]};
`NMI_XPI_DATLEN: s_nmi_rdata_d = {24'd0, s_xpi_datlen_q[s_xpi_cfgidx_q]};
`NMI_XPI_DATBIT: s_nmi_rdata_d = {29'd0, s_xpi_datbit_q[s_xpi_cfgidx_q]};
`NMI_XPI_HLVLEN: s_nmi_rdata_d = {24'd0, s_xpi_hlvlen_q[s_xpi_cfgidx_q]};
`NMI_XPI_RXDATA: begin
if (s_nmi_rd_hdshk) begin
s_rib_rdata_d = s_rib_rdata_q;
unique case (rib.addr[7:0])
`RIB_XPI_CFGIDX: s_rib_rdata_d = {{(32 - `XPI_LNS_NUM) {1'b0}}, s_xpi_cfgidx_q};
`RIB_XPI_ACCMD: s_rib_rdata_d = {31'd0, s_xpi_accmd_q[s_xpi_cfgidx_q]};
`RIB_XPI_MMSTAD: s_rib_rdata_d = s_xpi_mmstad_q[s_xpi_cfgidx_q];
`RIB_XPI_MMOFFST: s_rib_rdata_d = s_xpi_mmoffst_q[s_xpi_cfgidx_q];
`RIB_XPI_MODE: s_rib_rdata_d = {31'd0, s_xpi_mode_q[s_xpi_cfgidx_q]};
`RIB_XPI_NSS: s_rib_rdata_d = {{(32 - `XPI_LNS_NUM) {1'b0}}, s_xpi_nss_q};
`RIB_XPI_CLKDIV: s_rib_rdata_d = {24'd0, s_xpi_clkdiv_q[s_xpi_cfgidx_q]};
`RIB_XPI_RDWR: s_rib_rdata_d = {31'd0, s_xpi_rdwr_q[s_xpi_cfgidx_q]};
`RIB_XPI_REVDAT: s_rib_rdata_d = {31'd0, s_xpi_revdat_q[s_xpi_cfgidx_q]};
`RIB_XPI_TXUPB: s_rib_rdata_d = {24'd0, s_xpi_txupb_q[s_xpi_cfgidx_q]};
`RIB_XPI_TXLOWB: s_rib_rdata_d = {24'd0, s_xpi_txlowb_q[s_xpi_cfgidx_q]};
`RIB_XPI_RXUPB: s_rib_rdata_d = {26'd0, s_xpi_rxupb_q[s_xpi_cfgidx_q]};
`RIB_XPI_RXLOWB: s_rib_rdata_d = {26'd0, s_xpi_rxlowb_q[s_xpi_cfgidx_q]};
`RIB_XPI_CMDTYP: s_rib_rdata_d = {30'd0, s_xpi_cmdtyp_q[s_xpi_cfgidx_q]};
`RIB_XPI_CMDLEN: s_rib_rdata_d = {29'd0, s_xpi_cmdlen_q[s_xpi_cfgidx_q]};
`RIB_XPI_CMDDAT: s_rib_rdata_d = s_xpi_cmddat_q[s_xpi_cfgidx_q];
`RIB_XPI_ADRTYP: s_rib_rdata_d = {30'd0, s_xpi_adrtyp_q[s_xpi_cfgidx_q]};
`RIB_XPI_ADRLEN: s_rib_rdata_d = {29'd0, s_xpi_adrlen_q[s_xpi_cfgidx_q]};
`RIB_XPI_ADRDAT: s_rib_rdata_d = s_xpi_adrdat_q[s_xpi_cfgidx_q];
`RIB_XPI_ALTTYP: s_rib_rdata_d = {30'd0, s_xpi_alttyp_q[s_xpi_cfgidx_q]};
`RIB_XPI_ALTLEN: s_rib_rdata_d = {29'd0, s_xpi_altlen_q[s_xpi_cfgidx_q]};
`RIB_XPI_ALTDAT: s_rib_rdata_d = s_xpi_altdat_q[s_xpi_cfgidx_q];
`RIB_XPI_TDULEN: s_rib_rdata_d = {24'd0, s_xpi_tdulen_q[s_xpi_cfgidx_q]};
`RIB_XPI_RDULEN: s_rib_rdata_d = {24'd0, s_xpi_rdulen_q[s_xpi_cfgidx_q]};
`RIB_XPI_DATTYP: s_rib_rdata_d = {30'd0, s_xpi_dattyp_q[s_xpi_cfgidx_q]};
`RIB_XPI_DATLEN: s_rib_rdata_d = {24'd0, s_xpi_datlen_q[s_xpi_cfgidx_q]};
`RIB_XPI_DATBIT: s_rib_rdata_d = {29'd0, s_xpi_datbit_q[s_xpi_cfgidx_q]};
`RIB_XPI_HLVLEN: s_rib_rdata_d = {24'd0, s_xpi_hlvlen_q[s_xpi_cfgidx_q]};
`RIB_XPI_RXDATA: begin
if (s_rib_rd_hdshk) begin
rx_pop_valid_o = 1'b1;
if (~rx_empty_i) s_nmi_rdata_d = rx_pop_data_i;
else s_nmi_rdata_d = '0;
if (~rx_empty_i) s_rib_rdata_d = rx_pop_data_i;
else s_rib_rdata_d = '0;
end
end
`NMI_XPI_STATUS: s_nmi_rdata_d = {11'd0, s_xpi_status_q};
default: s_nmi_rdata_d = s_nmi_rdata_q;
`RIB_XPI_STATUS: s_rib_rdata_d = {11'd0, s_xpi_status_q};
default: s_rib_rdata_d = s_rib_rdata_q;
endcase
end
// verilog_format: on
dffer #(32) u_nmi_rdata_dffer (
dffer #(32) u_rib_rdata_dffer (
clk_i,
rst_n_i,
s_nmi_rdata_en,
s_nmi_rdata_d,
s_nmi_rdata_q
s_rib_rdata_en,
s_rib_rdata_d,
s_rib_rdata_q
);
endmodule
rtl/ip/native/util/async_fifo.sv → rtl/ip/rib/util/async_fifo.sv
View File
File renamed without changes.
rtl/ip/native/util/fifo.sv → rtl/ip/rib/util/fifo.sv
View File
File renamed without changes.
rtl/mini/address_map/generate_memory_map.py
+2 -2
View File
@@ -12,7 +12,7 @@ from typing import Any
MAX_ADDRESS = 1 << 32
VALID_ROUTES = {"native", "apb", "ram", "reserved"}
VALID_ROUTES = {"rib", "apb", "ram", "reserved"}
VALID_KINDS = {"active", "reserved"}
VALID_USER_ACCESS = {"none", "ro", "rw"}
@@ -153,7 +153,7 @@ def render_rtl(
f"{range_expression(symbol, region['base'], region['end'])}",
]
lines.append("")
for route in ("native", "apb", "ram", "reserved"):
for route in ("rib", "apb", "ram", "reserved"):
selected = [
f"`SOC_ADDR_IS_{region['symbol']}(addr)"
for region in regions
rtl/mini/address_map/memory_map.json
+27 -27
View File
@@ -21,8 +21,8 @@
{"symbol": "PERF_USER_WAIT_HI", "offset": "0x50"},
{"symbol": "PERF_DMA_WAIT_LO", "offset": "0x54"},
{"symbol": "PERF_DMA_WAIT_HI", "offset": "0x58"},
{"symbol": "PERF_NATV_WAIT_LO", "offset": "0x5C"},
{"symbol": "PERF_NATV_WAIT_HI", "offset": "0x60"},
{"symbol": "PERF_RIB_WAIT_LO", "offset": "0x5C"},
{"symbol": "PERF_RIB_WAIT_HI", "offset": "0x60"},
{"symbol": "PERF_APB_WAIT_LO", "offset": "0x64"},
{"symbol": "PERF_APB_WAIT_HI", "offset": "0x68"},
{"symbol": "PERF_SDRAM_WAIT_LO", "offset": "0x6C"},
@@ -33,27 +33,27 @@
{"symbol": "PERF_FLASH_WAIT_HI", "offset": "0x80"}
],
"regions": [
{"symbol": "FLASH", "base": "0x00000000", "size": "0x01000000", "route": "native", "kind": "active", "public": true, "linker": "FLASH", "user_access": "ro"},
{"symbol": "NMI_GPIO", "base": "0x10000000", "size": "0x00001000", "route": "native", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "NMI_UART0", "base": "0x10001000", "size": "0x00001000", "route": "native", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "NMI_TIM0", "base": "0x10002000", "size": "0x00001000", "route": "native", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "NMI_TIM1", "base": "0x10003000", "size": "0x00001000", "route": "native", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "NMI_PSRAM", "base": "0x10004000", "size": "0x00001000", "route": "native", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "NMI_SPISD", "base": "0x10005000", "size": "0x00001000", "route": "native", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "NMI_I2C0", "base": "0x10006000", "size": "0x00001000", "route": "native", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "NMI_I2S", "base": "0x10007000", "size": "0x00001000", "route": "native", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "NMI_ONEWIRE", "base": "0x10008000", "size": "0x00001000", "route": "native", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "NMI_XPI", "base": "0x10009000", "size": "0x00001000", "route": "native", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "NMI_DMA", "base": "0x1000A000", "size": "0x00001000", "route": "native", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "NMI_SYSCTRL", "base": "0x1000B000", "size": "0x00001000", "route": "native", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "NMI_CLINT", "base": "0x1000C000", "size": "0x00001000", "route": "native", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "NMI_SDRAM", "base": "0x1000D000", "size": "0x00001000", "route": "native", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "NMI_DVP", "base": "0x1000E000", "size": "0x00001000", "route": "native", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "NMI_SDIO", "base": "0x1000F000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "NMI_OPIPSRAM", "base": "0x10010000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "NMI_I2C1", "base": "0x10011000", "size": "0x00001000", "route": "native", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "NMI_GA", "base": "0x10012000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "NMI_APU", "base": "0x10013000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "FLASH", "base": "0x00000000", "size": "0x01000000", "route": "rib", "kind": "active", "public": true, "linker": "FLASH", "user_access": "ro"},
{"symbol": "RIB_GPIO", "base": "0x10000000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIB_UART0", "base": "0x10001000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIB_TIM0", "base": "0x10002000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIB_TIM1", "base": "0x10003000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIB_PSRAM", "base": "0x10004000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIB_SPISD", "base": "0x10005000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIB_I2C0", "base": "0x10006000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIB_I2S", "base": "0x10007000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIB_ONEWIRE", "base": "0x10008000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIB_XPI", "base": "0x10009000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIB_DMA", "base": "0x1000A000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIB_SYSCTRL", "base": "0x1000B000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIB_CLINT", "base": "0x1000C000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIB_SDRAM", "base": "0x1000D000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "none"},
{"symbol": "RIB_DVP", "base": "0x1000E000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIB_SDIO", "base": "0x1000F000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "RIB_OPIPSRAM", "base": "0x10010000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "RIB_I2C1", "base": "0x10011000", "size": "0x00001000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "RIB_GA", "base": "0x10012000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "RIB_APU", "base": "0x10013000", "size": "0x00001000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "APB_ARCHINFO", "base": "0x20000000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "ro"},
{"symbol": "APB_RNG", "base": "0x20001000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "APB_UART1", "base": "0x20002000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "rw"},
@@ -65,10 +65,10 @@
{"symbol": "APB_TMR", "base": "0x20008000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "APB_USER_IP", "base": "0x2000F000", "size": "0x00001000", "route": "apb", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "SRAM", "base": "0x30000000", "size": "0x00020000", "route": "ram", "kind": "active", "public": true, "linker": "SRAM", "user_access": "rw"},
{"symbol": "SDRAM", "base": "0x38000000", "size": "0x02000000", "route": "native", "kind": "active", "public": true, "linker": "SDRAM", "user_access": "rw"},
{"symbol": "PSRAM", "base": "0x40000000", "size": "0x00800000", "route": "native", "kind": "active", "public": true, "linker": "PSRAM", "user_access": "rw"},
{"symbol": "SDRAM", "base": "0x38000000", "size": "0x02000000", "route": "rib", "kind": "active", "public": true, "linker": "SDRAM", "user_access": "rw"},
{"symbol": "PSRAM", "base": "0x40000000", "size": "0x00800000", "route": "rib", "kind": "active", "public": true, "linker": "PSRAM", "user_access": "rw"},
{"symbol": "OPIPSRAM", "base": "0x48000000", "size": "0x08000000", "route": "reserved", "kind": "reserved", "public": false, "user_access": "none"},
{"symbol": "XPI", "base": "0x50000000", "size": "0x10000000", "route": "native", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "SPISD", "base": "0x60000000", "size": "0x40000000", "route": "native", "kind": "active", "public": true, "user_access": "rw"}
{"symbol": "XPI", "base": "0x50000000", "size": "0x10000000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"},
{"symbol": "SPISD", "base": "0x60000000", "size": "0x40000000", "route": "rib", "kind": "active", "public": true, "user_access": "rw"}
]
}
rtl/mini/dv/sva/soc_protocol_sva.sv
+11 -11
View File
@@ -45,37 +45,37 @@ bind bus soc_bus_sva u_soc_bus_sva (
.arb_locked_i (s_mstr_lock_q),
.access_denied_i(s_access_denied),
.arb_owner_i (s_mstr_id_q),
.mgmt_valid_i (mgmt_nmi.valid),
.user_valid_i (user_nmi.valid),
.dma_valid_i (dma_nmi.valid)
.mgmt_valid_i (mgmt_rib.valid),
.user_valid_i (user_rib.valid),
.dma_valid_i (dma_rib.valid)
);
module soc_nmi2apb_sva #(
module soc_rib2apb_sva #(
parameter int NSLV = 1
) (
input logic clk_i,
input logic rst_n_i,
input logic [NSLV-1:0] psel_comb_i,
input logic [NSLV-1:0] psel_q_i,
input logic nmi_ready_i,
input logic rib_ready_i,
input logic xfer_ready_i
);
// Address regions are disjoint and only the registered select drives a response.
assert property (@(posedge clk_i) disable iff (!rst_n_i) $onehot0(psel_comb_i));
assert property (@(posedge clk_i) disable iff (!rst_n_i) $onehot0(psel_q_i));
assert property (@(posedge clk_i) disable iff (!rst_n_i) nmi_ready_i |-> xfer_ready_i);
assert property (@(posedge clk_i) disable iff (!rst_n_i) rib_ready_i |-> xfer_ready_i);
endmodule
bind nmi2apb soc_nmi2apb_sva #(
bind rib2apb soc_rib2apb_sva #(
.NSLV(NSLV)
) u_soc_nmi2apb_sva (
) u_soc_rib2apb_sva (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.psel_comb_i (s_psel_comb),
.psel_q_i (s_psel_q),
.nmi_ready_i (nmi.ready),
.rib_ready_i (rib.ready),
.xfer_ready_i(s_xfer_ready)
);
@@ -136,8 +136,8 @@ module soc_gpio_user_handoff_sva #(
endmodule
bind nmi_gpio soc_gpio_user_handoff_sva #(
.DATA_WIDTH(`NMI_GPIO_NUM)
bind rib_gpio soc_gpio_user_handoff_sva #(
.DATA_WIDTH(`RIB_GPIO_NUM)
) u_soc_gpio_user_handoff_sva (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
rtl/mini/filelist/commonip.fl
+2 -2
View File
@@ -1,9 +1,9 @@
/clusterip/common/rtl/interface/apb4_if.sv
/clusterip/common/rtl/interface/apb4_pure_if.sv
/clusterip/common/rtl/interface/ahbl_if.sv
/clusterip/common/rtl/interface/nmi_if.sv
/clusterip/common/rtl/interface/rib_if.sv
/clusterip/common/rtl/interface/ram_if.sv
/top/soc_nmi_if.sv
/top/soc_rib_if.sv
/clusterip/common/rtl/utils/register.sv
/clusterip/common/rtl/utils/lfsr.sv
/clusterip/common/rtl/utils/gray2bin.sv
rtl/mini/filelist/inc.fl
+7 -7
View File
@@ -16,11 +16,11 @@
+incdir+/clusterip/wdg/rtl
+incdir+/clusterip/crc/rtl
+incdir+/clusterip/timer/rtl
+incdir+/ip/native/interconnect
+incdir+/ip/native/util
+incdir+/ip/native/memory
+incdir+/ip/native/storage
+incdir+/ip/native/serial
+incdir+/ip/native/multimedia
+incdir+/ip/native/peripheral
+incdir+/ip/rib/interconnect
+incdir+/ip/rib/util
+incdir+/ip/rib/memory
+incdir+/ip/rib/storage
+incdir+/ip/rib/serial
+incdir+/ip/rib/multimedia
+incdir+/ip/rib/peripheral
+incdir+/third_party/model/sdram/
rtl/mini/filelist/ip.fl
+50 -50
View File
@@ -1,50 +1,50 @@
/ip/native/memory/psram_core.sv
/ip/native/memory/psram.sv
/ip/native/memory/opipsram.sv
/ip/native/memory/opipsram_core.sv
/ip/native/storage/spisd_init.sv
/ip/native/storage/spisd_read.sv
/ip/native/storage/spisd_write.sv
/ip/native/storage/spisd_reg.sv
/ip/native/storage/spisd_cache.sv
/ip/native/storage/spisd_core.sv
/ip/native/storage/spisd_data.sv
/ip/native/storage/spisd.sv
/ip/native/storage/sdio.sv
/ip/native/serial/i2c_core.sv
/ip/native/serial/i2c.sv
/ip/native/serial/i2s_reg.sv
/ip/native/serial/i2s_clkgen.sv
/ip/native/serial/i2s_recv.sv
/ip/native/serial/i2s_send.sv
/ip/native/serial/i2s_core.sv
/ip/native/serial/i2s.sv
/ip/native/serial/onewire_core.sv
/ip/native/serial/onewire.sv
/ip/native/storage/xpi_reg.sv
/ip/native/storage/xpi_mm.sv
/ip/native/storage/xpi_clkgen.sv
/ip/native/storage/xpi_core.sv
/ip/native/storage/xpi.sv
/ip/native/peripheral/dma_core.sv
/ip/native/peripheral/dma.sv
/ip/native/peripheral/pll_ctrl_if.sv
/ip/native/peripheral/sysctrl.sv
/ip/native/peripheral/clint.sv
/ip/native/memory/sdram_clkgen.sv
/ip/native/memory/sdram_reg.sv
/ip/native/memory/sdram_core.sv
/ip/native/memory/sdram.sv
/ip/native/multimedia/dvp_core.sv
/ip/native/multimedia/dvp.sv
/ip/native/peripheral/timer.sv
/ip/native/serial/uart.sv
/ip/native/peripheral/gpio.sv
/ip/native/interconnect/nmi2apb.sv
/ip/native/interconnect/ahbl2nmi.sv
/top/ahbl2soc_nmi.sv
/ip/native/interconnect/axi4l2nmi.sv
/ip/native/util/async_fifo.sv
/ip/native/util/fifo.sv
/ip/native/interconnect/nmi_regslice.sv
/ip/native/interconnect/nmi2nmi.sv
/ip/rib/memory/psram_core.sv
/ip/rib/memory/psram.sv
/ip/rib/memory/opipsram.sv
/ip/rib/memory/opipsram_core.sv
/ip/rib/storage/spisd_init.sv
/ip/rib/storage/spisd_read.sv
/ip/rib/storage/spisd_write.sv
/ip/rib/storage/spisd_reg.sv
/ip/rib/storage/spisd_cache.sv
/ip/rib/storage/spisd_core.sv
/ip/rib/storage/spisd_data.sv
/ip/rib/storage/spisd.sv
/ip/rib/storage/sdio.sv
/ip/rib/serial/i2c_core.sv
/ip/rib/serial/i2c.sv
/ip/rib/serial/i2s_reg.sv
/ip/rib/serial/i2s_clkgen.sv
/ip/rib/serial/i2s_recv.sv
/ip/rib/serial/i2s_send.sv
/ip/rib/serial/i2s_core.sv
/ip/rib/serial/i2s.sv
/ip/rib/serial/onewire_core.sv
/ip/rib/serial/onewire.sv
/ip/rib/storage/xpi_reg.sv
/ip/rib/storage/xpi_mm.sv
/ip/rib/storage/xpi_clkgen.sv
/ip/rib/storage/xpi_core.sv
/ip/rib/storage/xpi.sv
/ip/rib/peripheral/dma_core.sv
/ip/rib/peripheral/dma.sv
/ip/rib/peripheral/pll_ctrl_if.sv
/ip/rib/peripheral/sysctrl.sv
/ip/rib/peripheral/clint.sv
/ip/rib/memory/sdram_clkgen.sv
/ip/rib/memory/sdram_reg.sv
/ip/rib/memory/sdram_core.sv
/ip/rib/memory/sdram.sv
/ip/rib/multimedia/dvp_core.sv
/ip/rib/multimedia/dvp.sv
/ip/rib/peripheral/timer.sv
/ip/rib/serial/uart.sv
/ip/rib/peripheral/gpio.sv
/ip/rib/interconnect/rib2apb.sv
/ip/rib/interconnect/ahbl2rib.sv
/top/ahbl2soc_rib.sv
/ip/rib/interconnect/axi4l2rib.sv
/ip/rib/util/async_fifo.sv
/ip/rib/util/fifo.sv
/ip/rib/interconnect/rib_regslice.sv
/ip/rib/interconnect/rib2rib.sv
rtl/mini/filelist/top.fl
+2 -2
View File
@@ -1,11 +1,11 @@
/top/apb4_if_bridge.sv
/top/gpio_pad_bridge.sv
/top/soc_nmi_regslice.sv
/top/soc_rib_regslice.sv
/top/core_wrapper.sv
/top/retrosoc.sv
/top/retrosoc_asic.sv
/top/onchip_ram.sv
/top/ip_nmi_wrapper.sv
/top/ip_rib_wrapper.sv
/top/ip_apb_wrapper.sv
/top/bus.sv
/top/rcu.sv
rtl/mini/formal/bus_formal.sv
+41 -41
View File
@@ -15,7 +15,7 @@ module bus_formal_design (
output logic user_ready,
output logic dma_valid,
output logic dma_ready,
output logic natv_valid,
output logic rib_valid,
output logic apb_valid,
output logic fault_valid,
output logic fault_access,
@@ -23,11 +23,11 @@ module bus_formal_design (
output logic [ 1:0] arb_owner
);
soc_nmi_if mgmt_nmi ();
soc_nmi_if user_nmi ();
soc_nmi_if dma_nmi ();
nmi_if natv_nmi ();
nmi_if apb_nmi ();
soc_rib_if mgmt_rib ();
soc_rib_if user_rib ();
soc_rib_if dma_rib ();
rib_if rib ();
rib_if apb_rib ();
(* anyseq *)logic f_mgmt_valid;
(* anyseq *)logic [31:0] f_mgmt_addr;
@@ -41,8 +41,8 @@ module bus_formal_design (
(* anyseq *)logic [31:0] f_dma_addr;
(* anyseq *)logic [31:0] f_dma_wdata;
(* anyseq *)logic [ 3:0] f_dma_wstrb;
(* anyseq *)logic f_natv_ready;
(* anyseq *)logic [31:0] f_natv_rdata;
(* anyseq *)logic f_rib_ready;
(* anyseq *)logic [31:0] f_rib_rdata;
(* anyseq *)logic f_apb_ready;
(* anyseq *)logic [31:0] f_apb_rdata;
logic [31:0] fault_addr;
@@ -51,46 +51,46 @@ module bus_formal_design (
logic [ 1:0] fault_master;
logic user_idle;
assign mgmt_nmi.valid = f_mgmt_valid;
assign mgmt_nmi.addr = f_mgmt_addr;
assign mgmt_nmi.wdata = f_mgmt_wdata;
assign mgmt_nmi.wstrb = f_mgmt_wstrb;
assign user_nmi.valid = f_user_valid;
assign user_nmi.addr = f_user_addr;
assign user_nmi.wdata = f_user_wdata;
assign user_nmi.wstrb = f_user_wstrb;
assign dma_nmi.valid = f_dma_valid;
assign dma_nmi.addr = f_dma_addr;
assign dma_nmi.wdata = f_dma_wdata;
assign dma_nmi.wstrb = f_dma_wstrb;
assign natv_nmi.ready = f_natv_ready;
assign natv_nmi.rdata = f_natv_rdata;
assign apb_nmi.ready = f_apb_ready;
assign apb_nmi.rdata = f_apb_rdata;
assign mgmt_rib.valid = f_mgmt_valid;
assign mgmt_rib.addr = f_mgmt_addr;
assign mgmt_rib.wdata = f_mgmt_wdata;
assign mgmt_rib.wstrb = f_mgmt_wstrb;
assign user_rib.valid = f_user_valid;
assign user_rib.addr = f_user_addr;
assign user_rib.wdata = f_user_wdata;
assign user_rib.wstrb = f_user_wstrb;
assign dma_rib.valid = f_dma_valid;
assign dma_rib.addr = f_dma_addr;
assign dma_rib.wdata = f_dma_wdata;
assign dma_rib.wstrb = f_dma_wstrb;
assign rib.ready = f_rib_ready;
assign rib.rdata = f_rib_rdata;
assign apb_rib.ready = f_apb_ready;
assign apb_rib.rdata = f_apb_rdata;
assign mgmt_valid = mgmt_nmi.valid;
assign mgmt_addr = mgmt_nmi.addr;
assign mgmt_wstrb = mgmt_nmi.wstrb;
assign mgmt_ready = mgmt_nmi.ready;
assign user_valid = user_nmi.valid;
assign user_addr = user_nmi.addr;
assign user_wstrb = user_nmi.wstrb;
assign user_ready = user_nmi.ready;
assign dma_valid = dma_nmi.valid;
assign dma_ready = dma_nmi.ready;
assign natv_valid = natv_nmi.valid;
assign apb_valid = apb_nmi.valid;
assign mgmt_valid = mgmt_rib.valid;
assign mgmt_addr = mgmt_rib.addr;
assign mgmt_wstrb = mgmt_rib.wstrb;
assign mgmt_ready = mgmt_rib.ready;
assign user_valid = user_rib.valid;
assign user_addr = user_rib.addr;
assign user_wstrb = user_rib.wstrb;
assign user_ready = user_rib.ready;
assign dma_valid = dma_rib.valid;
assign dma_ready = dma_rib.ready;
assign rib_valid = rib.valid;
assign apb_valid = apb_rib.valid;
bus u_dut (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.mgmt_nmi (mgmt_nmi),
.user_nmi (user_nmi),
.dma_nmi (dma_nmi),
.mgmt_rib (mgmt_rib),
.user_rib (user_rib),
.dma_rib (dma_rib),
.user_bus_enable_i(1'b1),
.user_bus_idle_o (user_idle),
.natv_nmi (natv_nmi),
.apb_nmi (apb_nmi),
.rib (rib),
.apb_rib (apb_rib),
.apb_resp_err_i (1'b0),
.perf_enable_i (1'b0),
.perf_clear_i (1'b0),
rtl/mini/formal/bus_formal_props.v
+4 -4
View File
@@ -16,7 +16,7 @@ module bus_formal;
wire user_ready;
wire dma_valid;
wire dma_ready;
wire natv_valid;
wire rib_valid;
wire apb_valid;
wire fault_valid;
wire fault_access;
@@ -37,7 +37,7 @@ module bus_formal;
.user_ready (user_ready),
.dma_valid (dma_valid),
.dma_ready (dma_ready),
.natv_valid (natv_valid),
.rib_valid (rib_valid),
.apb_valid (apb_valid),
.fault_valid (fault_valid),
.fault_access(fault_access),
@@ -57,8 +57,8 @@ module bus_formal;
assume (user_wstrb == $past(user_wstrb));
end
if (rst_n_i) begin
assert (!(natv_valid && apb_valid));
assert (!(fault_valid && (natv_valid || apb_valid)));
assert (!(rib_valid && apb_valid));
assert (!(fault_valid && (rib_valid || apb_valid)));
if (fault_access) begin
assert (fault_valid);
end
rtl/mini/formal/generate_formal_filelist.py
+10 -10
View File
@@ -17,8 +17,8 @@ from filelist import FileList, write_filelist # noqa: E402
COMMON_RTL = ROOT / "rtl/managed/clusterip/common/rtl"
INTERCONNECT = ROOT / "rtl/ip/native/interconnect"
PERIPHERAL = ROOT / "rtl/ip/native/peripheral"
INTERCONNECT = ROOT / "rtl/ip/rib/interconnect"
PERIPHERAL = ROOT / "rtl/ip/rib/peripheral"
TOP = ROOT / "rtl/mini/top"
@@ -28,25 +28,25 @@ def target_defines(target: str) -> list[str]:
def source_files(target: str) -> list[Path]:
common = [
COMMON_RTL / "interface/nmi_if.sv",
COMMON_RTL / "interface/rib_if.sv",
COMMON_RTL / "utils/register.sv",
TOP / "soc_nmi_if.sv",
TOP / "soc_rib_if.sv",
]
if target == "bus":
return [
*common,
TOP / "soc_nmi_regslice.sv",
TOP / "soc_rib_regslice.sv",
TOP / "bus.sv",
SCRIPT_DIR / "bus_formal.sv",
]
if target == "nmi2apb":
if target == "rib2apb":
return [
COMMON_RTL / "interface/nmi_if.sv",
COMMON_RTL / "interface/rib_if.sv",
COMMON_RTL / "interface/apb4_pure_if.sv",
COMMON_RTL / "utils/register.sv",
COMMON_RTL / "utils/edge_det.sv",
INTERCONNECT / "nmi2apb.sv",
SCRIPT_DIR / "nmi2apb_formal.sv",
INTERCONNECT / "rib2apb.sv",
SCRIPT_DIR / "rib2apb_formal.sv",
]
if target == "sysctrl":
return [
@@ -104,7 +104,7 @@ def parse_args() -> argparse.Namespace:
parser = argparse.ArgumentParser(description=__doc__)
parser.add_argument(
"--target",
choices=("bus", "nmi2apb", "sysctrl", "pll_rcu", "gpio_user"),
choices=("bus", "rib2apb", "sysctrl", "pll_rcu", "gpio_user"),
required=True,
)
parser.add_argument("--output", type=Path, required=True)
rtl/mini/formal/gpio_user_formal.sv
+21 -21
View File
@@ -5,11 +5,11 @@ module gpio_user_formal_design (
input logic clk_i,
output logic rst_n_i,
output logic f_past_valid,
output logic nmi_valid,
output logic [31:0] nmi_addr,
output logic [31:0] nmi_wdata,
output logic [ 3:0] nmi_wstrb,
output logic nmi_ready,
output logic rib_valid,
output logic [31:0] rib_addr,
output logic [31:0] rib_wdata,
output logic [ 3:0] rib_wstrb,
output logic rib_ready,
output logic [31:0] gpio_di,
output logic [31:0] gpio_oe,
output logic [31:0] gpio_do,
@@ -24,14 +24,14 @@ module gpio_user_formal_design (
output logic [31:0] native_do
);
nmi_if nmi ();
rib_if rib ();
gpio_if gpio ();
user_gpio_if user_gpio ();
(* anyseq *)logic f_nmi_valid;
(* anyseq *)logic [31:0] f_nmi_addr;
(* anyseq *)logic [31:0] f_nmi_wdata;
(* anyseq *)logic [ 3:0] f_nmi_wstrb;
(* anyseq *)logic f_rib_valid;
(* anyseq *)logic [31:0] f_rib_addr;
(* anyseq *)logic [31:0] f_rib_wdata;
(* anyseq *)logic [ 3:0] f_rib_wstrb;
(* anyseq *)logic [31:0] f_gpio_di;
(* anyseq *)logic [31:0] f_alt0_do;
(* anyseq *)logic [31:0] f_alt0_oe;
@@ -40,10 +40,10 @@ module gpio_user_formal_design (
(* anyseq *)logic [31:0] f_user_do;
(* anyseq *)logic [31:0] f_user_oe;
assign nmi.valid = f_nmi_valid;
assign nmi.addr = f_nmi_addr;
assign nmi.wdata = f_nmi_wdata;
assign nmi.wstrb = f_nmi_wstrb;
assign rib.valid = f_rib_valid;
assign rib.addr = f_rib_addr;
assign rib.wdata = f_rib_wdata;
assign rib.wstrb = f_rib_wstrb;
assign gpio.di_i = f_gpio_di;
assign gpio.alt0_do_i = f_alt0_do;
assign gpio.alt0_oe_i = f_alt0_oe;
@@ -52,11 +52,11 @@ module gpio_user_formal_design (
assign user_gpio.do_o = f_user_do;
assign user_gpio.oe_o = f_user_oe;
assign nmi_valid = nmi.valid;
assign nmi_addr = nmi.addr;
assign nmi_wdata = nmi.wdata;
assign nmi_wstrb = nmi.wstrb;
assign nmi_ready = nmi.ready;
assign rib_valid = rib.valid;
assign rib_addr = rib.addr;
assign rib_wdata = rib.wdata;
assign rib_wstrb = rib.wstrb;
assign rib_ready = rib.ready;
assign gpio_di = gpio.di_i;
assign gpio_oe = gpio.oe_o;
assign gpio_do = gpio.do_o;
@@ -70,10 +70,10 @@ module gpio_user_formal_design (
assign native_oe = u_dut.s_gpio_native_oe;
assign native_do = u_dut.s_gpio_native_out;
nmi_gpio u_dut (
rib_gpio u_dut (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.nmi (nmi),
.rib (rib),
.gpio (gpio),
.user_gpio(user_gpio)
);
rtl/mini/formal/gpio_user_formal_props.v
+15 -15
View File
@@ -6,11 +6,11 @@ module gpio_user_formal;
(* anyseq *) (* gclk *)reg clk_i;
wire rst_n_i;
wire f_past_valid;
wire nmi_valid;
wire [31:0] nmi_addr;
wire [31:0] nmi_wdata;
wire [ 3:0] nmi_wstrb;
wire nmi_ready;
wire rib_valid;
wire [31:0] rib_addr;
wire [31:0] rib_wdata;
wire [ 3:0] rib_wstrb;
wire rib_ready;
wire [31:0] gpio_di;
wire [31:0] gpio_oe;
wire [31:0] gpio_do;
@@ -28,11 +28,11 @@ module gpio_user_formal;
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.f_past_valid(f_past_valid),
.nmi_valid (nmi_valid),
.nmi_addr (nmi_addr),
.nmi_wdata (nmi_wdata),
.nmi_wstrb (nmi_wstrb),
.nmi_ready (nmi_ready),
.rib_valid (rib_valid),
.rib_addr (rib_addr),
.rib_wdata (rib_wdata),
.rib_wstrb (rib_wstrb),
.rib_ready (rib_ready),
.gpio_di (gpio_di),
.gpio_oe (gpio_oe),
.gpio_do (gpio_do),
@@ -48,11 +48,11 @@ module gpio_user_formal;
);
always @(posedge clk_i) begin
if (f_past_valid && $past(rst_n_i && nmi_valid && !nmi_ready)) begin
assume (nmi_valid);
assume (nmi_addr == $past(nmi_addr));
assume (nmi_wdata == $past(nmi_wdata));
assume (nmi_wstrb == $past(nmi_wstrb));
if (f_past_valid && $past(rst_n_i && rib_valid && !rib_ready)) begin
assume (rib_valid);
assume (rib_addr == $past(rib_addr));
assume (rib_wdata == $past(rib_wdata));
assume (rib_wstrb == $past(rib_wstrb));
end
if (rst_n_i) begin
rtl/mini/formal/nmi2apb_formal.sv → rtl/mini/formal/rib2apb_formal.sv
+22 -22
View File
@@ -22,22 +22,22 @@ module formal_apb_slave (
endmodule
module nmi2apb_formal_design (
module rib2apb_formal_design (
input logic clk_i,
output logic rst_n_i,
output logic f_past_valid,
output logic nmi_valid,
output logic [31:0] nmi_addr,
output logic [31:0] nmi_wdata,
output logic [ 3:0] nmi_wstrb,
output logic nmi_ready,
output logic rib_valid,
output logic [31:0] rib_addr,
output logic [31:0] rib_wdata,
output logic [ 3:0] rib_wstrb,
output logic rib_ready,
output logic [ 9:0] psel_comb,
output logic [ 9:0] psel_q,
output logic xfer_ready,
output logic [ 1:0] fsm_q
);
nmi_if nmi ();
rib_if rib ();
apb4_pure_if archinfo ();
apb4_pure_if rng ();
apb4_pure_if uart ();
@@ -49,20 +49,20 @@ module nmi2apb_formal_design (
apb4_pure_if tmr ();
apb4_pure_if user_ip ();
(* anyseq *)logic f_nmi_valid;
(* anyseq *)logic [31:0] f_nmi_addr;
(* anyseq *)logic [31:0] f_nmi_wdata;
(* anyseq *)logic [ 3:0] f_nmi_wstrb;
(* anyseq *)logic f_rib_valid;
(* anyseq *)logic [31:0] f_rib_addr;
(* anyseq *)logic [31:0] f_rib_wdata;
(* anyseq *)logic [ 3:0] f_rib_wstrb;
assign nmi.valid = f_nmi_valid;
assign nmi.addr = f_nmi_addr;
assign nmi.wdata = f_nmi_wdata;
assign nmi.wstrb = f_nmi_wstrb;
assign nmi_valid = nmi.valid;
assign nmi_addr = nmi.addr;
assign nmi_wdata = nmi.wdata;
assign nmi_wstrb = nmi.wstrb;
assign nmi_ready = nmi.ready;
assign rib.valid = f_rib_valid;
assign rib.addr = f_rib_addr;
assign rib.wdata = f_rib_wdata;
assign rib.wstrb = f_rib_wstrb;
assign rib_valid = rib.valid;
assign rib_addr = rib.addr;
assign rib_wdata = rib.wdata;
assign rib_wstrb = rib.wstrb;
assign rib_ready = rib.ready;
formal_apb_slave u_archinfo_slave (.apb(archinfo));
formal_apb_slave u_rng_slave (.apb(rng));
@@ -75,10 +75,10 @@ module nmi2apb_formal_design (
formal_apb_slave u_tmr_slave (.apb(tmr));
formal_apb_slave u_user_ip_slave (.apb(user_ip));
nmi2apb u_dut (
rib2apb u_dut (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.nmi (nmi),
.rib (rib),
.archinfo(archinfo),
.rng (rng),
.uart (uart),
rtl/mini/formal/nmi2apb_formal_props.v → rtl/mini/formal/rib2apb_formal_props.v
+19 -19
View File
@@ -8,7 +8,7 @@
// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
module nmi2apb_formal;
module rib2apb_formal;
localparam [1:0] FSM_SETP = 2'd1;
localparam [1:0] FSM_ENAB = 2'd2;
@@ -16,25 +16,25 @@ module nmi2apb_formal;
(* anyseq *) (* gclk *)reg clk_i;
wire rst_n_i;
wire f_past_valid;
wire nmi_valid;
wire [31:0] nmi_addr;
wire [31:0] nmi_wdata;
wire [ 3:0] nmi_wstrb;
wire nmi_ready;
wire rib_valid;
wire [31:0] rib_addr;
wire [31:0] rib_wdata;
wire [ 3:0] rib_wstrb;
wire rib_ready;
wire [ 9:0] psel_comb;
wire [ 9:0] psel_q;
wire xfer_ready;
wire [ 1:0] fsm_q;
nmi2apb_formal_design u_design (
rib2apb_formal_design u_design (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.f_past_valid(f_past_valid),
.nmi_valid (nmi_valid),
.nmi_addr (nmi_addr),
.nmi_wdata (nmi_wdata),
.nmi_wstrb (nmi_wstrb),
.nmi_ready (nmi_ready),
.rib_valid (rib_valid),
.rib_addr (rib_addr),
.rib_wdata (rib_wdata),
.rib_wstrb (rib_wstrb),
.rib_ready (rib_ready),
.psel_comb (psel_comb),
.psel_q (psel_q),
.xfer_ready (xfer_ready),
@@ -42,17 +42,17 @@ module nmi2apb_formal;
);
always @(posedge clk_i) begin
if (f_past_valid && $past(rst_n_i && nmi_valid && !nmi_ready)) begin
assume (nmi_valid);
assume (nmi_addr == $past(nmi_addr));
assume (nmi_wdata == $past(nmi_wdata));
assume (nmi_wstrb == $past(nmi_wstrb));
if (f_past_valid && $past(rst_n_i && rib_valid && !rib_ready)) begin
assume (rib_valid);
assume (rib_addr == $past(rib_addr));
assume (rib_wdata == $past(rib_wdata));
assume (rib_wstrb == $past(rib_wstrb));
end
if (rst_n_i) begin
assert ($onehot0(psel_comb));
assert ($onehot0(psel_q));
if (nmi_ready) begin
if (rib_ready) begin
assert (xfer_ready);
assert (fsm_q == FSM_ENAB);
end
@@ -63,7 +63,7 @@ module nmi2apb_formal;
assert (fsm_q == FSM_ENAB);
assert (psel_q == $past(psel_q));
end
cover (fsm_q == FSM_ENAB && nmi_ready);
cover (fsm_q == FSM_ENAB && rib_ready);
end
end
rtl/mini/formal/sysctrl_formal.sv
+23 -23
View File
@@ -5,11 +5,11 @@ module sysctrl_formal_design (
input logic clk_i,
output logic rst_n_i,
output logic f_past_valid,
output logic nmi_valid,
output logic [31:0] nmi_addr,
output logic [31:0] nmi_wdata,
output logic [ 3:0] nmi_wstrb,
output logic nmi_ready,
output logic rib_valid,
output logic [31:0] rib_addr,
output logic [31:0] rib_wdata,
output logic [ 3:0] rib_wstrb,
output logic rib_ready,
output logic [ 7:0] ip_sel,
output logic [ 4:0] core_sel,
output logic [ 5:0] user_reset,
@@ -33,14 +33,14 @@ module sysctrl_formal_design (
output logic [31:0] fault_count
);
nmi_if nmi ();
rib_if rib ();
sysctrl_if sysctrl ();
pll_ctrl_if pll_ctrl ();
(* anyseq *)logic f_nmi_valid;
(* anyseq *)logic [31:0] f_nmi_addr;
(* anyseq *)logic [31:0] f_nmi_wdata;
(* anyseq *)logic [ 3:0] f_nmi_wstrb;
(* anyseq *)logic f_rib_valid;
(* anyseq *)logic [31:0] f_rib_addr;
(* anyseq *)logic [31:0] f_rib_wdata;
(* anyseq *)logic [ 3:0] f_rib_wstrb;
(* anyseq *)logic f_pll_req_ready;
(* anyseq *)logic [ 2:0] f_pll_active_sel;
(* anyseq *)logic f_pll_active_valid;
@@ -54,18 +54,18 @@ module sysctrl_formal_design (
(* anyseq *)logic [ 3:0] f_fault_wstrb;
(* anyseq *)logic f_fault_reserved;
assign nmi.valid = f_nmi_valid;
assign nmi.addr = f_nmi_addr;
assign nmi.wdata = f_nmi_wdata;
assign nmi.wstrb = f_nmi_wstrb;
assign rib.valid = f_rib_valid;
assign rib.addr = f_rib_addr;
assign rib.wdata = f_rib_wdata;
assign rib.wstrb = f_rib_wstrb;
assign sysctrl.user_bus_idle_i = 1'b1;
assign sysctrl.fault_access_i = 1'b0;
assign sysctrl.fault_master_i = '0;
assign sysctrl.fault_code_i = f_fault_reserved ? `SOC_NMI_RESP_RESERVED : `SOC_NMI_RESP_DECERR;
assign sysctrl.fault_code_i = f_fault_reserved ? `SOC_RIB_RESP_RESERVED : `SOC_RIB_RESP_DECERR;
assign sysctrl.perf_mgmt_wait_i = '0;
assign sysctrl.perf_user_wait_i = '0;
assign sysctrl.perf_dma_wait_i = '0;
assign sysctrl.perf_natv_wait_i = '0;
assign sysctrl.perf_rib_wait_i = '0;
assign sysctrl.perf_apb_wait_i = '0;
assign sysctrl.perf_sdram_wait_i = '0;
assign sysctrl.perf_psram_wait_i = '0;
@@ -79,11 +79,11 @@ module sysctrl_formal_design (
assign pll_ctrl.rsp_valid_i = f_pll_rsp_valid;
assign pll_ctrl.capable_i = f_pll_capable;
assign nmi_valid = nmi.valid;
assign nmi_addr = nmi.addr;
assign nmi_wdata = nmi.wdata;
assign nmi_wstrb = nmi.wstrb;
assign nmi_ready = nmi.ready;
assign rib_valid = rib.valid;
assign rib_addr = rib.addr;
assign rib_wdata = rib.wdata;
assign rib_wstrb = rib.wstrb;
assign rib_ready = rib.ready;
assign ip_sel = sysctrl.ip_sel_o;
assign core_sel = u_dut.s_sysctrl_coresel_q;
assign user_reset = u_dut.s_user_reset_q;
@@ -106,14 +106,14 @@ module sysctrl_formal_design (
assign fault_addr_q = u_dut.s_fault_addr_q;
assign fault_count = u_dut.s_fault_count_q;
nmi_sysctrl u_dut (
rib_sysctrl u_dut (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.fault_valid_i (f_fault_valid),
.fault_addr_i (f_fault_addr),
.fault_wstrb_i (f_fault_wstrb),
.fault_reserved_i(f_fault_reserved),
.nmi (nmi),
.rib (rib),
.sysctrl (sysctrl),
.pll_ctrl (pll_ctrl)
);
rtl/mini/formal/sysctrl_formal_props.v
+35 -35
View File
@@ -12,11 +12,11 @@ module sysctrl_formal;
(* anyseq *) (* gclk *)reg clk_i;
wire rst_n_i;
wire f_past_valid;
wire nmi_valid;
wire [31:0] nmi_addr;
wire [31:0] nmi_wdata;
wire [ 3:0] nmi_wstrb;
wire nmi_ready;
wire rib_valid;
wire [31:0] rib_addr;
wire [31:0] rib_wdata;
wire [ 3:0] rib_wstrb;
wire rib_ready;
wire [ 7:0] ip_sel;
wire [ 4:0] core_sel;
wire [ 5:0] user_reset;
@@ -43,11 +43,11 @@ module sysctrl_formal;
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.f_past_valid (f_past_valid),
.nmi_valid (nmi_valid),
.nmi_addr (nmi_addr),
.nmi_wdata (nmi_wdata),
.nmi_wstrb (nmi_wstrb),
.nmi_ready (nmi_ready),
.rib_valid (rib_valid),
.rib_addr (rib_addr),
.rib_wdata (rib_wdata),
.rib_wstrb (rib_wstrb),
.rib_ready (rib_ready),
.ip_sel (ip_sel),
.core_sel (core_sel),
.user_reset (user_reset),
@@ -72,11 +72,11 @@ module sysctrl_formal;
);
always @(posedge clk_i) begin
if (f_past_valid && $past(rst_n_i && nmi_valid && !nmi_ready)) begin
assume (nmi_valid);
assume (nmi_addr == $past(nmi_addr));
assume (nmi_wdata == $past(nmi_wdata));
assume (nmi_wstrb == $past(nmi_wstrb));
if (f_past_valid && $past(rst_n_i && rib_valid && !rib_ready)) begin
assume (rib_valid);
assume (rib_addr == $past(rib_addr));
assume (rib_wdata == $past(rib_wdata));
assume (rib_wstrb == $past(rib_wstrb));
end
if (rst_n_i && pll_rsp_valid) begin
assume (pll_busy);
@@ -84,47 +84,47 @@ module sysctrl_formal;
if (rst_n_i && f_past_valid) begin
if ($past(
rst_n_i && nmi_valid && !nmi_ready && nmi_wstrb[0] &&
nmi_addr[7:0] == 8'h00 && nmi_wdata[4:0] < 6 && user_reset == 6'h3f && !user_bus_enable
rst_n_i && rib_valid && !rib_ready && rib_wstrb[0] &&
rib_addr[7:0] == 8'h00 && rib_wdata[4:0] < 6 && user_reset == 6'h3f && !user_bus_enable
)) begin
assert (core_sel == $past(nmi_wdata[4:0]));
assert (core_sel == $past(rib_wdata[4:0]));
end
if ($past(
rst_n_i && nmi_valid && !nmi_ready && nmi_wstrb[0] &&
nmi_addr[7:0] == 8'h00 && nmi_wdata[4:0] >= 6
rst_n_i && rib_valid && !rib_ready && rib_wstrb[0] &&
rib_addr[7:0] == 8'h00 && rib_wdata[4:0] >= 6
)) begin
assert (core_sel == $past(core_sel));
assert (user_config_error);
end
if ($past(
rst_n_i && nmi_valid && !nmi_ready && nmi_wstrb[0] &&
nmi_addr[7:0] == SYSCTRL_USER_CORE_RESET_OFFSET &&
nmi_wdata[5:0] == 6'h3f
rst_n_i && rib_valid && !rib_ready && rib_wstrb[0] &&
rib_addr[7:0] == SYSCTRL_USER_CORE_RESET_OFFSET &&
rib_wdata[5:0] == 6'h3f
)) begin
assert (user_reset == 6'h3f);
assert (!user_bus_enable);
end
if ($past(
rst_n_i && nmi_valid && !nmi_ready && |nmi_wstrb &&
nmi_addr[7:0] == SYSCTRL_IPSEL_OFFSET
rst_n_i && rib_valid && !rib_ready && |rib_wstrb &&
rib_addr[7:0] == SYSCTRL_IPSEL_OFFSET
)) begin
assert (ip_sel == $past(nmi_wdata[7:0]));
assert (ip_sel == $past(rib_wdata[7:0]));
end
if ($past(
rst_n_i && nmi_valid && !nmi_ready && nmi_wstrb[0] &&
nmi_addr[7:0] == SYSCTRL_PLL_CFG_OFFSET
rst_n_i && rib_valid && !rib_ready && rib_wstrb[0] &&
rib_addr[7:0] == SYSCTRL_PLL_CFG_OFFSET
)) begin
assert (pll_cfg == $past(nmi_wdata[2:0]));
assert (pll_cfg == $past(rib_wdata[2:0]));
end
if ($past(
rst_n_i && nmi_valid && !nmi_ready && nmi_wstrb[0] && nmi_wdata[0] &&
nmi_addr[7:0] == SYSCTRL_PLL_CMD_OFFSET && !pll_busy && !pll_req_valid
rst_n_i && rib_valid && !rib_ready && rib_wstrb[0] && rib_wdata[0] &&
rib_addr[7:0] == SYSCTRL_PLL_CMD_OFFSET && !pll_busy && !pll_req_valid
)) begin
assert (pll_busy);
end
if ($past(
rst_n_i && nmi_valid && !nmi_ready && nmi_wstrb[0] && nmi_wdata[0] &&
nmi_addr[7:0] == SYSCTRL_PLL_CMD_OFFSET && pll_busy
rst_n_i && rib_valid && !rib_ready && rib_wstrb[0] && rib_wdata[0] &&
rib_addr[7:0] == SYSCTRL_PLL_CMD_OFFSET && pll_busy
)) begin
assert (pll_error);
if (!$past(pll_rsp_valid)) begin
@@ -143,8 +143,8 @@ module sysctrl_formal;
end
end
if ($past(
rst_n_i && nmi_valid && !nmi_ready && nmi_wstrb[0] && nmi_wdata[0] &&
nmi_addr[7:0] == SYSCTRL_FAULT_STATUS_OFFSET && !fault_valid
rst_n_i && rib_valid && !rib_ready && rib_wstrb[0] && rib_wdata[0] &&
rib_addr[7:0] == SYSCTRL_FAULT_STATUS_OFFSET && !fault_valid
)) begin
assert (!fault_pending);
end
rtl/mini/integration/README.md
+4 -4
View File
@@ -3,13 +3,13 @@
`soc_topology.json` is the source of truth for internal Mini SoC integration
that is not part of the software address-map ABI or the package pad map.
The topology generator validates native NMI and APB target ownership against
The topology generator validates rib RIB and APB target ownership against
`../address_map/memory_map.json` and emits generated SystemVerilog include
files for `ip_nmi_wrapper.sv`, `ip_apb_wrapper.sv`, `nmi2apb.sv`, and
files for `ip_rib_wrapper.sv`, `ip_apb_wrapper.sv`, `rib2apb.sv`, and
`retrosoc.sv`. The output retains scalar interface instances and ports, so it
does not depend on interface-array support in FPGA or netlist simulation tools.
The `native_targets` list uses stable response slots. Every active native
The `rib_targets` list uses stable response slots. Every active rib
memory-map region must appear exactly once. Disabled targets keep their slot
and interface declaration but cannot own an address region.
@@ -24,7 +24,7 @@ target is part of the fixed platform integration and its presence is checked
against the canonical memory map.
`irq_vector_width`, `irq_groups`, and `interrupts` define the complete core
interrupt topology. `nmi` and `apb` group entries declare the wrapper output
interrupt topology. `rib` and `apb` group entries declare the wrapper output
width and the associated `retrosoc.sv` signal. Every group bit must be present
exactly once, each core-vector bit must have one source, and sources are limited
to scalar signal references or one-bit constants. The generator emits the two
rtl/mini/integration/clock_reset_domains.json
+4 -4
View File
@@ -53,11 +53,11 @@
"reset": "s_dvp_pclk_rst_n_sync",
"reset_source": "rst_n_i",
"reset_primitive": "rst_sync",
"path": "rtl/ip/native/multimedia/dvp.sv",
"path": "rtl/ip/rib/multimedia/dvp.sv",
"instance": "u_dvp_pclk_rst_sync",
"sta": {
"source_port": "gpio_10_io_pad",
"pin": "u_retrosoc.u_ip_nmi_wrapper.u_nmi_dvp.u_dvp_pclk_clk_buf/clk_o",
"pin": "u_retrosoc.u_ip_rib_wrapper/u_rib_dvp.u_dvp_pclk_clk_buf/clk_o",
"period_ns": 41.666666667,
"async_group": "dvp"
}
@@ -85,7 +85,7 @@
"source": "system",
"destination": "dvp",
"primitive": "cdc_sync",
"path": "rtl/ip/native/multimedia/dvp.sv",
"path": "rtl/ip/rib/multimedia/dvp.sv",
"instance": "u_dvp_recven_cdc_sync"
},
{
@@ -93,7 +93,7 @@
"source": "dvp",
"destination": "system",
"primitive": "async_fifo",
"path": "rtl/ip/native/multimedia/dvp.sv",
"path": "rtl/ip/rib/multimedia/dvp.sv",
"instance": "u_rx_async_fifo"
}
]
rtl/mini/integration/generate_soc_topology.py
+75 -75
View File
@@ -16,21 +16,21 @@ from typing import Any
SV_IDENTIFIER_RE = re.compile(r"[A-Za-z_][A-Za-z0-9_]*$")
SV_REFERENCE_RE = re.compile(r"[A-Za-z_][A-Za-z0-9_]*(?:\.[A-Za-z_][A-Za-z0-9_]*)*(?:\[[0-9]+\])?$")
SV_CONSTANT_RE = re.compile(r"(?:1'[bB][01]|'[01])$")
FABRIC_LINK_NAMES = ("mgmt", "user", "dma", "native", "apb")
SOC_NMI_FABRIC_LINK_NAMES = ("mgmt", "user", "dma")
IRQ_GROUP_NAMES = ("nmi", "apb")
FABRIC_LINK_NAMES = ("mgmt", "user", "dma", "rib", "apb")
SOC_RIB_MASTER_LINK_NAMES = ("mgmt", "user", "dma")
IRQ_GROUP_NAMES = ("rib", "apb")
IRQ_VECTOR_WIDTH = 32
COMPATIBILITY_IRQ_BINDINGS = (
("clint_software", "nmi", 0, 0, "u_clint_if.sfr_irq_o"),
("clint_timer", "nmi", 1, 1, "u_clint_if.tmr_irq_o"),
("uart0", "nmi", 2, 2, "uart.irq_o"),
("timer0", "nmi", 3, 3, "s_tim0_irq"),
("timer1", "nmi", 4, 4, "s_tim1_irq"),
("psram", "nmi", 5, 5, "psram.irq_o"),
("spisd", "nmi", 6, 6, "spisd.irq_o"),
("i2c0", "nmi", 7, 7, "i2c0.irq_o"),
("i2s", "nmi", 8, 8, "i2s.irq_o"),
("xpi", "nmi", 9, 9, "xpi.irq_o"),
("clint_software", "rib", 0, 0, "u_clint_if.sfr_irq_o"),
("clint_timer", "rib", 1, 1, "u_clint_if.tmr_irq_o"),
("uart0", "rib", 2, 2, "uart.irq_o"),
("timer0", "rib", 3, 3, "s_tim0_irq"),
("timer1", "rib", 4, 4, "s_tim1_irq"),
("psram", "rib", 5, 5, "psram.irq_o"),
("spisd", "rib", 6, 6, "spisd.irq_o"),
("i2c0", "rib", 7, 7, "i2c0.irq_o"),
("i2s", "rib", 8, 8, "i2s.irq_o"),
("xpi", "rib", 9, 9, "xpi.irq_o"),
("uart1", "apb", 0, 10, "uart.irq_o"),
("pwm", "apb", 1, 11, "pwm.irq_o"),
("ps2", "apb", 2, 12, "ps2.irq_o"),
@@ -42,7 +42,7 @@ COMPATIBILITY_IRQ_BINDINGS = (
@dataclass(frozen=True)
class NativeTarget:
class RIBTarget:
slot: int
name: str
interface: str
@@ -174,76 +174,76 @@ def parse_regions(value: Any, field: str) -> tuple[str, ...]:
return regions
def parse_native_targets(
def parse_rib_targets(
value: Any, memory_regions: dict[str, dict[str, Any]]
) -> list[NativeTarget]:
) -> list[RIBTarget]:
if not isinstance(value, list) or not value:
raise ValueError("native_targets must be a non-empty list")
targets: list[NativeTarget] = []
raise ValueError("rib_targets must be a non-empty list")
targets: list[RIBTarget] = []
claimed_regions: set[str] = set()
names: set[str] = set()
interfaces: set[str] = set()
slots: set[int] = set()
for index, entry in enumerate(value):
target = require_object(entry, f"native_targets[{index}]")
target = require_object(entry, f"rib_targets[{index}]")
slot = target.get("slot")
if not isinstance(slot, int) or slot < 0:
raise ValueError(f"native_targets[{index}].slot must be a non-negative integer")
name = require_identifier(target.get("name"), f"native_targets[{index}].name")
raise ValueError(f"rib_targets[{index}].slot must be a non-negative integer")
name = require_identifier(target.get("name"), f"rib_targets[{index}].name")
interface = require_identifier(
target.get("interface"), f"native_targets[{index}].interface"
target.get("interface"), f"rib_targets[{index}].interface"
)
disabled = target.get("disabled", False)
if not isinstance(disabled, bool):
raise ValueError(f"native_targets[{index}].disabled must be boolean")
raise ValueError(f"rib_targets[{index}].disabled must be boolean")
if disabled:
if "regions" in target:
raise ValueError(f"native_targets[{index}] is disabled but declares regions")
raise ValueError(f"rib_targets[{index}] is disabled but declares regions")
regions: tuple[str, ...] = ()
else:
regions = parse_regions(target.get("regions"), f"native_targets[{index}].regions")
regions = parse_regions(target.get("regions"), f"rib_targets[{index}].regions")
for region_name in regions:
region = memory_regions.get(region_name)
if region is None:
raise ValueError(
f"native_targets[{index}] references unknown region {region_name}"
f"rib_targets[{index}] references unknown region {region_name}"
)
if region.get("route") != "native" or region.get("kind") != "active":
if region.get("route") != "rib" or region.get("kind") != "active":
raise ValueError(
f"native_targets[{index}] region {region_name} is not an active native region"
f"rib_targets[{index}] region {region_name} is not an active rib region"
)
if region_name in claimed_regions:
raise ValueError(f"native region {region_name} has multiple targets")
raise ValueError(f"rib region {region_name} has multiple targets")
claimed_regions.add(region_name)
if name in names:
raise ValueError(f"native target name {name} is duplicated")
raise ValueError(f"rib target name {name} is duplicated")
if interface in interfaces:
raise ValueError(f"native target interface {interface} is duplicated")
raise ValueError(f"rib target interface {interface} is duplicated")
if slot in slots:
raise ValueError(f"native target slot {slot} is duplicated")
raise ValueError(f"rib target slot {slot} is duplicated")
names.add(name)
interfaces.add(interface)
slots.add(slot)
targets.append(NativeTarget(slot, name, interface, regions, disabled))
targets.append(RIBTarget(slot, name, interface, regions, disabled))
ordered = sorted(targets, key=lambda item: item.slot)
if [target.slot for target in ordered] != list(range(len(ordered))):
raise ValueError("native target slots must be contiguous from zero")
active_native_regions = {
raise ValueError("rib target slots must be contiguous from zero")
active_rib_regions = {
symbol
for symbol, region in memory_regions.items()
if region.get("route") == "native" and region.get("kind") == "active"
if region.get("route") == "rib" and region.get("kind") == "active"
}
if claimed_regions != active_native_regions:
missing = sorted(active_native_regions - claimed_regions)
extra = sorted(claimed_regions - active_native_regions)
if claimed_regions != active_rib_regions:
missing = sorted(active_rib_regions - claimed_regions)
extra = sorted(claimed_regions - active_rib_regions)
details: list[str] = []
if missing:
details.append(f"missing {', '.join(missing)}")
if extra:
details.append(f"extra {', '.join(extra)}")
raise ValueError(
f"native target regions do not cover the memory map ({'; '.join(details)})"
f"rib target regions do not cover the memory map ({'; '.join(details)})"
)
return ordered
@@ -484,7 +484,7 @@ def validate_compatibility_irq_bindings(interrupts: list[Interrupt]) -> None:
def read_topology(
topology_path: Path, memory_map_path: Path
) -> tuple[
list[NativeTarget],
list[RIBTarget],
list[ApbTarget],
list[FabricLink],
list[GpioFunction],
@@ -506,7 +506,7 @@ def read_topology(
interrupts = parse_interrupts(document.get("interrupts"), irq_groups, irq_vector_width)
validate_compatibility_irq_bindings(interrupts)
return (
parse_native_targets(document.get("native_targets"), memory_regions),
parse_rib_targets(document.get("rib_targets"), memory_regions),
parse_apb_targets(document.get("apb_targets"), memory_regions),
parse_fabric_links(document.get("fabric_links")),
parse_gpio_functions(document.get("gpio_alt_functions"), gpio_pins),
@@ -516,21 +516,21 @@ def read_topology(
)
def render_nmi_interfaces(targets: list[NativeTarget]) -> str:
def render_rib_interfaces(targets: list[RIBTarget]) -> str:
lines = ["// Generated by rtl/mini/integration/generate_soc_topology.py; do not edit."]
lines.extend(f" nmi_if {target.interface} ();" for target in targets)
lines.extend(f" rib_if {target.interface} ();" for target in targets)
return "\n".join(lines) + "\n"
def render_region_select(region: str, memory_region: dict[str, Any]) -> str:
base = int(require_string(memory_region.get("base"), f"memory map region {region}.base"), 0)
if base == 0:
return f"(nmi.addr <= `SOC_ADDR_{region}_END)"
return f"`SOC_ADDR_IS_{region}(nmi.addr)"
return f"(rib.addr <= `SOC_ADDR_{region}_END)"
return f"`SOC_ADDR_IS_{region}(rib.addr)"
def render_nmi_routes(
targets: list[NativeTarget], memory_regions: dict[str, dict[str, Any]]
def render_rib_routes(
targets: list[RIBTarget], memory_regions: dict[str, dict[str, Any]]
) -> str:
count = len(targets)
lines = ["// Generated by rtl/mini/integration/generate_soc_topology.py; do not edit."]
@@ -556,13 +556,13 @@ def render_nmi_routes(
f"{render_region_select(region, memory_regions[region])};"
)
lines.append(
f" assign {target.interface}.valid = nmi.valid && (|s_{target.name}_region_sel);"
f" assign {target.interface}.valid = rib.valid && (|s_{target.name}_region_sel);"
)
lines.extend(
[
f" assign {target.interface}.addr = nmi.addr;",
f" assign {target.interface}.wdata = nmi.wdata;",
f" assign {target.interface}.wstrb = nmi.wstrb;",
f" assign {target.interface}.addr = rib.addr;",
f" assign {target.interface}.wdata = rib.wdata;",
f" assign {target.interface}.wstrb = rib.wstrb;",
f" assign s_slv_sel_d[{target.slot}] = {target.interface}.valid;",
f" assign s_slv_ready[{target.slot}] = {target.interface}.ready;",
f" assign s_slv_rdata[{target.slot}] = {target.interface}.rdata;",
@@ -578,13 +578,13 @@ def render_nmi_routes(
" s_slv_sel_q",
" );",
"",
" assign nmi.ready = |(s_slv_sel_q & s_slv_ready);",
" assign rib.ready = |(s_slv_sel_q & s_slv_ready);",
"",
" always_comb begin",
" nmi.rdata = '0;",
" rib.rdata = '0;",
f" for (int index = 0; index < {count}; index++) begin",
" if (s_slv_sel_q[index]) begin",
" nmi.rdata = nmi.rdata | s_slv_rdata[index];",
" rib.rdata = rib.rdata | s_slv_rdata[index];",
" end",
" end",
" end",
@@ -653,13 +653,13 @@ def render_apb_request_routes(targets: list[ApbTarget]) -> str:
for target in targets:
lines.extend(
[
f" assign {target.name}.paddr = nmi.addr;",
f" assign {target.name}.paddr = rib.addr;",
f" assign {target.name}.pprot = '0;",
f" assign {target.name}.psel = s_xfer_valid && `SOC_ADDR_IS_{target.region}(nmi.addr);",
f" assign {target.name}.psel = s_xfer_valid && `SOC_ADDR_IS_{target.region}(rib.addr);",
f" assign {target.name}.penable = s_fsm_q == FSM_ENAB;",
f" assign {target.name}.pwrite = |nmi.wstrb;",
f" assign {target.name}.pwdata = nmi.wdata;",
f" assign {target.name}.pstrb = nmi.wstrb;",
f" assign {target.name}.pwrite = |rib.wstrb;",
f" assign {target.name}.pwdata = rib.wdata;",
f" assign {target.name}.pstrb = rib.wstrb;",
"",
]
)
@@ -669,7 +669,7 @@ def render_apb_request_routes(targets: list[ApbTarget]) -> str:
def render_apb_select_routes(targets: list[ApbTarget]) -> str:
lines = ["// Generated by rtl/mini/integration/generate_soc_topology.py; do not edit."]
lines.extend(
f" assign s_psel_comb[{target.slot}] = `SOC_ADDR_IS_{target.region}(nmi.addr);"
f" assign s_psel_comb[{target.slot}] = `SOC_ADDR_IS_{target.region}(rib.addr);"
for target in targets
)
return "\n".join(lines) + "\n"
@@ -694,7 +694,7 @@ def render_apb_response_mux(targets: list[ApbTarget]) -> str:
def render_fabric_interfaces(links: list[FabricLink]) -> str:
lines = ["// Generated by rtl/mini/integration/generate_soc_topology.py; do not edit."]
lines.extend(
f" {'soc_nmi_if' if link.name in SOC_NMI_FABRIC_LINK_NAMES else 'nmi_if'} "
f" {'soc_rib_if' if link.name in SOC_RIB_MASTER_LINK_NAMES else 'rib_if'} "
f"{link.interface} ();"
for link in links
)
@@ -714,11 +714,11 @@ def render_fabric_connection(links: list[FabricLink], name: str, port: str) -> s
def render_bus_fabric_connections(links: list[FabricLink]) -> str:
port_names = {
"mgmt": "mgmt_nmi",
"user": "user_nmi",
"dma": "dma_nmi",
"native": "natv_nmi",
"apb": "apb_nmi",
"mgmt": "mgmt_rib",
"user": "user_rib",
"dma": "dma_rib",
"rib": "rib",
"apb": "apb_rib",
}
interfaces = {link.name: link.interface for link in links}
lines = ["// Generated by rtl/mini/integration/generate_soc_topology.py; do not edit."]
@@ -860,8 +860,8 @@ def generate(topology_path: Path, memory_map_path: Path, output_dir: Path) -> No
) = read_topology(topology_path, memory_map_path)
memory_regions = read_memory_regions(memory_map_path)
rtl_dir = output_dir / "rtl"
atomic_write(rtl_dir / "soc_nmi_interfaces.svh", render_nmi_interfaces(targets))
atomic_write(rtl_dir / "soc_nmi_routes.svh", render_nmi_routes(targets, memory_regions))
atomic_write(rtl_dir / "soc_rib_interfaces.svh", render_rib_interfaces(targets))
atomic_write(rtl_dir / "soc_rib_routes.svh", render_rib_routes(targets, memory_regions))
atomic_write(rtl_dir / "soc_apb_interfaces.svh", render_apb_interfaces(apb_targets))
atomic_write(rtl_dir / "soc_apb_bridges.svh", render_apb_bridges(apb_targets))
atomic_write(rtl_dir / "soc_apb_ports.svh", render_apb_ports(apb_targets))
@@ -873,21 +873,21 @@ def generate(topology_path: Path, memory_map_path: Path, output_dir: Path) -> No
atomic_write(rtl_dir / "soc_fabric_interfaces.svh", render_fabric_interfaces(fabric_links))
atomic_write(
rtl_dir / "soc_mgmt_core_wrapper_fabric.svh",
render_fabric_connection(fabric_links, "mgmt", "nmi"),
render_fabric_connection(fabric_links, "mgmt", "rib"),
)
atomic_write(
rtl_dir / "soc_user_core_fabric.svh",
render_fabric_connection(fabric_links, "user", "nmi"),
render_fabric_connection(fabric_links, "user", "rib"),
)
atomic_write(rtl_dir / "soc_bus_fabric.svh", render_bus_fabric_connections(fabric_links))
atomic_write(
rtl_dir / "soc_ip_nmi_wrapper_fabric.svh",
render_fabric_connection(fabric_links, "native", "nmi")
+ render_fabric_connection(fabric_links, "dma", "dma_nmi"),
rtl_dir / "soc_ip_rib_wrapper_fabric.svh",
render_fabric_connection(fabric_links, "rib", "rib")
+ render_fabric_connection(fabric_links, "dma", "dma_rib"),
)
atomic_write(
rtl_dir / "soc_ip_apb_wrapper_fabric.svh",
render_fabric_connection(fabric_links, "apb", "nmi"),
render_fabric_connection(fabric_links, "apb", "rib"),
)
atomic_write(rtl_dir / "soc_gpio_alt_bindings.svh", render_gpio_bindings(gpio_functions))
atomic_write(rtl_dir / "soc_irq_config.svh", render_irq_config(irq_vector_width, irq_groups))
rtl/mini/integration/generate_user_extensions.py
+14 -14
View File
@@ -118,7 +118,7 @@ def render_core_bindings(extensions: ExtensionMap) -> str:
for target in extensions.core_targets:
lines.extend(
[
f" nmi_if u_user_{target.slot}_nmi_if ();",
f" rib_if u_user_{target.slot}_rib_if ();",
f" logic [31:0] s_user_{target.slot}_irq;",
]
)
@@ -126,17 +126,17 @@ def render_core_bindings(extensions: ExtensionMap) -> str:
[
"",
" always_comb begin",
" nmi.valid = '0;",
" nmi.addr = '0;",
" nmi.wdata = '0;",
" nmi.wstrb = '0;",
" rib.valid = '0;",
" rib.addr = '0;",
" rib.wdata = '0;",
" rib.wstrb = '0;",
]
)
for target in extensions.core_targets:
lines.extend(
[
f" u_user_{target.slot}_nmi_if.rdata = '0;",
f" u_user_{target.slot}_nmi_if.ready = '0;",
f" u_user_{target.slot}_rib_if.rdata = '0;",
f" u_user_{target.slot}_rib_if.ready = '0;",
f" s_user_{target.slot}_irq = '0;",
]
)
@@ -145,12 +145,12 @@ def render_core_bindings(extensions: ExtensionMap) -> str:
lines.extend(
[
f" {extensions.core_selector_width}'d{target.slot}: begin",
f" nmi.valid = u_user_{target.slot}_nmi_if.valid;",
f" nmi.addr = u_user_{target.slot}_nmi_if.addr;",
f" nmi.wdata = u_user_{target.slot}_nmi_if.wdata;",
f" nmi.wstrb = u_user_{target.slot}_nmi_if.wstrb;",
f" u_user_{target.slot}_nmi_if.rdata = nmi.rdata;",
f" u_user_{target.slot}_nmi_if.ready = nmi.ready;",
f" rib.valid = u_user_{target.slot}_rib_if.valid;",
f" rib.addr = u_user_{target.slot}_rib_if.addr;",
f" rib.wdata = u_user_{target.slot}_rib_if.wdata;",
f" rib.wstrb = u_user_{target.slot}_rib_if.wstrb;",
f" u_user_{target.slot}_rib_if.rdata = rib.rdata;",
f" u_user_{target.slot}_rib_if.ready = rib.ready;",
f" s_user_{target.slot}_irq = irq_i;",
" end",
]
@@ -163,7 +163,7 @@ def render_core_bindings(extensions: ExtensionMap) -> str:
" .clk_i (clk_i),",
f" .rst_n_i(rst_n_i && ~core_reset_i[{target.slot}]),",
f" .irq_i (s_user_{target.slot}_irq),",
f" .nmi (u_user_{target.slot}_nmi_if)",
f" .rib (u_user_{target.slot}_rib_if)",
" );",
"",
]
rtl/mini/integration/soc_topology.json
+35 -35
View File
@@ -3,20 +3,20 @@
"gpio_pins": 32,
"irq_vector_width": 32,
"irq_groups": [
{"name": "nmi", "width": 10, "top_signal": "s_nmi_irq"},
{"name": "rib", "width": 10, "top_signal": "s_rib_irq"},
{"name": "apb", "width": 7, "top_signal": "s_apb_irq"}
],
"interrupts": [
{"name": "clint_software", "description": "CLINT machine software interrupt", "group": "nmi", "group_bit": 0, "core_bit": 0, "signal": "u_clint_if.sfr_irq_o"},
{"name": "clint_timer", "description": "CLINT machine timer interrupt", "group": "nmi", "group_bit": 1, "core_bit": 1, "signal": "u_clint_if.tmr_irq_o"},
{"name": "uart0", "description": "Native UART0 interrupt", "group": "nmi", "group_bit": 2, "core_bit": 2, "signal": "uart.irq_o"},
{"name": "timer0", "description": "Native timer0 interrupt", "group": "nmi", "group_bit": 3, "core_bit": 3, "signal": "s_tim0_irq"},
{"name": "timer1", "description": "Native timer1 interrupt", "group": "nmi", "group_bit": 4, "core_bit": 4, "signal": "s_tim1_irq"},
{"name": "psram", "description": "PSRAM controller interrupt", "group": "nmi", "group_bit": 5, "core_bit": 5, "signal": "psram.irq_o"},
{"name": "spisd", "description": "SPI SD controller interrupt", "group": "nmi", "group_bit": 6, "core_bit": 6, "signal": "spisd.irq_o"},
{"name": "i2c0", "description": "Native I2C0 interrupt", "group": "nmi", "group_bit": 7, "core_bit": 7, "signal": "i2c0.irq_o"},
{"name": "i2s", "description": "Native I2S interrupt", "group": "nmi", "group_bit": 8, "core_bit": 8, "signal": "i2s.irq_o"},
{"name": "xpi", "description": "XPI controller interrupt", "group": "nmi", "group_bit": 9, "core_bit": 9, "signal": "xpi.irq_o"},
{"name": "clint_software", "description": "CLINT machine software interrupt", "group": "rib", "group_bit": 0, "core_bit": 0, "signal": "u_clint_if.sfr_irq_o"},
{"name": "clint_timer", "description": "CLINT machine timer interrupt", "group": "rib", "group_bit": 1, "core_bit": 1, "signal": "u_clint_if.tmr_irq_o"},
{"name": "uart0", "description": "RIB UART0 interrupt", "group": "rib", "group_bit": 2, "core_bit": 2, "signal": "uart.irq_o"},
{"name": "timer0", "description": "RIB timer0 interrupt", "group": "rib", "group_bit": 3, "core_bit": 3, "signal": "s_tim0_irq"},
{"name": "timer1", "description": "RIB timer1 interrupt", "group": "rib", "group_bit": 4, "core_bit": 4, "signal": "s_tim1_irq"},
{"name": "psram", "description": "PSRAM controller interrupt", "group": "rib", "group_bit": 5, "core_bit": 5, "signal": "psram.irq_o"},
{"name": "spisd", "description": "SPI SD controller interrupt", "group": "rib", "group_bit": 6, "core_bit": 6, "signal": "spisd.irq_o"},
{"name": "i2c0", "description": "RIB I2C0 interrupt", "group": "rib", "group_bit": 7, "core_bit": 7, "signal": "i2c0.irq_o"},
{"name": "i2s", "description": "RIB I2S interrupt", "group": "rib", "group_bit": 8, "core_bit": 8, "signal": "i2s.irq_o"},
{"name": "xpi", "description": "XPI controller interrupt", "group": "rib", "group_bit": 9, "core_bit": 9, "signal": "xpi.irq_o"},
{"name": "uart1", "description": "APB UART1 interrupt", "group": "apb", "group_bit": 0, "core_bit": 10, "signal": "uart.irq_o"},
{"name": "pwm", "description": "APB PWM interrupt", "group": "apb", "group_bit": 1, "core_bit": 11, "signal": "pwm.irq_o"},
{"name": "ps2", "description": "APB PS2 interrupt", "group": "apb", "group_bit": 2, "core_bit": 12, "signal": "ps2.irq_o"},
@@ -25,32 +25,32 @@
{"name": "advanced_timer", "description": "APB advanced timer interrupt", "group": "apb", "group_bit": 5, "core_bit": 15, "signal": "u_tmr_if.irq_o"},
{"name": "reserved", "description": "Reserved interrupt slot", "group": "apb", "group_bit": 6, "core_bit": 16, "signal": "1'b0"}
],
"native_targets": [
{"slot": 0, "name": "uart0", "interface": "u_uart_nmi_if", "regions": ["NMI_UART0"]},
{"slot": 1, "name": "gpio", "interface": "u_gpio_nmi_if", "regions": ["NMI_GPIO"]},
{"slot": 2, "name": "tim0", "interface": "u_tim0_nmi_if", "regions": ["NMI_TIM0"]},
{"slot": 3, "name": "tim1", "interface": "u_tim1_nmi_if", "regions": ["NMI_TIM1"]},
{"slot": 4, "name": "psram", "interface": "u_psram_nmi_if", "regions": ["NMI_PSRAM", "PSRAM"]},
{"slot": 5, "name": "spisd", "interface": "u_spisd_nmi_if", "regions": ["NMI_SPISD", "SPISD"]},
{"slot": 6, "name": "i2c0", "interface": "u_i2c0_nmi_if", "regions": ["NMI_I2C0"]},
{"slot": 7, "name": "i2s", "interface": "u_i2s_nmi_if", "regions": ["NMI_I2S"]},
{"slot": 8, "name": "onewire", "interface": "u_onewire_nmi_if", "regions": ["NMI_ONEWIRE"]},
{"slot": 9, "name": "xpi", "interface": "u_xpi_nmi_if", "regions": ["NMI_XPI", "FLASH", "XPI"]},
{"slot": 10, "name": "dma", "interface": "u_dma_nmi_if", "regions": ["NMI_DMA"]},
{"slot": 11, "name": "sysctrl", "interface": "u_sysctrl_nmi_if", "regions": ["NMI_SYSCTRL"]},
{"slot": 12, "name": "clint", "interface": "u_clint_nmi_if", "regions": ["NMI_CLINT"]},
{"slot": 13, "name": "sdram", "interface": "u_sdram_nmi_if", "regions": ["NMI_SDRAM", "SDRAM"]},
{"slot": 14, "name": "dvp", "interface": "u_dvp_nmi_if", "regions": ["NMI_DVP"]},
{"slot": 15, "name": "sdio", "interface": "u_sdio_nmi_if", "disabled": true},
{"slot": 16, "name": "opipsram", "interface": "u_opipsram_nmi_if", "disabled": true},
{"slot": 17, "name": "i2c1", "interface": "u_i2c1_nmi_if", "regions": ["NMI_I2C1"]}
"rib_targets": [
{"slot": 0, "name": "uart0", "interface": "u_uart_rib_if", "regions": ["RIB_UART0"]},
{"slot": 1, "name": "gpio", "interface": "u_gpio_rib_if", "regions": ["RIB_GPIO"]},
{"slot": 2, "name": "tim0", "interface": "u_tim0_rib_if", "regions": ["RIB_TIM0"]},
{"slot": 3, "name": "tim1", "interface": "u_tim1_rib_if", "regions": ["RIB_TIM1"]},
{"slot": 4, "name": "psram", "interface": "u_psram_rib_if", "regions": ["RIB_PSRAM", "PSRAM"]},
{"slot": 5, "name": "spisd", "interface": "u_spisd_rib_if", "regions": ["RIB_SPISD", "SPISD"]},
{"slot": 6, "name": "i2c0", "interface": "u_i2c0_rib_if", "regions": ["RIB_I2C0"]},
{"slot": 7, "name": "i2s", "interface": "u_i2s_rib_if", "regions": ["RIB_I2S"]},
{"slot": 8, "name": "onewire", "interface": "u_onewire_rib_if", "regions": ["RIB_ONEWIRE"]},
{"slot": 9, "name": "xpi", "interface": "u_xpi_rib_if", "regions": ["RIB_XPI", "FLASH", "XPI"]},
{"slot": 10, "name": "dma", "interface": "u_dma_rib_if", "regions": ["RIB_DMA"]},
{"slot": 11, "name": "sysctrl", "interface": "u_sysctrl_rib_if", "regions": ["RIB_SYSCTRL"]},
{"slot": 12, "name": "clint", "interface": "u_clint_rib_if", "regions": ["RIB_CLINT"]},
{"slot": 13, "name": "sdram", "interface": "u_sdram_rib_if", "regions": ["RIB_SDRAM", "SDRAM"]},
{"slot": 14, "name": "dvp", "interface": "u_dvp_rib_if", "regions": ["RIB_DVP"]},
{"slot": 15, "name": "sdio", "interface": "u_sdio_rib_if", "disabled": true},
{"slot": 16, "name": "opipsram", "interface": "u_opipsram_rib_if", "disabled": true},
{"slot": 17, "name": "i2c1", "interface": "u_i2c1_rib_if", "regions": ["RIB_I2C1"]}
],
"fabric_links": [
{"name": "mgmt", "interface": "u_mgmt_nmi_if"},
{"name": "user", "interface": "u_user_nmi_if"},
{"name": "dma", "interface": "u_dma_nmi_if"},
{"name": "native", "interface": "u_nmi_nmi_if"},
{"name": "apb", "interface": "u_apb_nmi_if"}
{"name": "mgmt", "interface": "u_mgmt_rib_if"},
{"name": "user", "interface": "u_user_rib_if"},
{"name": "dma", "interface": "u_dma_rib_if"},
{"name": "rib", "interface": "u_rib_if"},
{"name": "apb", "interface": "u_apb_rib_if"}
],
"apb_targets": [
{"slot": 0, "name": "archinfo", "timed_interface": "u_archinfo_apb_if", "pure_interface": "u_archinfo_apb_pure_if", "region": "APB_ARCHINFO"},
rtl/mini/mk/formal.mk
+11 -11
View File
@@ -6,14 +6,14 @@ FORMAL_SOLVER_DIR := $(FORMAL_DIR)/bin
FORMAL_SOLVER_WRAPPER := $(FORMAL_SOLVER_DIR)/bitwuzla
FORMAL_DEPTH ?= 20
FORMAL_TIMEOUT ?= 60
FORMAL_TARGETS := bus nmi2apb sysctrl pll_rcu gpio_user
FORMAL_TARGETS := bus rib2apb sysctrl pll_rcu gpio_user
FORMAL_FILELIST_GENERATOR := $(RTL_PATH)/formal/generate_formal_filelist.py
FORMAL_SBY_GENERATOR := $(RTL_PATH)/formal/generate_sby_config.py
FORMAL_RESULT_GENERATOR := $(RTL_PATH)/formal/formal_results.py
FORMAL_SOURCE_FILES := $(RTL_PATH)/formal/bus_formal.sv \
$(RTL_PATH)/formal/bus_formal_props.v \
$(RTL_PATH)/formal/nmi2apb_formal.sv \
$(RTL_PATH)/formal/nmi2apb_formal_props.v \
$(RTL_PATH)/formal/rib2apb_formal.sv \
$(RTL_PATH)/formal/rib2apb_formal_props.v \
$(RTL_PATH)/formal/sysctrl_formal.sv \
$(RTL_PATH)/formal/sysctrl_formal_props.v \
$(RTL_PATH)/formal/pll_rcu_formal.sv \
@@ -21,13 +21,13 @@ FORMAL_SOURCE_FILES := $(RTL_PATH)/formal/bus_formal.sv \
$(RTL_PATH)/formal/gpio_user_formal.sv \
$(RTL_PATH)/formal/gpio_user_formal_props.v \
$(RTL_PATH)/top/bus.sv \
$(ROOT_PATH)/rtl/ip/native/interconnect/nmi2apb.sv \
$(ROOT_PATH)/rtl/ip/native/interconnect/nmi_regslice.sv \
$(ROOT_PATH)/rtl/ip/native/peripheral/gpio.sv \
$(ROOT_PATH)/rtl/ip/native/peripheral/pll_ctrl_if.sv \
$(ROOT_PATH)/rtl/ip/native/peripheral/sysctrl.sv \
$(ROOT_PATH)/rtl/ip/rib/interconnect/rib2apb.sv \
$(ROOT_PATH)/rtl/ip/rib/interconnect/rib_regslice.sv \
$(ROOT_PATH)/rtl/ip/rib/peripheral/gpio.sv \
$(ROOT_PATH)/rtl/ip/rib/peripheral/pll_ctrl_if.sv \
$(ROOT_PATH)/rtl/ip/rib/peripheral/sysctrl.sv \
$(RTL_PATH)/top/rcu.sv \
$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/interface/nmi_if.sv \
$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/interface/rib_if.sv \
$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/interface/apb4_pure_if.sv \
$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv \
$(ROOT_PATH)/rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv \
@@ -105,7 +105,7 @@ formal: $(FORMAL_RESULT) | manifest
formal-bus: $(FORMAL_DIR)/bus/.stamp | manifest
formal-nmi2apb: $(FORMAL_DIR)/nmi2apb/.stamp | manifest
formal-rib2apb: $(FORMAL_DIR)/rib2apb/.stamp | manifest
formal-sysctrl: $(FORMAL_DIR)/sysctrl/.stamp | manifest
@@ -119,4 +119,4 @@ formal-doctor:
formal-clean:
python3 $(ROOT_PATH)/scripts/clean.py --root $(ROOT_PATH) --path $(FORMAL_DIR)
.PHONY: formal formal-bus formal-nmi2apb formal-sysctrl formal-pll-rcu formal-gpio-user formal-doctor formal-clean
.PHONY: formal formal-bus formal-rib2apb formal-sysctrl formal-pll-rcu formal-gpio-user formal-doctor formal-clean
rtl/mini/top/ahbl2soc_nmi.sv → rtl/mini/top/ahbl2soc_rib.sv
+28 -28
View File
@@ -8,13 +8,13 @@
// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`include "soc_nmi_defs.svh"
`include "soc_rib_defs.svh"
// Management-core AHB-Lite to SoC NMI bridge. It is intentionally separate
// from the managed-compatible ahbl2nmi used by externally supplied user cores.
module ahbl2soc_nmi (
// Management-core AHB-Lite to SoC RIB bridge. It is intentionally separate
// from the managed-compatible ahbl2rib used by externally supplied user cores.
module ahbl2soc_rib (
ahbl_if.slave ahbl,
soc_nmi_if.master nmi
soc_rib_if.master rib
);
localparam logic [1:0] AHBL_TRANS_NSEQ = 2'b10;
@@ -31,49 +31,49 @@ module ahbl2soc_nmi (
logic s_hwrite_d, s_hwrite_q;
logic [2:0] s_hsize_d, s_hsize_q;
assign ahbl.hready = s_fsm_q == STATE_IDLE || nmi.ready;
assign ahbl.hresp = nmi.ready && nmi.resp_err ? AHBL_RESP_ERROR : AHBL_RESP_OKAY;
assign ahbl.hrdata = nmi.rdata;
assign nmi.valid = s_fsm_q != STATE_IDLE;
assign nmi.addr = {s_haddr_q[31:2], 2'b00};
assign ahbl.hready = s_fsm_q == STATE_IDLE || rib.ready;
assign ahbl.hresp = rib.ready && rib.resp_err ? AHBL_RESP_ERROR : AHBL_RESP_OKAY;
assign ahbl.hrdata = rib.rdata;
assign rib.valid = s_fsm_q != STATE_IDLE;
assign rib.addr = {s_haddr_q[31:2], 2'b00};
always_comb begin
nmi.wstrb = '0;
nmi.wdata = '0;
rib.wstrb = '0;
rib.wdata = '0;
if (s_hwrite_q) begin
unique case (s_hsize_q)
AHBL_SIZE_BYTE: begin
unique case (s_haddr_q[1:0])
2'd0: begin
nmi.wstrb = 4'b0001;
nmi.wdata = {24'd0, ahbl.hwdata[7:0]};
rib.wstrb = 4'b0001;
rib.wdata = {24'd0, ahbl.hwdata[7:0]};
end
2'd1: begin
nmi.wstrb = 4'b0010;
nmi.wdata = {16'd0, ahbl.hwdata[7:0], 8'd0};
rib.wstrb = 4'b0010;
rib.wdata = {16'd0, ahbl.hwdata[7:0], 8'd0};
end
2'd2: begin
nmi.wstrb = 4'b0100;
nmi.wdata = {8'd0, ahbl.hwdata[7:0], 16'd0};
rib.wstrb = 4'b0100;
rib.wdata = {8'd0, ahbl.hwdata[7:0], 16'd0};
end
default: begin
nmi.wstrb = 4'b1000;
nmi.wdata = {ahbl.hwdata[7:0], 24'd0};
rib.wstrb = 4'b1000;
rib.wdata = {ahbl.hwdata[7:0], 24'd0};
end
endcase
end
AHBL_SIZE_HWRD: begin
if (s_haddr_q[1]) begin
nmi.wstrb = 4'b1100;
nmi.wdata = {ahbl.hwdata[15:0], 16'd0};
rib.wstrb = 4'b1100;
rib.wdata = {ahbl.hwdata[15:0], 16'd0};
end else begin
nmi.wstrb = 4'b0011;
nmi.wdata = {16'd0, ahbl.hwdata[15:0]};
rib.wstrb = 4'b0011;
rib.wdata = {16'd0, ahbl.hwdata[15:0]};
end
end
default: begin
nmi.wstrb = 4'b1111;
nmi.wdata = ahbl.hwdata;
rib.wstrb = 4'b1111;
rib.wdata = ahbl.hwdata;
end
endcase
end
@@ -94,7 +94,7 @@ module ahbl2soc_nmi (
end
end
STATE_DATA: begin
if (!nmi.ready) begin
if (!rib.ready) begin
s_fsm_d = STATE_WAIT;
end else if (ahbl.htrans == AHBL_TRANS_NSEQ) begin
s_haddr_d = ahbl.haddr;
@@ -105,7 +105,7 @@ module ahbl2soc_nmi (
end
end
STATE_WAIT: begin
if (nmi.ready) begin
if (rib.ready) begin
if (ahbl.htrans == AHBL_TRANS_NSEQ) begin
s_fsm_d = STATE_DATA;
s_haddr_d = ahbl.haddr;
rtl/mini/top/bus.sv
+119 -116
View File
@@ -9,36 +9,36 @@
// See the Mulan PSL v2 for more details.
`include "mmap_define.svh"
`include "soc_nmi_defs.svh"
`include "soc_rib_defs.svh"
module bus (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
input logic clk_i,
input logic rst_n_i,
`ifdef HAVE_SRAM_IF
ram_if.master ram,
ram_if.master ram,
`endif
soc_nmi_if.slave mgmt_nmi,
soc_nmi_if.slave user_nmi,
soc_nmi_if.slave dma_nmi,
input logic user_bus_enable_i,
output logic user_bus_idle_o,
nmi_if.master natv_nmi,
nmi_if.master apb_nmi,
input logic apb_resp_err_i,
input logic perf_enable_i,
input logic perf_clear_i,
output logic fault_valid_o,
output logic [31:0] fault_addr_o,
output logic [3:0] fault_wstrb_o,
output logic fault_reserved_o,
output logic fault_access_o,
output logic [1:0] fault_master_o,
output logic [2:0] fault_code_o,
soc_rib_if.slave mgmt_rib,
soc_rib_if.slave user_rib,
soc_rib_if.slave dma_rib,
input logic user_bus_enable_i,
output logic user_bus_idle_o,
rib_if.master rib,
rib_if.master apb_rib,
input logic apb_resp_err_i,
input logic perf_enable_i,
input logic perf_clear_i,
output logic fault_valid_o,
output logic [31:0] fault_addr_o,
output logic [3:0] fault_wstrb_o,
output logic fault_reserved_o,
output logic fault_access_o,
output logic [1:0] fault_master_o,
output logic [2:0] fault_code_o,
output logic [63:0] perf_mgmt_wait_o,
output logic [63:0] perf_user_wait_o,
output logic [63:0] perf_dma_wait_o,
output logic [63:0] perf_natv_wait_o,
output logic [63:0] perf_rib_wait_o,
output logic [63:0] perf_apb_wait_o,
output logic [63:0] perf_sdram_wait_o,
output logic [63:0] perf_psram_wait_o,
@@ -50,7 +50,7 @@ module bus (
localparam logic [1:0] MSTR_USER = 2'd1;
localparam logic [1:0] MSTR_DMA = 2'd2;
logic s_natv_sel, s_apb_sel, s_ram_sel, s_fault_sel, s_access_denied;
logic s_rib_sel, s_apb_sel, s_ram_sel, s_fault_sel, s_access_denied;
logic s_target_resp_err, s_rsp_err, s_rsp_ready, s_fault_event;
logic [2:0] s_rsp_code;
logic s_ram_valid, s_ram_ready;
@@ -59,19 +59,19 @@ module bus (
logic [1:0] s_mstr_rr_d, s_mstr_rr_q;
logic s_user_request;
logic s_user_access_allowed;
soc_nmi_if u_mstr_nmi_if ();
soc_nmi_if u_mstr_rgsl_nmi_if ();
soc_rib_if u_mstr_rib_if ();
soc_rib_if u_mstr_rgsl_rib_if ();
logic [63:0] s_perf_mgmt_wait_d, s_perf_mgmt_wait_q;
logic [63:0] s_perf_user_wait_d, s_perf_user_wait_q;
logic [63:0] s_perf_dma_wait_d, s_perf_dma_wait_q;
logic [63:0] s_perf_natv_wait_d, s_perf_natv_wait_q;
logic [63:0] s_perf_rib_wait_d, s_perf_rib_wait_q;
logic [63:0] s_perf_apb_wait_d, s_perf_apb_wait_q;
logic [63:0] s_perf_sdram_wait_d, s_perf_sdram_wait_q;
logic [63:0] s_perf_psram_wait_d, s_perf_psram_wait_q;
logic [63:0] s_perf_flash_wait_d, s_perf_flash_wait_q;
assign s_user_request = user_bus_enable_i && user_nmi.valid;
assign s_user_request = user_bus_enable_i && user_rib.valid;
assign user_bus_idle_o = ~s_mstr_lock_q || s_mstr_id_q != MSTR_USER;
always_comb begin
@@ -81,13 +81,13 @@ module bus (
if (~s_mstr_lock_q) begin
unique case (s_mstr_rr_q)
MSTR_MGMT: begin
if (mgmt_nmi.valid) begin
if (mgmt_rib.valid) begin
s_mstr_lock_d = 1'b1;
s_mstr_id_d = MSTR_MGMT;
end else if (s_user_request) begin
s_mstr_lock_d = 1'b1;
s_mstr_id_d = MSTR_USER;
end else if (dma_nmi.valid) begin
end else if (dma_rib.valid) begin
s_mstr_lock_d = 1'b1;
s_mstr_id_d = MSTR_DMA;
end
@@ -96,19 +96,19 @@ module bus (
if (s_user_request) begin
s_mstr_lock_d = 1'b1;
s_mstr_id_d = MSTR_USER;
end else if (dma_nmi.valid) begin
end else if (dma_rib.valid) begin
s_mstr_lock_d = 1'b1;
s_mstr_id_d = MSTR_DMA;
end else if (mgmt_nmi.valid) begin
end else if (mgmt_rib.valid) begin
s_mstr_lock_d = 1'b1;
s_mstr_id_d = MSTR_MGMT;
end
end
default: begin
if (dma_nmi.valid) begin
if (dma_rib.valid) begin
s_mstr_lock_d = 1'b1;
s_mstr_id_d = MSTR_DMA;
end else if (mgmt_nmi.valid) begin
end else if (mgmt_rib.valid) begin
s_mstr_lock_d = 1'b1;
s_mstr_id_d = MSTR_MGMT;
end else if (s_user_request) begin
@@ -117,7 +117,7 @@ module bus (
end
end
endcase
end else if (u_mstr_nmi_if.ready) begin
end else if (u_mstr_rib_if.ready) begin
s_mstr_lock_d = 1'b0;
unique case (s_mstr_id_q)
MSTR_MGMT: s_mstr_rr_d = MSTR_USER;
@@ -147,97 +147,100 @@ module bus (
// The owner is locked from request acceptance through its response.
// verilog_format: off
assign u_mstr_nmi_if.valid = s_mstr_lock_q && (s_mstr_id_q == MSTR_MGMT ? mgmt_nmi.valid :
s_mstr_id_q == MSTR_USER ? user_nmi.valid :
dma_nmi.valid);
assign u_mstr_nmi_if.addr = s_mstr_id_q == MSTR_MGMT ? mgmt_nmi.addr :
s_mstr_id_q == MSTR_USER ? user_nmi.addr : dma_nmi.addr;
assign u_mstr_nmi_if.wdata = s_mstr_id_q == MSTR_MGMT ? mgmt_nmi.wdata :
s_mstr_id_q == MSTR_USER ? user_nmi.wdata : dma_nmi.wdata;
assign u_mstr_nmi_if.wstrb = s_mstr_id_q == MSTR_MGMT ? mgmt_nmi.wstrb :
s_mstr_id_q == MSTR_USER ? user_nmi.wstrb : dma_nmi.wstrb;
assign u_mstr_rib_if.valid = s_mstr_lock_q && (s_mstr_id_q == MSTR_MGMT ? mgmt_rib.valid :
s_mstr_id_q == MSTR_USER ? user_rib.valid :
dma_rib.valid);
assign u_mstr_rib_if.addr = s_mstr_id_q == MSTR_MGMT ? mgmt_rib.addr :
s_mstr_id_q == MSTR_USER ? user_rib.addr :
dma_rib.addr;
assign u_mstr_rib_if.wdata = s_mstr_id_q == MSTR_MGMT ? mgmt_rib.wdata :
s_mstr_id_q == MSTR_USER ? user_rib.wdata :
dma_rib.wdata;
assign u_mstr_rib_if.wstrb = s_mstr_id_q == MSTR_MGMT ? mgmt_rib.wstrb :
s_mstr_id_q == MSTR_USER ? user_rib.wstrb :
dma_rib.wstrb;
assign mgmt_nmi.ready = s_mstr_lock_q && s_mstr_id_q == MSTR_MGMT ? u_mstr_nmi_if.ready : '0;
assign mgmt_nmi.rdata = s_mstr_lock_q && s_mstr_id_q == MSTR_MGMT ? u_mstr_nmi_if.rdata : '0;
assign mgmt_nmi.resp_err = s_mstr_lock_q && s_mstr_id_q == MSTR_MGMT ? u_mstr_nmi_if.resp_err : 1'b0;
assign mgmt_nmi.resp_code = s_mstr_lock_q && s_mstr_id_q == MSTR_MGMT ? u_mstr_nmi_if.resp_code : `SOC_NMI_RESP_OK;
assign user_nmi.ready = s_mstr_lock_q && s_mstr_id_q == MSTR_USER ? u_mstr_nmi_if.ready : '0;
assign user_nmi.rdata = s_mstr_lock_q && s_mstr_id_q == MSTR_USER ? u_mstr_nmi_if.rdata : '0;
assign user_nmi.resp_err = s_mstr_lock_q && s_mstr_id_q == MSTR_USER ? u_mstr_nmi_if.resp_err : 1'b0;
assign user_nmi.resp_code = s_mstr_lock_q && s_mstr_id_q == MSTR_USER ? u_mstr_nmi_if.resp_code : `SOC_NMI_RESP_OK;
assign dma_nmi.ready = s_mstr_lock_q && s_mstr_id_q == MSTR_DMA ? u_mstr_nmi_if.ready : '0;
assign dma_nmi.rdata = s_mstr_lock_q && s_mstr_id_q == MSTR_DMA ? u_mstr_nmi_if.rdata : '0;
assign dma_nmi.resp_err = s_mstr_lock_q && s_mstr_id_q == MSTR_DMA ? u_mstr_nmi_if.resp_err : 1'b0;
assign dma_nmi.resp_code = s_mstr_lock_q && s_mstr_id_q == MSTR_DMA ? u_mstr_nmi_if.resp_code : `SOC_NMI_RESP_OK;
assign mgmt_rib.ready = s_mstr_lock_q && s_mstr_id_q == MSTR_MGMT ? u_mstr_rib_if.ready : '0;
assign mgmt_rib.rdata = s_mstr_lock_q && s_mstr_id_q == MSTR_MGMT ? u_mstr_rib_if.rdata : '0;
assign mgmt_rib.resp_err = s_mstr_lock_q && s_mstr_id_q == MSTR_MGMT ? u_mstr_rib_if.resp_err : 1'b0;
assign mgmt_rib.resp_code = s_mstr_lock_q && s_mstr_id_q == MSTR_MGMT ? u_mstr_rib_if.resp_code : `SOC_RIB_RESP_OK;
assign user_rib.ready = s_mstr_lock_q && s_mstr_id_q == MSTR_USER ? u_mstr_rib_if.ready : '0;
assign user_rib.rdata = s_mstr_lock_q && s_mstr_id_q == MSTR_USER ? u_mstr_rib_if.rdata : '0;
assign user_rib.resp_err = s_mstr_lock_q && s_mstr_id_q == MSTR_USER ? u_mstr_rib_if.resp_err : 1'b0;
assign user_rib.resp_code = s_mstr_lock_q && s_mstr_id_q == MSTR_USER ? u_mstr_rib_if.resp_code : `SOC_RIB_RESP_OK;
assign dma_rib.ready = s_mstr_lock_q && s_mstr_id_q == MSTR_DMA ? u_mstr_rib_if.ready : '0;
assign dma_rib.rdata = s_mstr_lock_q && s_mstr_id_q == MSTR_DMA ? u_mstr_rib_if.rdata : '0;
assign dma_rib.resp_err = s_mstr_lock_q && s_mstr_id_q == MSTR_DMA ? u_mstr_rib_if.resp_err : 1'b0;
assign dma_rib.resp_code = s_mstr_lock_q && s_mstr_id_q == MSTR_DMA ? u_mstr_rib_if.resp_code : `SOC_RIB_RESP_OK;
// verilog_format: on
soc_nmi_regslice u_soc_nmi_regslice (
soc_rib_regslice u_soc_rib_regslice (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.nmi_slv(u_mstr_nmi_if),
.nmi_mst(u_mstr_rgsl_nmi_if)
.rib_slv(u_mstr_rib_if),
.rib_mst(u_mstr_rgsl_rib_if)
);
assign s_user_access_allowed = |u_mstr_rgsl_nmi_if.wstrb ?
`SOC_USER_ADDR_WRITABLE(u_mstr_rgsl_nmi_if.addr) :
`SOC_USER_ADDR_READABLE(u_mstr_rgsl_nmi_if.addr);
assign s_access_denied = u_mstr_rgsl_nmi_if.valid && s_mstr_id_q == MSTR_USER &&
assign s_user_access_allowed = |u_mstr_rgsl_rib_if.wstrb ?
`SOC_USER_ADDR_WRITABLE(u_mstr_rgsl_rib_if.addr) :
`SOC_USER_ADDR_READABLE(u_mstr_rgsl_rib_if.addr);
assign s_access_denied = u_mstr_rgsl_rib_if.valid && s_mstr_id_q == MSTR_USER &&
~s_user_access_allowed;
// Address ownership comes from the generated address map. User requests are
// filtered before any target observes valid.
// verilog_format: off
assign s_natv_sel = `SOC_ADDR_IS_NATIVE(u_mstr_rgsl_nmi_if.addr) && ~s_access_denied;
assign natv_nmi.valid = u_mstr_rgsl_nmi_if.valid && s_natv_sel;
assign natv_nmi.addr = u_mstr_rgsl_nmi_if.addr;
assign natv_nmi.wdata = u_mstr_rgsl_nmi_if.wdata;
assign natv_nmi.wstrb = u_mstr_rgsl_nmi_if.wstrb;
assign s_rib_sel = `SOC_ADDR_IS_RIB(u_mstr_rgsl_rib_if.addr) && ~s_access_denied;
assign rib.valid = u_mstr_rgsl_rib_if.valid && s_rib_sel;
assign rib.addr = u_mstr_rgsl_rib_if.addr;
assign rib.wdata = u_mstr_rgsl_rib_if.wdata;
assign rib.wstrb = u_mstr_rgsl_rib_if.wstrb;
assign s_apb_sel = `SOC_ADDR_IS_APB(u_mstr_rgsl_nmi_if.addr) && ~s_access_denied;
assign apb_nmi.valid = u_mstr_rgsl_nmi_if.valid && s_apb_sel;
assign apb_nmi.addr = u_mstr_rgsl_nmi_if.addr;
assign apb_nmi.wdata = u_mstr_rgsl_nmi_if.wdata;
assign apb_nmi.wstrb = u_mstr_rgsl_nmi_if.wstrb;
assign s_apb_sel = `SOC_ADDR_IS_APB(u_mstr_rgsl_rib_if.addr) && ~s_access_denied;
assign apb_rib.valid = u_mstr_rgsl_rib_if.valid && s_apb_sel;
assign apb_rib.addr = u_mstr_rgsl_rib_if.addr;
assign apb_rib.wdata = u_mstr_rgsl_rib_if.wdata;
assign apb_rib.wstrb = u_mstr_rgsl_rib_if.wstrb;
`ifdef HAVE_SRAM_IF
assign s_ram_sel = `SOC_ADDR_IS_RAM(u_mstr_rgsl_nmi_if.addr) && ~s_access_denied;
assign s_ram_valid = u_mstr_rgsl_nmi_if.valid && s_ram_sel;
assign ram.addr = u_mstr_rgsl_nmi_if.addr[16:2];
assign ram.wdata = u_mstr_rgsl_nmi_if.wdata;
assign ram.wstrb = s_ram_valid ? u_mstr_rgsl_nmi_if.wstrb : '0;
assign s_ram_sel = `SOC_ADDR_IS_RAM(u_mstr_rgsl_rib_if.addr) && ~s_access_denied;
assign s_ram_valid = u_mstr_rgsl_rib_if.valid && s_ram_sel;
assign ram.addr = u_mstr_rgsl_rib_if.addr[16:2];
assign ram.wdata = u_mstr_rgsl_rib_if.wdata;
assign ram.wstrb = s_ram_valid ? u_mstr_rgsl_rib_if.wstrb : '0;
`else
assign s_ram_sel = 1'b0;
assign s_ram_valid = 1'b0;
assign s_ram_ready = 1'b0;
`endif
assign s_fault_sel = u_mstr_rgsl_nmi_if.valid &&
(s_access_denied || ~(s_natv_sel || s_apb_sel || s_ram_sel));
assign s_target_resp_err = apb_nmi.valid && apb_nmi.ready && apb_resp_err_i;
assign s_rsp_ready = s_fault_sel || (natv_nmi.valid && natv_nmi.ready) ||
(apb_nmi.valid && apb_nmi.ready) || s_ram_ready;
assign s_fault_sel = u_mstr_rgsl_rib_if.valid &&
(s_access_denied || ~(s_rib_sel || s_apb_sel || s_ram_sel));
assign s_target_resp_err = apb_rib.valid && apb_rib.ready && apb_resp_err_i;
assign s_rsp_ready = s_fault_sel || (rib.valid && rib.ready) ||
(apb_rib.valid && apb_rib.ready) || s_ram_ready;
always_comb begin
s_rsp_err = s_target_resp_err;
s_rsp_code = s_target_resp_err ? `SOC_NMI_RESP_SLVERR : `SOC_NMI_RESP_OK;
s_rsp_code = s_target_resp_err ? `SOC_RIB_RESP_SLVERR : `SOC_RIB_RESP_OK;
if (s_fault_sel) begin
s_rsp_err = 1'b1;
if (s_access_denied) begin
s_rsp_code = `SOC_NMI_RESP_PROTERR;
end else if (`SOC_ADDR_IS_RESERVED(u_mstr_rgsl_nmi_if.addr)) begin
s_rsp_code = `SOC_NMI_RESP_RESERVED;
s_rsp_code = `SOC_RIB_RESP_PROTERR;
end else if (`SOC_ADDR_IS_RESERVED(u_mstr_rgsl_rib_if.addr)) begin
s_rsp_code = `SOC_RIB_RESP_RESERVED;
end else begin
s_rsp_code = `SOC_NMI_RESP_DECERR;
s_rsp_code = `SOC_RIB_RESP_DECERR;
end
end
end
assign s_fault_event = u_mstr_rgsl_nmi_if.valid && s_rsp_ready && s_rsp_err;
assign fault_valid_o = s_fault_event;
assign fault_addr_o = u_mstr_rgsl_nmi_if.addr;
assign fault_wstrb_o = u_mstr_rgsl_nmi_if.wstrb;
assign fault_reserved_o = s_rsp_code == `SOC_NMI_RESP_RESERVED;
assign fault_access_o = s_rsp_code == `SOC_NMI_RESP_PROTERR;
assign fault_master_o = s_mstr_id_q;
assign fault_code_o = s_rsp_code;
assign s_fault_event = u_mstr_rgsl_rib_if.valid && s_rsp_ready && s_rsp_err;
assign fault_valid_o = s_fault_event;
assign fault_addr_o = u_mstr_rgsl_rib_if.addr;
assign fault_wstrb_o = u_mstr_rgsl_rib_if.wstrb;
assign fault_reserved_o = s_rsp_code == `SOC_RIB_RESP_RESERVED;
assign fault_access_o = s_rsp_code == `SOC_RIB_RESP_PROTERR;
assign fault_master_o = s_mstr_id_q;
assign fault_code_o = s_rsp_code;
// verilog_format: on
`ifdef HAVE_SRAM_MACRO
@@ -253,30 +256,30 @@ module bus (
// verilog_format: off
`ifdef HAVE_SRAM_IF
assign u_mstr_rgsl_nmi_if.ready = s_rsp_ready;
assign u_mstr_rgsl_rib_if.ready = s_rsp_ready;
`else
assign u_mstr_rgsl_nmi_if.ready = s_rsp_ready;
assign u_mstr_rgsl_rib_if.ready = s_rsp_ready;
`endif
`ifdef HAVE_SRAM_IF
assign u_mstr_rgsl_nmi_if.rdata = s_rsp_err ? '0 :
(natv_nmi.valid && natv_nmi.ready) ? natv_nmi.rdata :
(apb_nmi.valid && apb_nmi.ready) ? apb_nmi.rdata :
assign u_mstr_rgsl_rib_if.rdata = s_rsp_err ? '0 :
(rib.valid && rib.ready) ? rib.rdata :
(apb_rib.valid && apb_rib.ready) ? apb_rib.rdata :
s_ram_ready ? ram.rdata : '0;
`else
assign u_mstr_rgsl_nmi_if.rdata = s_rsp_err ? '0 :
(natv_nmi.valid && natv_nmi.ready) ? natv_nmi.rdata :
(apb_nmi.valid && apb_nmi.ready) ? apb_nmi.rdata : '0;
assign u_mstr_rgsl_rib_if.rdata = s_rsp_err ? '0 :
(rib.valid && rib.ready) ? rib.rdata :
(apb_rib.valid && apb_rib.ready) ? apb_rib.rdata : '0;
`endif
assign u_mstr_rgsl_nmi_if.resp_err = s_rsp_ready && s_rsp_err;
assign u_mstr_rgsl_nmi_if.resp_code = s_rsp_ready ? s_rsp_code : `SOC_NMI_RESP_OK;
assign u_mstr_rgsl_rib_if.resp_err = s_rsp_ready && s_rsp_err;
assign u_mstr_rgsl_rib_if.resp_code = s_rsp_ready ? s_rsp_code : `SOC_RIB_RESP_OK;
// verilog_format: on
always_comb begin
s_perf_mgmt_wait_d = s_perf_mgmt_wait_q;
s_perf_user_wait_d = s_perf_user_wait_q;
s_perf_dma_wait_d = s_perf_dma_wait_q;
s_perf_natv_wait_d = s_perf_natv_wait_q;
s_perf_rib_wait_d = s_perf_rib_wait_q;
s_perf_apb_wait_d = s_perf_apb_wait_q;
s_perf_sdram_wait_d = s_perf_sdram_wait_q;
s_perf_psram_wait_d = s_perf_psram_wait_q;
@@ -285,26 +288,26 @@ module bus (
s_perf_mgmt_wait_d = '0;
s_perf_user_wait_d = '0;
s_perf_dma_wait_d = '0;
s_perf_natv_wait_d = '0;
s_perf_rib_wait_d = '0;
s_perf_apb_wait_d = '0;
s_perf_sdram_wait_d = '0;
s_perf_psram_wait_d = '0;
s_perf_flash_wait_d = '0;
end else if (perf_enable_i && u_mstr_rgsl_nmi_if.valid && !s_rsp_ready) begin
end else if (perf_enable_i && u_mstr_rgsl_rib_if.valid && !s_rsp_ready) begin
unique case (s_mstr_id_q)
MSTR_MGMT: s_perf_mgmt_wait_d = s_perf_mgmt_wait_q + 1'b1;
MSTR_USER: s_perf_user_wait_d = s_perf_user_wait_q + 1'b1;
default: s_perf_dma_wait_d = s_perf_dma_wait_q + 1'b1;
endcase
if (s_natv_sel) s_perf_natv_wait_d = s_perf_natv_wait_q + 1'b1;
if (s_rib_sel) s_perf_rib_wait_d = s_perf_rib_wait_q + 1'b1;
if (s_apb_sel) s_perf_apb_wait_d = s_perf_apb_wait_q + 1'b1;
if (`SOC_ADDR_IS_SDRAM(u_mstr_rgsl_nmi_if.addr)) begin
if (`SOC_ADDR_IS_SDRAM(u_mstr_rgsl_rib_if.addr)) begin
s_perf_sdram_wait_d = s_perf_sdram_wait_q + 1'b1;
end
if (`SOC_ADDR_IS_PSRAM(u_mstr_rgsl_nmi_if.addr)) begin
if (`SOC_ADDR_IS_PSRAM(u_mstr_rgsl_rib_if.addr)) begin
s_perf_psram_wait_d = s_perf_psram_wait_q + 1'b1;
end
if (`SOC_ADDR_IS_FLASH(u_mstr_rgsl_nmi_if.addr)) begin
if (`SOC_ADDR_IS_FLASH(u_mstr_rgsl_rib_if.addr)) begin
s_perf_flash_wait_d = s_perf_flash_wait_q + 1'b1;
end
end
@@ -327,11 +330,11 @@ module bus (
s_perf_dma_wait_d,
s_perf_dma_wait_q
);
dffr #(64) u_perf_natv_wait_dffr (
dffr #(64) u_perf_rib_wait_dffr (
clk_i,
rst_n_i,
s_perf_natv_wait_d,
s_perf_natv_wait_q
s_perf_rib_wait_d,
s_perf_rib_wait_q
);
dffr #(64) u_perf_apb_wait_dffr (
clk_i,
@@ -360,7 +363,7 @@ module bus (
assign perf_mgmt_wait_o = s_perf_mgmt_wait_q;
assign perf_user_wait_o = s_perf_user_wait_q;
assign perf_dma_wait_o = s_perf_dma_wait_q;
assign perf_natv_wait_o = s_perf_natv_wait_q;
assign perf_rib_wait_o = s_perf_rib_wait_q;
assign perf_apb_wait_o = s_perf_apb_wait_q;
assign perf_sdram_wait_o = s_perf_sdram_wait_q;
assign perf_psram_wait_o = s_perf_psram_wait_q;
rtl/mini/top/core_wrapper.sv
+2 -2
View File
@@ -13,7 +13,7 @@ module core_wrapper (
input logic clk_i,
input logic rst_n_i,
input logic [31:0] irq_i,
soc_nmi_if.master nmi
soc_rib_if.master rib
// verilog_format: on
);
@@ -21,7 +21,7 @@ module core_wrapper (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.irq_i (irq_i),
.nmi (nmi)
.rib (rib)
);
endmodule
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