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https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
feat: add formal properties for sysctrl and update related files
- Introduced to define formal properties for the sysctrl module. - Updated to include new formal properties and source files. - Renamed to in the bus module and created a new file. - Implemented a testbench for in . - Removed the obsolete test file. - Updated test scripts to reference the new instead of the old RAM module. - Adjusted various test files to ensure compatibility with the new structure and naming conventions.
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+128
-363
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@@ -48,7 +48,7 @@ def test_bus_preserves_incr4_and_rejects_illegal_bursts(tmp_path: Path) -> None:
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str(ROOT / "rtl/mini/top/soc_ribl2rib.sv"),
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str(ROOT / "rtl/mini/top/soc_rib2ribp.sv"),
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str(ROOT / "rtl/mini/top/soc_rib_error_slave.sv"),
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str(ROOT / "rtl/mini/top/soc_rib_ram.sv"),
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str(ROOT / "rtl/mini/top/soc_rib2ram.sv"),
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str(ROOT / "rtl/mini/top/bus.sv"),
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str(ROOT / "tests/rtl/rib_bus_tb.sv"),
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"",
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@@ -77,37 +77,13 @@ def test_bus_preserves_incr4_and_rejects_illegal_bursts(tmp_path: Path) -> None:
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assert "RIB burst arbitration and protocol test passed" in result.stdout
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def test_common_spill_register_preserves_ready_valid_data(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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simulation = tmp_path / "spill_register_tb"
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subprocess.run(
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[
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iverilog,
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"-g2012",
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"-s",
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"spill_register_tb",
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"-o",
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str(simulation),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/spill_register.sv"),
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str(ROOT / "tests/rtl/spill_register_tb.sv"),
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],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "spill register ready/valid test passed" in result.stdout
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def test_burst_sram_preserves_data_and_backpressure(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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source_list = tmp_path / "soc_rib_ram.fl"
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source_list = tmp_path / "soc_rib2ram.fl"
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source_list.write_text(
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"\n".join(
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[
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@@ -118,14 +94,14 @@ def test_burst_sram_preserves_data_and_backpressure(tmp_path: Path) -> None:
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str(ROOT / "rtl/mini/top/soc_rib_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/spill_register.sv"),
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str(ROOT / "rtl/mini/top/soc_rib_ram.sv"),
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str(ROOT / "tests/rtl/soc_rib_ram_tb.sv"),
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str(ROOT / "rtl/mini/top/soc_rib2ram.sv"),
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str(ROOT / "tests/rtl/soc_rib2ram_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "soc_rib_ram_tb.v"
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converted = tmp_path / "soc_rib2ram_tb.v"
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subprocess.run(
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[
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sys.executable,
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@@ -137,9 +113,9 @@ def test_burst_sram_preserves_data_and_backpressure(tmp_path: Path) -> None:
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],
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check=True,
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)
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simulation = tmp_path / "soc_rib_ram_tb"
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simulation = tmp_path / "soc_rib2ram_tb"
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subprocess.run(
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[iverilog, "-g2012", "-s", "soc_rib_ram_tb", "-o", str(simulation), str(converted)],
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[iverilog, "-g2012", "-s", "soc_rib2ram_tb", "-o", str(simulation), str(converted)],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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