chore: support the gen fucn of yosys filelist

.gitignore

@@ -38,4 +38,6 @@ clusterip
 nanoV
 tinyQV
 kianV
-!get_pdk.py
+!get_pdk.py
+def.fl
+yosys.fl

Makefile

@@ -43,12 +43,29 @@ $(info RTL_SIM_PLLCFG: $(RTL_SIM_PLLCFG))
 $(info WAVE:           $(WAVE))
 $(info =========================================)
 
+DEF_LIST    ?= +define+PDK_$(PDK)
+DEF_LIST    += +define+CORE_$(CORE)
+ifeq ($(HAVE_PLL), YES)
+    DEF_LIST += +define+HAVE_PLL
+endif
+
+ifeq ($(HAVE_SRAM), YES)
+    DEF_LIST += +define+HAVE_SRAM
+endif
+
+ifeq ($(HAVE_SVA), NO)
+    DEF_LIST += +define+SV_ASSRT_DISABLE
+endif
+
 ifeq ($(SOC), MINI)
     RTL_PATH = $(ROOT_PATH)/rtl/mini
+    $(file > $(RTL_PATH)/filelist/def.fl, $(DEF_LIST))
     include rtl/mini/Makefile
 endif
 
 ifeq ($(SYNTH), YOSYS)
+    demo := $(shell python3 $(RTL_PATH)/filelist/comb.py $(RTL_FLIST))
+    $(info demo: $(demo))
     include syn/yosys/yosys.mk
 else ifeq ($(SYNTH), DC)
     include syn/dc.mk

rtl/mini/script/vcs.mk

@@ -9,37 +9,24 @@ VERDI_TOOL   := bsub -Is verdi
 COMP_LOG     := -l compile.log
 SIM_LOG      := -l sim.log
 
-DEF_LIST    ?= +define+PDK_$(PDK)
-DEF_LIST    += +define+CORE_$(CORE)
-ifeq ($(HAVE_PLL), YES)
-    DEF_LIST += +define+HAVE_PLL
-endif
-
-ifeq ($(HAVE_SRAM), YES)
-    DEF_LIST += +define+HAVE_SRAM
-endif
-
-ifeq ($(HAVE_SVA), NO)
-    DEF_LIST += +define+SV_ASSRT_DISABLE
-endif
-
 ifeq ($(PDK), IHP130)
     RTL_FLIST := -f ../filelist/pdk_ihp130.fl
 else ifeq ($(PDK), S110)
     RTL_FLIST := -f ../filelist/pdk_s110.fl
 endif
 
+RTL_FLIST += -f ../filelist/def.fl \
+             -f ../filelist/inc.fl \
+             -f ../filelist/ip.fl \
+             -f ../filelist/tech.fl \
+
 ifeq ($(CORE), PICORV32)
     RTL_FLIST += -f ../filelist/core_picorv32.fl
 else ifeq ($(CORE), KIANV)
     RTL_FLIST += -f ../filelist/core_kianv.fl
 endif
 
-RTL_FLIST += -f ../filelist/top.fl \
-             -f ../filelist/ip.fl \
-             -f ../filelist/tech.fl \
-             -f ../filelist/inc.fl \
-             -f ../filelist/def.fl
+RTL_FLIST += -f ../filelist/top.fl
 
 TB_FLIST  := -f ../filelist/tb.fl
 
@@ -53,7 +40,6 @@ SIM_OPTIONS := -full64 +v2k -sverilog -timescale=1ns/10ps \
                 +error+500 \
                 +vcs+flush+all \
                 +lint=TFIPC-L \
-                $(DEF_LIST) \
                 -xprop=../xprop_config \
                 -work DEFAULT
 

syn/yosys/yosys.mk

@@ -29,7 +29,7 @@ include $(YOSYS_DIR)/synth_config.mk
 
 TOP_DESIGN    ?= retrosoc_asic
 RTL_NAME      ?= retrosoc_asic
-SV_FLIST      := $(YOSYS_DIR)/../../rtl/mini/filelist/mini.fl
+SV_FLIST      := $(YOSYS_DIR)/../../rtl/mini/filelist/yosys.fl
 
 $(info SV_FLIST: $(SV_FLIST))