feat: refactor UART and Timer Interfaces; Remove Unused Components

- Deleted the UART interface and related components from the RTL design, including the UART TX/RX signals and instances.
- Removed the timer interface and its associated files from the project, including the timer definitions and references in the integration files.
- Updated the APB target configurations to reflect the removal of the UART and timer components, ensuring the IRQ and memory map configurations are consistent.
- Adjusted the formal verification properties and testbenches to exclude references to the removed components.
- Cleaned up the integration documentation to accurately describe the current state of the system without the UART and timer interfaces.

tests/rtl/rib2apb_tb.sv

@@ -12,13 +12,11 @@ module rib2apb_tb;
   rib_if rib ();
   apb4_pure_if archinfo ();
   apb4_pure_if rng ();
-  apb4_pure_if uart ();
   apb4_pure_if pwm ();
   apb4_pure_if ps2 ();
   apb4_pure_if rtc ();
   apb4_pure_if wdg ();
   apb4_pure_if crc ();
-  apb4_pure_if tmr ();
   apb4_pure_if user_ip ();
 
   always #5 clk_i = ~clk_i;
@@ -29,9 +27,6 @@ module rib2apb_tb;
   assign rng.pready       = rng_ready;
   assign rng.prdata       = rng_rdata;
   assign rng.pslverr      = rng_slverr;
-  assign uart.pready      = 1'b0;
-  assign uart.prdata      = '0;
-  assign uart.pslverr     = 1'b0;
   assign pwm.pready       = 1'b0;
   assign pwm.prdata       = '0;
   assign pwm.pslverr      = 1'b0;
@@ -47,9 +42,6 @@ module rib2apb_tb;
   assign crc.pready       = 1'b0;
   assign crc.prdata       = '0;
   assign crc.pslverr      = 1'b0;
-  assign tmr.pready       = 1'b0;
-  assign tmr.prdata       = '0;
-  assign tmr.pslverr      = 1'b0;
   assign user_ip.pready   = 1'b0;
   assign user_ip.prdata   = '0;
   assign user_ip.pslverr  = 1'b0;
@@ -60,13 +52,11 @@ module rib2apb_tb;
       .rib     (rib),
       .archinfo(archinfo),
       .rng     (rng),
-      .uart    (uart),
       .pwm     (pwm),
       .ps2     (ps2),
       .rtc     (rtc),
       .wdg     (wdg),
       .crc     (crc),
-      .tmr     (tmr),
       .user_ip (user_ip)
   );
 

tests/rtl/soc_irq_topology_tb.sv

@@ -30,17 +30,31 @@ module soc_irq_topology_tb;
       expect_irq(32'd1 << bit_index);
     end
 
-    s_ribp_irq     = '0;
-    s_ribp_irq[10] = 1'b1;
-    expect_irq(32'd1 << 17);
+    for (int bit_index = 10; bit_index < `SOC_IRQ_RIBP_WIDTH; bit_index++) begin
+      s_ribp_irq            = '0;
+      s_ribp_irq[bit_index] = 1'b1;
+      expect_irq(32'd1 << (bit_index + 7));
+    end
 
     for (int bit_index = 0; bit_index < `SOC_IRQ_APB_WIDTH; bit_index++) begin
       s_ribp_irq           = '0;
       s_apb_irq            = '0;
       s_apb_irq[bit_index] = 1'b1;
-      expect_irq(32'd1 << (10 + bit_index));
+      case (bit_index)
+        0:       expect_irq(32'd1 << 11);
+        1:       expect_irq(32'd1 << 12);
+        2:       expect_irq(32'd1 << 13);
+        3:       expect_irq(32'd1 << 14);
+        4:       expect_irq(32'd1 << 16);
+        default: $fatal(1, "unexpected APB IRQ bit %0d", bit_index);
+      endcase
     end
 
+    s_apb_irq = '0;
+    expect_irq('0);
+    if (s_irq[10] !== 1'b0 || s_irq[15] !== 1'b0) begin
+      $fatal(1, "removed core IRQ bits are not low: IRQ10=%b IRQ15=%b", s_irq[10], s_irq[15]);
+    end
     if (s_irq[31:18] !== '0) begin
       $fatal(1, "unallocated core IRQ bits are not low: %h", s_irq[31:18]);
     end

tests/test_memory_map.py

@@ -87,8 +87,23 @@ def test_user_ip_is_always_emitted_for_the_fixed_platform(tmp_path: Path) -> Non
     rtl = (tmp_path / "rtl/mmap_define.svh").read_text(encoding="utf-8")
     header = (tmp_path / "include/retrosoc/generated/memory_map.h").read_text(encoding="utf-8")
 
-    assert "SOC_ADDR_APB_USER_IP_BASE" in rtl
-    assert "RS_SOC_APB_USER_IP_BASE" in header
+    expected_apb_bases = {
+        "ARCHINFO": "20000000",
+        "RNG": "20001000",
+        "PWM": "20002000",
+        "PS2": "20003000",
+        "RTC": "20004000",
+        "WDG": "20005000",
+        "CRC": "20006000",
+        "USER_IP": "20007000",
+    }
+    for symbol, base in expected_apb_bases.items():
+        assert f"`define SOC_ADDR_APB_{symbol}_BASE 32'h{base}" in rtl
+        assert f"#define RS_SOC_APB_{symbol}_BASE UINT32_C(0x{base})" in header
+    assert "APB_UART1" not in rtl
+    assert "APB_UART1" not in header
+    assert "APB_TMR" not in rtl
+    assert "APB_TMR" not in header
 
 
 def test_bootstrap_assembly_uses_the_generated_gpio_admin_base() -> None:

tests/test_soc_topology.py

@@ -82,7 +82,11 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -
     assert "assign s_xpi_region_sel[1] = (ribp.addr <= `SOC_ADDR_FLASH_END);" in routes
     assert "assign u_sdio_ribp_if.valid = 1'b0;" in routes
     assert gpio.count("// GPIO") == 64
-    assert "assign u_uart1_if.rx_i = u_gpio_if.di_i[0];" in gpio
+    assert "u_uart1_if" not in gpio
+    assert "assign u_gpio_if.alt0_do_i[0] = 1'b0;" in gpio
+    assert "assign u_gpio_if.alt0_oe_i[0] = 1'b0;" in gpio
+    assert "assign u_gpio_if.alt0_do_i[1] = 1'b0;" in gpio
+    assert "assign u_gpio_if.alt0_oe_i[1] = 1'b0;" in gpio
     assert "assign u_gpio_if.alt1_do_i[0] = u_ps2_if.ps2_clk_o;" in gpio
     assert "assign u_gpio_if.alt1_oe_i[0] = u_ps2_if.ps2_clk_oe_o;" in gpio
     assert "assign u_gpio_if.alt1_do_i[1] = u_ps2_if.ps2_dat_o;" in gpio
@@ -95,11 +99,12 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -
     assert "assign u_pwm_if.capture_i[0] = u_gpio_if.di_i[30];" in gpio
     assert "assign u_pwm_if.capture_i[1] = u_gpio_if.di_i[31];" in gpio
     assert "assign u_gpio_if.alt1_do_i[22] = u_psram_if.nss_o[0];" in gpio
-    assert apb_interfaces.count("apb4_if u_") == 10
+    assert "s_tmr_capch" not in gpio
+    assert apb_interfaces.count("apb4_if u_") == 8
     assert "apb4_pure_if u_archinfo_apb_pure_if ();" in apb_interfaces
-    assert "assign tmr.paddr = s_addr_q;" in apb_routes
-    assert "({32{s_psel_q[8]}} & tmr.prdata)" in apb_response
-    assert "localparam int NSLV = 10;" in apb_declarations
+    assert "assign user_ip.paddr = s_addr_q;" in apb_routes
+    assert "({32{s_psel_q[7]}} & user_ip.prdata)" in apb_response
+    assert "localparam int NSLV = 8;" in apb_declarations
     assert fabric.count("ribp_if u_") == 1
     assert fabric.count("rib_if u_") == 4
     assert ".mgmt_ribp(u_mgmt_ribp_if)" in bus_fabric
@@ -107,16 +112,20 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -
     assert ".apb_rib(u_apb_rib_if)" in bus_fabric
     assert ".rib(u_rib_if)" in bus_fabric
     assert "`define SOC_IRQ_VECTOR_WIDTH 32" in irq_config
-    assert "`define SOC_USER_IRQ_MASK 32'h000EFFFC" in irq_config
+    assert "`define SOC_USER_IRQ_MASK 32'h000E7BFC" in irq_config
     assert "`define SOC_IRQ_RIBP_WIDTH 13" in irq_config
-    assert "`define SOC_IRQ_APB_WIDTH 7" in irq_config
+    assert "`define SOC_IRQ_APB_WIDTH 5" in irq_config
     assert "assign irq_o[0] = u_clint_if.software_irq_o[0];" in rib_irq
     assert "assign irq_o[10] = ws2812.irq_o;" in rib_irq
     assert "assign irq_o[11] = gpio.irq_o;" in rib_irq
     assert "assign irq_o[12] = i2c1.irq_o;" in rib_irq
-    assert "assign irq_o[5] = u_tmr_if.irq_o;" in apb_irq
-    assert "assign irq_o[6] = s_rng_irq;" in apb_irq
-    assert "s_irq[16] = s_apb_irq[6];" in irq_wiring
+    assert "assign irq_o[0] = pwm.irq_o;" in apb_irq
+    assert "assign irq_o[4] = s_rng_irq;" in apb_irq
+    assert "s_irq[10]" not in irq_wiring
+    assert "s_irq[15]" not in irq_wiring
+    assert "s_irq[16] = s_apb_irq[4];" in irq_wiring
+    assert "irq_i[10] == 1'b0" in irq_sva
+    assert "irq_i[15] == 1'b0" in irq_sva
     assert "irq_i[31] == 1'b0" in irq_sva
     assert "bind retrosoc soc_irq_topology_sva" in irq_sva
     assert filelist.startswith("+incdir+")
@@ -135,7 +144,7 @@ def test_topology_preserves_default_irq_compatibility_mapping() -> None:
         )
         for interrupt in document["interrupts"]
     ]
-    assert mappings[:20] == [
+    assert mappings == [
         ("clint_software", "ribp", 0, 0, "u_clint_if.software_irq_o[0]"),
         ("clint_timer", "ribp", 1, 1, "u_clint_if.timer_irq_o[0]"),
         ("uart0", "ribp", 2, 2, "uart.irq_o"),
@@ -146,18 +155,15 @@ def test_topology_preserves_default_irq_compatibility_mapping() -> None:
         ("i2c0", "ribp", 7, 7, "i2c0.irq_o"),
         ("i2s", "ribp", 8, 8, "i2s.irq_o"),
         ("xpi", "ribp", 9, 9, "xpi.irq_o"),
-        ("uart1", "apb", 0, 10, "uart.irq_o"),
-        ("pwm", "apb", 1, 11, "pwm.irq_o"),
-        ("ps2", "apb", 2, 12, "ps2.irq_o"),
-        ("rtc", "apb", 3, 13, "u_rtc_if.irq_o"),
-        ("watchdog_early_warning", "apb", 4, 14, "u_wdg_if.irq_o"),
-        ("advanced_timer", "apb", 5, 15, "u_tmr_if.irq_o"),
-        ("rng", "apb", 6, 16, "s_rng_irq"),
+        ("pwm", "apb", 0, 11, "pwm.irq_o"),
+        ("ps2", "apb", 1, 12, "ps2.irq_o"),
+        ("rtc", "apb", 2, 13, "u_rtc_if.irq_o"),
+        ("watchdog_early_warning", "apb", 3, 14, "u_wdg_if.irq_o"),
+        ("rng", "apb", 4, 16, "s_rng_irq"),
         ("ws2812", "ribp", 10, 17, "ws2812.irq_o"),
         ("gpio", "ribp", 11, 18, "gpio.irq_o"),
         ("i2c1", "ribp", 12, 19, "i2c1.irq_o"),
     ]
-    assert all(mapping[3] >= 20 for mapping in mappings[20:])
 
 
 def test_topology_always_adds_the_user_apb_target(tmp_path: Path) -> None:
@@ -172,12 +178,12 @@ def test_topology_always_adds_the_user_apb_target(tmp_path: Path) -> None:
     )
 
     assert "apb4_if u_user_ip_apb_if (clk_i, rst_n_i);" in interfaces
-    assert "localparam int NSLV = 10;" in declarations
-    assert "s_psel_q[9]" in response
+    assert "localparam int NSLV = 8;" in declarations
+    assert "s_psel_q[7]" in response
     assert "apb4_pure_if user_ip ();" in formal_design
     assert ".user_ip (user_ip)" in formal_design
-    assert "logic [ 9:0] psel_comb" in formal_design
-    assert "wire [ 9:0] psel_comb" in formal_properties
+    assert "logic [ 7:0] psel_comb" in formal_design
+    assert "wire [ 7:0] psel_comb" in formal_properties
 
 
 def test_topology_rejects_unknown_or_non_rib_regions(tmp_path: Path) -> None:
@@ -222,7 +228,7 @@ def test_topology_rejects_invalid_apb_target_ownership(tmp_path: Path) -> None:
     assert "not an active APB region" in result.stderr
 
     document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
-    document["apb_targets"][8]["slot"] = 0
+    document["apb_targets"][7]["slot"] = 0
     result = validate(write_invalid_topology(tmp_path, document))
     assert result.returncode != 0
     assert "APB target slot 0 is duplicated" in result.stderr
@@ -268,7 +274,12 @@ def test_topology_rejects_invalid_irq_groups_and_bindings(tmp_path: Path) -> Non
     assert "core interrupt bit 0 is duplicated" in result.stderr
 
     document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
-    document["interrupts"].pop(16)
+    rng_index = next(
+        index
+        for index, interrupt in enumerate(document["interrupts"])
+        if interrupt["name"] == "rng"
+    )
+    document["interrupts"].pop(rng_index)
     result = validate(write_invalid_topology(tmp_path, document))
     assert result.returncode != 0
     assert "interrupt group apb does not cover every group bit" in result.stderr