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feat(tech): add the GF180 64/128/256x8 SRAM functional models

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Extend gf180_sram_sim_cells.sv with pin-compatible functional models for
gf180mcu_fd_ip_sram__sram{64,128,256}x8m8wm1, matching the existing 512x8
model's style and behavior (registered read, per-bit active-low WEN,
VDD/VSS sanity checks). All four geometries ship vendor collateral in the
locked gf180mcu-pdk checkout; the repo-owned models keep simulation
self-contained per the existing convention. No filelist change: the file
is already listed in pdk_gf180.fl.
This commit is contained in:
maksyuki committed 2026-10-15 15:54:01 +08:00
1 parent 7070be96c9
commit e5819d0a27
1 file changed
+98 -1
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rtl/tech/gf180_sram_sim_cells.sv
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@@ -8,7 +8,8 @@
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
// Pin-compatible functional model for the GF180 512x8 bit-write SRAM macro.
// Pin-compatible functional models for the GF180 bit-write SRAM macros
// (512x8 for the SoC SRAM, 64/128/256x8 for the C906 SRAM tiles).
/* verilator lint_off DECLFILENAME */
module gf180mcu_fd_ip_sram__sram512x8m8wm1 (
// verilog_format: off -- preserve the PDK memory interface columns
@@ -40,3 +41,99 @@ module gf180mcu_fd_ip_sram__sram512x8m8wm1 (
end
endmodule
/* verilator lint_on DECLFILENAME */
/* verilator lint_off DECLFILENAME */
module gf180mcu_fd_ip_sram__sram256x8m8wm1 (
// verilog_format: off -- preserve the PDK memory interface columns
input logic CLK,
input logic CEN,
input logic GWEN,
input logic [7:0] WEN,
input logic [7:0] A,
input logic [7:0] D,
output logic [7:0] Q,
inout wire VDD,
inout wire VSS
// verilog_format: on
);
logic [7:0] s_storage_q[0:255];
always_ff @(posedge CLK) begin
if (!CEN && (VDD !== 1'b0) && (VSS !== 1'b1)) begin
if (GWEN) begin
Q <= s_storage_q[A];
end else begin
for (int unsigned bit_index = 0; bit_index < 8; bit_index++) begin
if (!WEN[bit_index]) begin
s_storage_q[A][bit_index] <= D[bit_index];
end
end
end
end
end
endmodule
/* verilator lint_on DECLFILENAME */
/* verilator lint_off DECLFILENAME */
module gf180mcu_fd_ip_sram__sram128x8m8wm1 (
// verilog_format: off -- preserve the PDK memory interface columns
input logic CLK,
input logic CEN,
input logic GWEN,
input logic [7:0] WEN,
input logic [6:0] A,
input logic [7:0] D,
output logic [7:0] Q,
inout wire VDD,
inout wire VSS
// verilog_format: on
);
logic [7:0] s_storage_q[0:127];
always_ff @(posedge CLK) begin
if (!CEN && (VDD !== 1'b0) && (VSS !== 1'b1)) begin
if (GWEN) begin
Q <= s_storage_q[A];
end else begin
for (int unsigned bit_index = 0; bit_index < 8; bit_index++) begin
if (!WEN[bit_index]) begin
s_storage_q[A][bit_index] <= D[bit_index];
end
end
end
end
end
endmodule
/* verilator lint_on DECLFILENAME */
/* verilator lint_off DECLFILENAME */
module gf180mcu_fd_ip_sram__sram64x8m8wm1 (
// verilog_format: off -- preserve the PDK memory interface columns
input logic CLK,
input logic CEN,
input logic GWEN,
input logic [7:0] WEN,
input logic [5:0] A,
input logic [7:0] D,
output logic [7:0] Q,
inout wire VDD,
inout wire VSS
// verilog_format: on
);
logic [7:0] s_storage_q[0:63];
always_ff @(posedge CLK) begin
if (!CEN && (VDD !== 1'b0) && (VSS !== 1'b1)) begin
if (GWEN) begin
Q <= s_storage_q[A];
end else begin
for (int unsigned bit_index = 0; bit_index < 8; bit_index++) begin
if (!WEN[bit_index]) begin
s_storage_q[A][bit_index] <= D[bit_index];
end
end
end
end
end
endmodule
/* verilator lint_on DECLFILENAME */