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feat: add pulp croc yosys config files

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maksyuki committed 2025-01-22 23:06:19 +08:00
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syn/yosys/.gitignore
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reports
out
WORK
*.log
syn/yosys/project-synth.mk
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# Copyright (c) 2022 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
#
# Authors:
# - Philippe Sauter <phsauter@iis.ee.ethz.ch>
# target clock-period in pico-seconds
export YOSYS_TARGET_PERIOD_PS := 10000
# modules Yosys will treat as blackboxes
export YOSYS_BLACKBOX_MODULES := "*tc_sram_blackbox*"
# flatten hierarchy (except for below selections)
export YOSYS_FLATTEN_HIER := 1
# a list of yosys selection strings, all selected instances will be
# kept as a seperate hierarchical element, all others will be flattened
# https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/select.html
export YOSYS_KEEP_HIER_INST := "t:croc_soc$$*" \
"t:croc_domain$$*" \
"t:core_wrap$$*" \
"t:cve2_register_file_ff$$*" \
"t:cve2_cs_registers$$*" \
"t:dmi_jtag$$*" \
"t:dm_top$$*" \
"t:gpio$$*" \
"t:timer_unit$$*" \
"t:reg_uart_wrap$$*" \
"t:tc_clk*$$*" \
"t:tc_sram$$*" \
"t:soc_ctrl_reg_top$$*" \
"t:user_domain$$*" \
"t:cdc_*$$*" \
"t:sync$$*" \
# the paths (full names) of all instances matching these strings is reported
# for floorplaning or writing constraints
export YOSYS_REPORT_INSTS := "t:*RM_IHPSG13_*"
syn/yosys/scripts/abc-opt.script
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# Copyright (c) 2022 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
#
# Authors:
# - Philippe Sauter <phsauter@iis.ee.ethz.ch>
#
# Optimization script utilizing 'Lazy Mans Synthesis'
# Requires the library of 6-input records (src/rec6Lib...)
# https://people.eecs.berkeley.edu/~alanmi/publications/2012/iccad12_lms.pdf
print_stats
# strash can fix some yosys-convertion edge-cases, good idea to run first
strash
rec_start3 {REC_AIG}
# main optimization iteration:
alias &opt_iter "&st; &if -y -K 6; &syn2; &if -K 6; &st; &b"
# &if -y -K 6; &syn2; &if -K 6, see LMS paper
# &dc2 AIG rewriting (greedy minimization)
# &b balance structure for depth
# &st structural hashing
# &dc compute structural choices
# &nf select choice and map to tech
# &ps print statistics
# mapping iteration
alias &map_iter "&st; &nf {D}; &ps"
# initial mapping iteration
&get -n
echo "Initial network:"
&ps
echo "High effort delay optimization..."
&opt_iter; &opt_iter; &ps;
&opt_iter; &opt_iter; &ps;
&opt_iter; &opt_iter; &ps;
&opt_iter; &opt_iter; &ps;
&put
# according to https://people.eecs.berkeley.edu/~alanmi/abc/
# it can take up to 10-ish iterations for convergence
# in my experience it seems to get 99% there after 5-6 with a lower runtime
&get -n
echo "Opt+mapping Iterations..."
&opt_iter; &map_iter;
&opt_iter; &map_iter;
&opt_iter; &map_iter;
&opt_iter; &map_iter;
&opt_iter; &map_iter;
&opt_iter; &map_iter;
&opt_iter; &map_iter;
&opt_iter; &map_iter;
&put
topo
stime
echo "buffering for delay and fanout..."
buffer -p
echo "resizing cells..."
upsize {D}
dnsize {D}
upsize {D}
dnsize {D}
echo "Final timing:"
stime
syn/yosys/scripts/filter_output.awk
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BEGIN {
IGNORECASE=1
capture = 0
RED = "\033[31m"
YELLOW = "\033[33m"
RESET = "\033[0m"
}
/Executing SLANG frontend/ {
# Start capturing when we find "Executing SLANG frontend"
capture = 1
gsub(/\<Warning[s]*\>/, YELLOW "Warning" RESET)
gsub(/\<Error[s]*\>/, RED "Error" RESET)
print
next
}
capture {
gsub(/\<Warning[s]*\>/, YELLOW "Warning" RESET)
gsub(/\<Error[s]*\>/, RED "Error" RESET)
print
if ($0 ~ /Executing/ && $0 !~ /SLANG frontend/) {
capture = 0
}
}
/Executing/ {
if ($0 ~ /[0-9\.]+ Executing/) {
gsub(/\<Warning[s]*\>/, YELLOW "Warning" RESET)
gsub(/\<Error[s]*\>/, RED "Error" RESET)
print
}
}
/\<Warning[s]*\>|\<Error[s]*\>/ {
gsub(/\<Warning\>/, YELLOW "Warning" RESET)
gsub(/\<Error\>/, RED "Error" RESET)
print
}
syn/yosys/scripts/init_tech.tcl
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# Copyright (c) 2022 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
#
# Authors:
# - Philippe Sauter <phsauter@iis.ee.ethz.ch>
# get environment variables
set yosys_dir [file dirname [file dirname [info script]]]
set root_dir [file dirname $yosys_dir]
if {[file exists "$root_dir/.cockpitrc"]} {
puts "0. Executing init_tech: load technology from ETHZ DZ cockpit"
set pdk_dir "$root_dir/technology"
set pdk_cells_lib ${pdk_dir}/lib
set pdk_sram_lib ${pdk_dir}/lib
set pdk_io_lib ${pdk_dir}/lib
} else {
puts "0. Executing init_tech: load technology from Github PDK"
if {![info exists pdk_dir]} {
set pdk_dir "$root_dir/ihp13/pdk"
}
set pdk_cells_lib ${pdk_dir}/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib
set pdk_sram_lib ${pdk_dir}/ihp-sg13g2/libs.ref/sg13g2_sram/lib
set pdk_io_lib ${pdk_dir}/ihp-sg13g2/libs.ref/sg13g2_io/lib
}
set tech_cells [list "$pdk_cells_lib/sg13g2_stdcell_typ_1p20V_25C.lib"]
set tech_macros [glob -nocomplain -directory $pdk_sram_lib *_typ_1p20V_25C.lib]
lappend tech_macros "$pdk_io_lib/sg13g2_io_typ_1p2V_3p3V_25C.lib"
# for hilomap
set tech_cell_tiehi {sg13g2_tiehi L_HI}
set tech_cell_tielo {sg13g2_tielo L_LO}
# pre-formated for easier use in yosys commands
# all liberty files
set lib_list [concat [split $tech_cells] [split $tech_macros] ]
set liberty_args_list [lmap lib $lib_list {concat "-liberty" $lib}]
set liberty_args [concat {*}$liberty_args_list]
# only the standard cells
set tech_cells_args_list [lmap lib $tech_cells {concat "-liberty" $lib}]
set tech_cells_args [concat {*}$tech_cells_args_list]
# read library files
foreach file $lib_list {
yosys read_liberty -lib "$file"
}
syn/yosys/scripts/yosys_common.tcl
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# Copyright (c) 2022 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
#
# Authors:
# - Philippe Sauter <phsauter@iis.ee.ethz.ch>
# Common setup used for all yosys scripts
# list of global variables that may be used
set variables {
vlog_files { VLOG_FILES "" }
sv_flist { SV_FLIST "" }
top_design { TOP_DESIGN "" }
hier_depth { HIER_DEPTH 0 }
period_ps { YOSYS_TARGET_PERIOD_PS 5000 }
proj_name { PROJ_NAME "" }
build_dir { BUILD "[set dir [pwd]]/out" }
work_dir { WORK "[set dir [pwd]]/WORK" }
report_dir { REPORTS "[set dir [pwd]]/report" }
netlist { NETLIST "" }
}
# either use env-var or default to fallback
foreach var [dict keys $variables] {
set values [dict get $variables $var]
set env_var [lindex $values 0]
set fallback [lindex $values 1]
if {[info exists ::env($env_var)]} {
puts "using: $var= '$::env($env_var)'"
set $var $::env($env_var)
} else {
puts "using: '$var= $fallback'"
set $var $fallback
}
}
if {[string eq $netlist ""]} {
set netlist ${build_dir}/${top_design}_netlist.v
}
proc envVarValid {var_name} {
if { [info exists ::env($var_name)]} {
if {$::env($var_name) != "0" && $::env($var_name) ne ""} {
return 1
}
}
return 0
}
proc processAbcScript {abc_script} {
global work_dir period_ps
set src_dir [file join [file dirname [info script]] ../src]
set abc_out_path $work_dir/[file tail $abc_script]
set raw [read -nonewline [open $abc_script r]]
set abc_script_delay [string map -nocase [list "{D}" [subst "-D $period_ps"]] $raw]
set abc_script_recaig [string map -nocase [list "{REC_AIG}" [subst "$src_dir/rec6Lib_final_filtered3_recanon_basilisk.aig"]] $abc_script_delay]
set abc_out [open $abc_out_path w]
puts -nonewline $abc_out $abc_script_recaig
flush $abc_out
close $abc_out
return $abc_out_path
}
syn/yosys/scripts/yosys_synthesis.tcl
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# Copyright (c) 2022 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
#
# Authors:
# - Philippe Sauter <phsauter@iis.ee.ethz.ch>
# get environment variables
set script_dir [file dirname [info script]]
source $script_dir/yosys_common.tcl
# constraints file
set abc_constr [file join $script_dir ../src/abc.constr]
# ABC script without DFF optimizations
set abc_combinational_script $script_dir/abc-opt.script
# process abc file (written to WORK directory)
set abc_comb_script [processAbcScript $abc_combinational_script]
# read liberty files and prepare some variables
source $script_dir/init_tech.tcl
yosys plugin -i slang.so
# read design
yosys read_slang --top $top_design -f $sv_flist \
--compat-mode --keep-hierarchy \
--allow-use-before-declare --ignore-unknown-modules
# blackbox requested modules
if { [info exists ::env(YOSYS_BLACKBOX_MODULES)] } {
foreach sel $::env(YOSYS_BLACKBOX_MODULES) {
puts "Blackboxing the module ${sel}"
yosys select -list {*}$sel
yosys blackbox {*}$sel
yosys setattr -set keep_hierarchy 1 {*}$sel
}
}
# preserve hierarchy of selected modules/instances
if { [info exists ::env(YOSYS_KEEP_HIER_INST)] } {
foreach sel $::env(YOSYS_KEEP_HIER_INST) {
puts "Keeping hierarchy of selection: $sel"
yosys select -list {*}$sel
yosys setattr -set keep_hierarchy 1 {*}$sel
}
}
# map dont_touch attribute commonly applied to output-nets of async regs to keep
yosys attrmap -rename dont_touch keep
# copy the keep attribute to their driving cells (retain on net for debugging)
yosys attrmvcp -copy -attr keep
# -----------------------------------------------------------------------------
# this section heavily borrows from the yosys synth command:
# synth - check
yosys hierarchy -check -top $top_design
yosys proc
yosys tee -q -o "${report_dir}/${proj_name}_initial.rpt" stat
yosys write_verilog -norename -noexpr -attr2comment ${build_dir}/${proj_name}_yosys_initial.v
# synth - coarse:
# yosys synth -run coarse -noalumacc
yosys opt_expr
yosys opt_clean
yosys check
yosys opt -noff
yosys fsm
yosys opt
yosys tee -q -o "${report_dir}/${proj_name}_initial_opt.rpt" stat
yosys wreduce
yosys peepopt
yosys opt_clean
yosys opt -full
yosys booth
yosys alumacc
yosys share
yosys opt
yosys memory
yosys opt -fast
yosys opt_dff -sat -nodffe -nosdff
yosys share
yosys opt -full
yosys clean -purge
yosys write_verilog -norename ${work_dir}/${proj_name}_abstract.yosys.v
yosys tee -q -o "${report_dir}/${proj_name}_abstract.rpt" stat -tech cmos
yosys techmap
yosys opt -fast
yosys clean -purge
# -----------------------------------------------------------------------------
yosys tee -q -o "${report_dir}/${proj_name}_generic.rpt" stat -tech cmos
yosys tee -q -o "${report_dir}/${proj_name}_generic.json" stat -json -tech cmos
if {[envVarValid "YOSYS_FLATTEN_HIER"]} {
yosys flatten
}
yosys clean -purge
# -----------------------------------------------------------------------------
# split internal nets
yosys splitnets -format __v
# rename DFFs from the driven signal
yosys rename -wire -suffix _reg t:*DFF*
yosys select -write ${report_dir}/${proj_name}_registers.rpt t:*DFF*
# rename all other cells
yosys autoname t:*DFF* %n
yosys clean -purge
# print paths to important instances
yosys select -write ${report_dir}/${proj_name}_registers.rpt t:*DFF*
set report [open ${report_dir}/${proj_name}_instances.rpt "w"]
close $report
if { [info exists ::env(YOSYS_REPORT_INSTS)] } {
foreach sel $::env(YOSYS_REPORT_INSTS) {
yosys tee -q -a ${report_dir}/${proj_name}_instances.rpt select -list {*}$sel
}
}
yosys tee -q -o "${report_dir}/${proj_name}_pre_tech.rpt" stat -tech cmos
yosys tee -q -o "${report_dir}/${proj_name}_pre_tech.json" stat -json -tech cmos
# -----------------------------------------------------------------------------
# mapping to technology
puts "Using combinational-only abc optimizations"
yosys dfflibmap {*}$tech_cells_args
yosys abc {*}$tech_cells_args -D $period_ps -script $abc_comb_script -constr $abc_constr -showtmp
yosys clean -purge
# -----------------------------------------------------------------------------
# prep for openROAD
yosys write_verilog -norename -noexpr -attr2comment ${build_dir}/${proj_name}_yosys_debug.v
yosys splitnets -ports -format __v
yosys setundef -zero
yosys clean -purge
yosys hilomap -singleton -hicell {*}$tech_cell_tiehi -locell {*}$tech_cell_tielo
# final reports
yosys tee -q -o "${report_dir}/${proj_name}_synth.rpt" check
yosys tee -q -o "${report_dir}/${proj_name}_area.rpt" stat -top $top_design {*}$liberty_args
yosys tee -q -o "${report_dir}/${proj_name}_area_logic.rpt" stat -top $top_design {*}$tech_cells_args
# final netlist
yosys write_verilog -noattr -noexpr -nohex -nodec $netlist
syn/yosys/src/abc.constr
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# Copyright (c) 2024 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
#
# Authors:
# - Philippe Sauter <phsauter@iis.ee.ethz.ch>
set_driving_cell sg13g2_buf_1
set_load 0.015
syn/yosys/yosys.mk
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# Copyright (c) 2022 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
#
# Authors:
# - Philippe Sauter <phsauter@iis.ee.ethz.ch>
# Tools
YOSYS ?= yosys
# Directories
# directory of the path to the last called Makefile (this one)
YOSYS_DIR := $(realpath $(dir $(realpath $(lastword $(MAKEFILE_LIST)))))
YOSYS_OUT := $(YOSYS_DIR)/out
YOSYS_WORK := $(YOSYS_DIR)/tmp
YOSYS_REPORTS := $(YOSYS_DIR)/reports
# Project variables
include $(YOSYS_DIR)/project-synth.mk
TOP_DESIGN ?= croc_chip
RTL_NAME ?= croc
PICKLE_OUT := $(realpath $(YOSYS_DIR)/..)/pickle
VLOG_FILES := $(PICKLE_OUT)/$(RTL_NAME)_sv2v.v
NETLIST := $(YOSYS_OUT)/$(RTL_NAME)_yosys.v
NETLIST_DEBUG := $(YOSYS_OUT)/$(RTL_NAME)_debug_yosys.v
## Synthesize netlist using Yosys
yosys: $(NETLIST)
$(NETLIST) $(NETLIST_DEBUG): $(SV_FLIST)
@mkdir -p $(YOSYS_OUT)
@mkdir -p $(YOSYS_WORK)
@mkdir -p $(YOSYS_REPORTS)
SV_FLIST="$(SV_FLIST)" \
TOP_DESIGN="$(TOP_DESIGN)" \
PROJ_NAME="$(RTL_NAME)" \
WORK="$(YOSYS_WORK)" \
BUILD="$(YOSYS_OUT)" \
REPORTS="$(YOSYS_REPORTS)" \
NETLIST="$(NETLIST)" \
$(YOSYS) -c $(YOSYS_DIR)/scripts/yosys_synthesis.tcl \
2>&1 | TZ=UTC gawk '{ print strftime("[%Y-%m-%d %H:%M %Z]"), $$0 }' \
| tee "$(YOSYS_DIR)/$(RTL_NAME).log" \
| gawk -f $(YOSYS_DIR)/scripts/filter_output.awk;
ys_clean:
rm -rf $(YOSYS_OUT)
rm -rf $(YOSYS_WORK)
rm -rf $(YOSYS_REPORTS)
rm -f $(YOSYS_DIR)/$(RTL_NAME).log
.PHONY: ys_clean yosys synth yosys-slang