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synced 2026-11-04 22:32:36 +00:00
fix: fix inout wire port connect
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1 file changed
+3
-3
@@ -36,7 +36,7 @@ module retrosoc_tb;
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wire s_rst_n;
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wire [4:0] s_core_mdd_sel;
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wire [4:0] s_ip_mdd_sel;
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wire s_pll_en;
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wire s_clk_bypass;
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wire [2:0] s_pll_cfg;
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wire s_uart_tx;
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@@ -71,7 +71,7 @@ module retrosoc_tb;
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assign s_rst_n = r_rst_n;
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assign s_core_mdd_sel = r_core_mdd_sel;
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assign s_ip_mdd_sel = r_ip_mdd_sel;
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assign s_pll_en = r_pll_en;
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assign s_clk_bypass = ~r_pll_en;
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assign s_pll_cfg = r_pll_cfg;
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retrosoc_asic u_retrosoc_asic (
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@@ -111,7 +111,7 @@ module retrosoc_tb;
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.pll_cfg_0_i_pad (s_pll_cfg[0]),
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.pll_cfg_1_i_pad (s_pll_cfg[1]),
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.pll_cfg_2_i_pad (s_pll_cfg[2]),
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.clk_bypass_i_pad (~s_pll_en),
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.clk_bypass_i_pad (s_clk_bypass),
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.ext_rst_n_i_pad (s_rst_n),
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.sys_clkdiv4_o_pad (),
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.uart_tx_o_pad (s_uart_tx),
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