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fix: fix a axil rdata wire select

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maksyuki committed 2025-02-11 21:44:45 +08:00
1 parent 8c755a5c36
commit eb7d300ac2
3 files changed
+10 -6
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fpga/retrosoc_top.v
+4
View File
@@ -15,6 +15,8 @@ module retrosoc_top (
output cust_pwm_pwm_o,
input cust_ps2_ps2_clk_i,
input cust_ps2_ps2_dat_i,
inout cust_i2c_scl_io,
inout cust_i2c_sda_io,
output cust_qspi_spi_clk_o,
output cust_qspi_spi_csn_0_o,
inout cust_qspi_dat_0_io,
@@ -79,6 +81,8 @@ module retrosoc_top (
.cust_pwm_pwm_3_o_pad (),
.cust_ps2_ps2_clk_i_pad (cust_ps2_ps2_clk_i),
.cust_ps2_ps2_dat_i_pad (cust_ps2_ps2_dat_i),
.cust_i2c_scl_io_pad (cust_i2c_scl_io),
.cust_i2c_sda_io_pad (cust_i2c_sda_io),
.cust_qspi_spi_clk_o_pad (cust_qspi_spi_clk_o),
.cust_qspi_spi_csn_0_o_pad(cust_qspi_spi_csn_0_o),
.cust_qspi_spi_csn_1_o_pad(),
fpga/starrysky_v2.xdc
+3 -3
View File
@@ -10,14 +10,14 @@ set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS18} [get_ports gpio_io1]
set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS18} [get_ports pwm_pwm_o]
# set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS18} [get_ports i2c_scl_io]
# set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS18} [get_ports i2c_sda_io]
set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS18} [get_ports cust_uart_tx_o]
set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS18} [get_ports cust_uart_rx_i]
set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS18} [get_ports cust_pwm_pwm_o]
set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS18} [get_ports cust_ps2_ps2_clk_i]
set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18} [get_ports cust_ps2_ps2_dat_i]
set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS18} [get_ports cust_i2c_scl_io]
set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS18} [get_ports cust_i2c_sda_io]
set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS18} [get_ports cust_spfs_cs_o]
set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS18} [get_ports cust_spfs_clk_o]
set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS18} [get_ports cust_spfs_mosi_o]
rtl/ip/axil_ip_wrapper.v
+3 -3
View File
@@ -174,7 +174,7 @@ module axil_ip_wrapper (
.pwdata (s_m_apb_pwdata),
.pstrb (s_m_apb_pstrb),
.pready (s_m_apb_pready[5]),
.prdata (s_m_apb_prdata5),
.prdata (s_m_apb_prdata6),
.pslverr (s_m_apb_pslverr[5]),
.scl_i (i2c_scl_i),
.scl_o (i2c_scl_o),
@@ -196,7 +196,7 @@ module axil_ip_wrapper (
.PWRITE (s_m_apb_pwrite),
.PSEL (s_m_apb_psel[6]),
.PENABLE (s_m_apb_penable),
.PRDATA (s_m_apb_prdata6),
.PRDATA (s_m_apb_prdata7),
.PREADY (s_m_apb_pready[6]),
.PSLVERR (s_m_apb_pslverr[6]),
.spi_clk (qspi_spi_clk_o),
@@ -233,7 +233,7 @@ module axil_ip_wrapper (
.pwdata (s_m_apb_pwdata),
.pwstrb (4'hF),
.pready (s_m_apb_pready[7]),
.prdata (s_m_apb_prdata7),
.prdata (s_m_apb_prdata8),
.pslverr (s_m_apb_pslverr[7]),
.spi_clk (spfs_clk_o),
.spi_cs (spfs_cs_o),