feat: change sram to the 64KB

syn/synth_retrosoc.ys

@@ -2,10 +2,10 @@ read_verilog ../rtl/spram_model.v
 read_verilog ../rtl/picorv32.v
 read_verilog ../rtl/spimemio.v
 read_verilog ../rtl/simpleuart.v
-read_verilog ../rtl/picosoc.v
 read_verilog ../rtl/retrosoc.v
+read_verilog ../rtl/retrosoc_asic.v
 
-hierarchy -top retrosoc
+hierarchy -top retrosoc_asic
 proc; flatten
 
 synth;

syn/yosys/scripts/yosys_synthesis.tcl

@@ -35,8 +35,8 @@ yosys read_verilog ../../rtl/spram_model.v
 yosys read_verilog ../../rtl/picorv32.v
 yosys read_verilog ../../rtl/spimemio.v
 yosys read_verilog ../../rtl/simpleuart.v
-yosys read_verilog ../../rtl/picosoc.v
 yosys read_verilog ../../rtl/retrosoc.v
+yosys read_verilog ../../rtl/retrosoc_asic.v
 
 # # blackbox requested modules
 # if { [info exists ::env(YOSYS_BLACKBOX_MODULES)] } {

syn/yosys/yosys.mk

@@ -18,8 +18,8 @@ YOSYS_REPORTS   := $(YOSYS_DIR)/reports
 # Project variables
 include $(YOSYS_DIR)/project-synth.mk
 
-TOP_DESIGN      ?= retrosoc
-RTL_NAME        ?= retrosoc
+TOP_DESIGN      ?= retrosoc_asic
+RTL_NAME        ?= retrosoc_asic
 
 VLOG_FILES      := $(RTL_NAME)_sv2v.v
 NETLIST         := $(YOSYS_OUT)/$(RTL_NAME)_yosys.v

tech/tc_sram.v

@@ -1,11 +1,11 @@
 module tc_sram_1024x32 (
-    input             clk_i,
-    input             cs_i,
-    input      [ 9:0] addr_i,
-    input      [31:0] data_i,
-    input      [ 3:0] mask_i,
-    input             wren_i,
-    output reg [31:0] data_o
+    input         clk_i,
+    input         cs_i,
+    input  [ 9:0] addr_i,
+    input  [31:0] data_i,
+    input  [ 3:0] mask_i,
+    input         wren_i,
+    output [31:0] data_o
 );
 
   wire [15:0] s_rd_data_mem1, s_rd_data_mem2;
@@ -13,7 +13,7 @@ module tc_sram_1024x32 (
 
   RM_IHPSG13_1P_1024x16_c2_bm_bist u_mem1 (
       .A_CLK      (clk_i),
-      .A_ADDR     (addr_i[9:0]),
+      .A_ADDR     (addr_i),
       .A_BM       ({{8{mask_i[1]}}, {8{mask_i[0]}}}),
       .A_MEN      (cs_i),
       .A_WEN      (wren_i),
@@ -33,7 +33,7 @@ module tc_sram_1024x32 (
 
   RM_IHPSG13_1P_1024x16_c2_bm_bist u_mem2 (
       .A_CLK      (clk_i),
-      .A_ADDR     (addr_i[9:0]),
+      .A_ADDR     (addr_i),
       .A_BM       ({{8{mask_i[3]}}, {8{mask_i[2]}}}),
       .A_MEN      (cs_i),
       .A_WEN      (wren_i),
@@ -51,3 +51,29 @@ module tc_sram_1024x32 (
       .A_DLY      (1'b0)
   );
 endmodule
+
+// 4KB
+module SPRAM1024X16 (
+    input             clk_i,
+    input             cs_i,
+    input      [ 9:0] addr_i,
+    input      [15:0] data_i,
+    input      [ 3:0] mask_i,
+    input             wren_i,
+    output reg [15:0] data_o
+);
+  reg [15:0] mem[0:1023];
+  always @(posedge clk_i) begin
+    if (cs_i) begin
+      if (!wren_i) begin
+        data_o <= mem[addr_i];
+      end else begin
+        if (mask_i[0]) mem[addr_i][7:0] <= data_i[7:0];
+        if (mask_i[1]) mem[addr_i][15:8] <= data_i[15:8];
+        if (mask_i[2]) mem[addr_i][23:16] <= data_i[23:16];
+        if (mask_i[3]) mem[addr_i][31:24] <= data_i[31:24];
+        data_o <= 32'bx;
+      end
+    end
+  end
+endmodule