mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
feat: remove support for XEZIM and CVC simulators
- Deleted references to XEZIM and CVC in the Makefile and related scripts. - Removed XEZIM-specific and CVC-specific files, including external memory models and SRAM models. - Updated the test suite to reflect the removal of XEZIM and CVC simulators, ensuring no broken references remain. - Cleaned up the README and doctor scripts to remove mentions of XEZIM and CVC.
This commit is contained in:
16 files changed
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@@ -159,12 +159,6 @@ warning checks, and metric collection.
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newline or when simulation ends. Treat `sim.log` and `result-sim*.json` as
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the verdict; delayed terminal UART display is a known operational condition,
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not evidence that the simulation has failed.
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- `SIMU=XEZIM` is an optional IHP130 RTL-behavior flow and `SIMU=CVC` is an
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optional synthesized, zero-delay netlist flow. They reuse generated
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filelists and result checks but are outside the locked CI matrix. Both use
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compact functional external-memory models; do not treat their results as a
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replacement for the supported Verilator/Icarus/VCS or OpenSTA coverage.
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## Before Hand-off
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1. State the selected profile and commands run.
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@@ -121,7 +121,7 @@ FLOW_FILELIST_DIR := $(SIM_BUILD_ROOT)/filelists
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endif
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VALID_SOC := MINI
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VALID_SIMU := VCS VERILATOR IVERILOG XEZIM CVC
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VALID_SIMU := VCS VERILATOR IVERILOG
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VALID_SYNTH := NONE YOSYS
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VALID_SYNTH_RECIPE := balanced area speed
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VALID_STA := NONE OPENSTA
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@@ -41,9 +41,9 @@ under the [Mulan Permissive Software License, Version 2](LICENSE).
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support. Available interfaces depend on the selected SoC configuration.
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- A standalone RISC-V runtime, HAL, board support, middleware, and `benchmark`, `bringup`,
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`coremark`, `debug`, and `shell` applications.
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- Open-source behavioral simulation with Icarus Verilog and Verilator, optional RTL
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behavior simulation with Xezim, synthesis with Yosys, netlist simulation with
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Icarus Verilog or optional CVC, and timing analysis with OpenSTA.
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- Open-source behavioral simulation with Icarus Verilog and Verilator,
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synthesis with Yosys, netlist simulation with Icarus Verilog, and timing
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analysis with OpenSTA.
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- Read-only ARCHINFO ABI discovery for build/configuration provenance, SoC
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topology, technology capabilities, and lifecycle-gated device identity.
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- Checksum-verified dependency and toolchain locks, structured flow results, warning
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@@ -170,29 +170,6 @@ make CONFIG=configs/ci/ihp130.mk firmware
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make CONFIG=configs/ci/ihp130.mk SIMU=IVERILOG sim
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```
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Xezim and CVC are optional local backends. They are not included in the locked
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development environment or the default CI matrix. Set their executable paths
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explicitly before use:
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```sh
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export XEZIM=/path/to/xezim
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export CVC=/path/to/cvc64
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export BUILD_TIMESTAMP=2026-08-22-00-00
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make CONFIG=configs/ci/ihp130.mk SIMU=XEZIM BUILD_TIMESTAMP="$BUILD_TIMESTAMP" firmware sim
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make CONFIG=configs/ci/ihp130.mk BUILD_TIMESTAMP="$BUILD_TIMESTAMP" firmware
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make CONFIG=configs/ci/ihp130.mk SYNTH=YOSYS BUILD_TIMESTAMP="$BUILD_TIMESTAMP" synth
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make CONFIG=configs/ci/ihp130.mk SIMU=CVC SYNTH=YOSYS BUILD_TIMESTAMP="$BUILD_TIMESTAMP" netsim
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```
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Xezim is limited to RTL behavior simulation in this integration. CVC is
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limited to synthesized, zero-delay netlist simulation; neither backend is a
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replacement for the supported Verilator/Icarus/VCS baseline or for OpenSTA
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timing analysis. The optional behavior flows use compact external-memory
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models and the IHP130 `PDK_BEHAV` path; they are intended for protocol and
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bring-up checks, not PDK-model or signoff coverage. Keep the same
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`BUILD_TIMESTAMP` when sharing generated artifacts between synthesis and
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netlist simulation commands.
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Select the interactive shell application without editing source files:
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```sh
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@@ -231,12 +208,10 @@ make CONFIG=configs/ci/ihp130.mk SIMU=IVERILOG \
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| --- | --- |
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| Icarus behavioral simulation | `make CONFIG=configs/ci/ihp130.mk SIMU=IVERILOG sim` |
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| Verilator behavioral simulation | `make CONFIG=configs/ci/ihp130.mk SIMU=VERILATOR sim` |
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| Xezim RTL behavioral simulation (optional) | `make CONFIG=configs/ci/ihp130.mk SIMU=XEZIM sim` |
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| Hazard3 JTAG debug acceptance | `make CONFIG=configs/ci/ihp130-debug.mk SIMU=VERILATOR debug-sim` |
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| Assembly self-test with Icarus | `make CONFIG=configs/ci/ihp130.mk SIMU=IVERILOG RTL_SIM_TIMEOUT=5200000 sim-asm` |
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| Yosys synthesis | `make CONFIG=configs/ci/ihp130.mk SYNTH=YOSYS synth` |
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| Icarus netlist simulation after synthesis | `make CONFIG=configs/ci/ihp130.mk SIMU=IVERILOG netsim` |
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| CVC netlist simulation after synthesis (optional) | `make CONFIG=configs/ci/ihp130.mk SIMU=CVC SYNTH=YOSYS netsim` |
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| OpenSTA core timing analysis after synthesis | `make CONFIG=configs/ci/ihp130.mk STA=OPENSTA sta` |
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| Strict Verilator RTL lint | `make CONFIG=configs/ci/ihp130.mk SIMU=VERILATOR HAVE_SVA=YES check-rtl-lint` |
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| Hazard3 CoreMark quick report | `make CONFIG=configs/benchmark/ihp130-hazard3-coremark.mk SIMU=VERILATOR coremark-report` |
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@@ -17,11 +17,6 @@ specific to a checkout and continue to be installed by make setup or
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make setup-regression. The latter prepares the four pull-request PDK profiles
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in a fixed order.
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The optional Xezim and CVC simulation backends are also outside the locked
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environment. They must be installed separately and selected through explicit
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`XEZIM` and `CVC` executable paths. They are local compatibility tools, not
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reproducible CI inputs.
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## Shared Bootstrap
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scripts/development_environment.py is the only tool installer for the three
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@@ -52,24 +52,6 @@ VCS flows remain cluster-only because public runners do not have the licensed
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simulator. ICS55 uses the same variant layout, manifests, result JSON, warning
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scanner, and cleanup rules as the other open-source CI PDKs.
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## Optional Simulation Backends
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The default simulator and regression matrix remain unchanged. `SIMU=XEZIM`
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adds an optional RTL behavior flow, while `SIMU=CVC` adds an optional
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post-synthesis, zero-delay netlist flow. Both backends reuse the generated
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profile filelists, firmware preparation, `scripts/run_flow.py`, structured
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result JSON, and `check_simulation.py` terminal marker checks.
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These tools are not installed by `scripts/development_environment.py` and are
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not entries in `dependencies/dependencies.lock.json`. Supply local executable
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paths with the `XEZIM` and `CVC` environment variables. Xezim does not provide
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the integrated netlist or SDF flow, and CVC does not provide the integrated
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post-layout SDF flow. Neither result replaces the Verilator/Icarus/VCS baseline
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or OpenSTA timing analysis. The IHP130 Xezim and CVC testbenches substitute
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small functional models for the large vendor flash, PSRAM, SDRAM, camera, and
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EEPROM models so that the optional tools can parse and elaborate the design;
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the supported baseline remains the authority for full external-model coverage.
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## Reproducible Inputs
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`dependencies/dependencies.lock.json` is the source of truth for external Git repositories, downloaded
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@@ -176,10 +176,6 @@ else ifeq ($(SIMU), VERILATOR)
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include $(RTL_PATH)/mk/verilator.mk
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else ifeq ($(SIMU), IVERILOG)
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include $(RTL_PATH)/mk/iverilog.mk
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else ifeq ($(SIMU), XEZIM)
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include $(RTL_PATH)/mk/xezim.mk
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else ifeq ($(SIMU), CVC)
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include $(RTL_PATH)/mk/cvc.mk
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endif
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.PHONY: gen_mpw_code generate_filelist memory-map check-memory-map pin-map check-pin-map \
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@@ -16,11 +16,7 @@ module retrosoc_tb;
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localparam real XTAL_CPU_FREQ = 24.0;
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localparam real EXT_CPU_FREQ = 72.0;
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localparam real AUD_CPU_FREQ = 18.432;
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`ifdef SIMU_CVC
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localparam integer ResetHoldTime = 170744;
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`else
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localparam time ResetHoldTime = 170744ns;
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`endif
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integer sim_runtime;
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@@ -153,10 +149,8 @@ module retrosoc_tb;
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);
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`ifndef SIMU_CVC
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pullup u_i2c0_scl_pullup (s_i2c0_scl_io);
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pullup u_i2c0_sda_pullup (s_i2c0_sda_io);
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`endif
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AT24C04 u_AT24C04_0 (
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.WP (1'b0),
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.SCL(s_i2c0_scl_io),
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@@ -182,9 +176,7 @@ module retrosoc_tb;
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);
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`ifndef SIMU_CVC
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pullup u_psram_nss0_pullup (s_psram_nss0);
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`endif
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ESP_PSRAM64H #(0) u_ESP_PSRAM64H_0 (
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.sclk(s_psram_sck),
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.csn (s_psram_nss0),
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@@ -192,27 +184,21 @@ module retrosoc_tb;
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);
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`ifndef SIMU_CVC
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pullup u_psram_nss1_pullup (s_psram_nss1);
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`endif
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ESP_PSRAM64H #(1) u_ESP_PSRAM64H_1 (
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.sclk(s_psram_sck),
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.csn (s_psram_nss1),
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.sio ({s_psram_dat3, s_psram_dat2, s_psram_dat1, s_psram_dat0})
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);
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`ifndef SIMU_CVC
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pullup u_psram_nss2_pullup (s_psram_nss2);
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`endif
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ESP_PSRAM64H #(2) u_ESP_PSRAM64H_2 (
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.sclk(s_psram_sck),
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.csn (s_psram_nss2),
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.sio ({s_psram_dat3, s_psram_dat2, s_psram_dat1, s_psram_dat0})
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);
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`ifndef SIMU_CVC
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pullup u_psram_nss3_pullup (s_psram_nss3);
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`endif
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ESP_PSRAM64H #(3) u_ESP_PSRAM64H_3 (
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.sclk(s_psram_sck),
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.csn (s_psram_nss3),
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@@ -1,420 +0,0 @@
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// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of the Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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//
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// Compact models for the optional Xezim and CVC flows.
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// The production Icarus/VCS testbench continues to use the vendor models.
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`timescale 1ns / 1ps
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module W25Q128JVxIM (
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input wire CSn,
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input wire CLK,
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inout wire DIO,
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inout wire DO,
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inout wire WPn,
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inout wire HOLDn
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);
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localparam integer MEMORY_BYTES = 65536;
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localparam [7:0] CMD_QUAD_READ = 8'hEB;
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localparam [7:0] CMD_READ = 8'h03;
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localparam [7:0] CMD_FAST_READ = 8'h0B;
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localparam [7:0] CMD_READ_ID = 8'h9F;
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reg [ 7:0] memory [0:MEMORY_BYTES - 1];
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reg [ 7:0] command;
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reg [23:0] address;
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reg [ 7:0] mode;
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reg [ 7:0] output_byte;
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reg [ 3:0] output_nibble;
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reg [ 2:0] bit_count;
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reg [ 2:0] nibble_count;
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reg [ 3:0] dummy_count;
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reg [ 2:0] state;
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reg output_enable;
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reg output_quad;
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localparam [2:0] STATE_COMMAND = 3'd0;
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localparam [2:0] STATE_ADDRESS = 3'd1;
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localparam [2:0] STATE_MODE = 3'd2;
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localparam [2:0] STATE_DUMMY = 3'd3;
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localparam [2:0] STATE_READ = 3'd4;
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assign DIO = (output_enable && output_quad) ? output_nibble[0] : 1'bz;
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assign DO = output_enable ? (output_quad ? output_nibble[1] : output_nibble[0]) : 1'bz;
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assign WPn = (output_enable && output_quad) ? output_nibble[2] : 1'bz;
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assign HOLDn = (output_enable && output_quad) ? output_nibble[3] : 1'bz;
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initial begin
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$readmemh("MEM.TXT", memory);
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command = 8'h00;
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address = 24'h000000;
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mode = 8'h00;
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output_byte = 8'h00;
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output_nibble = 4'h0;
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bit_count = 3'd0;
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nibble_count = 3'd0;
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dummy_count = 3'd0;
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state = STATE_COMMAND;
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output_enable = 1'b0;
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output_quad = 1'b0;
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end
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always @(negedge CSn) begin
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state = STATE_COMMAND;
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bit_count = 3'd0;
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nibble_count = 3'd0;
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dummy_count = 3'd0;
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output_enable = 1'b0;
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output_quad = 1'b0;
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end
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always @(posedge CLK) begin
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if (!CSn) begin
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case (state)
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STATE_COMMAND: begin
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command = {command[6:0], DIO};
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if (bit_count == 3'd7) begin
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bit_count = 3'd0;
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if ({command[6:0], DIO} == CMD_READ_ID) begin
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output_byte = 8'hEF;
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state = STATE_READ;
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output_quad = 1'b0;
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end else begin
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state = STATE_ADDRESS;
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output_quad = ({command[6:0], DIO} == CMD_QUAD_READ);
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end
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end else begin
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bit_count = bit_count + 1'b1;
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end
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end
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STATE_ADDRESS: begin
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if (output_quad) begin
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address = {address[19:0], DIO, DO, WPn, HOLDn};
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if (nibble_count == 3'd5) begin
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nibble_count = 3'd0;
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mode = 8'h00;
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state = STATE_MODE;
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end else begin
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nibble_count = nibble_count + 1'b1;
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end
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end else begin
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address = {address[22:0], DIO};
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if (bit_count == 3'd7) begin
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bit_count = 3'd0;
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state = (command == CMD_FAST_READ) ? STATE_DUMMY : STATE_READ;
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dummy_count = (command == CMD_FAST_READ) ? 4'd8 : 4'd0;
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end else begin
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bit_count = bit_count + 1'b1;
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end
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end
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end
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STATE_MODE: begin
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mode = {mode[3:0], DIO, DO, WPn, HOLDn};
|
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if (nibble_count == 3'd1) begin
|
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nibble_count = 3'd0;
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dummy_count = 3'd4;
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state = STATE_DUMMY;
|
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end else begin
|
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nibble_count = nibble_count + 1'b1;
|
||||
end
|
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end
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STATE_DUMMY: begin
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if (dummy_count == 3'd1) begin
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output_byte = memory[address[15:0]];
|
||||
nibble_count = 3'd0;
|
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state = STATE_READ;
|
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end else begin
|
||||
dummy_count = dummy_count - 1'b1;
|
||||
end
|
||||
end
|
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STATE_READ: begin
|
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if (nibble_count == 3'd1) begin
|
||||
nibble_count = 3'd0;
|
||||
address = address + 1'b1;
|
||||
output_byte = memory[address[15:0]+1'b1];
|
||||
end else begin
|
||||
nibble_count = nibble_count + 1'b1;
|
||||
end
|
||||
end
|
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default: state = STATE_COMMAND;
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endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(negedge CLK) begin
|
||||
if (!CSn && (state == STATE_READ)) begin
|
||||
output_enable = 1'b1;
|
||||
if (command == CMD_READ_ID) begin
|
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output_quad = 1'b0;
|
||||
output_nibble[0] = (nibble_count == 3'd0) ? 1'b0 : 1'b0;
|
||||
end else if (output_quad) begin
|
||||
output_nibble = (nibble_count == 3'd0) ? output_byte[7:4] : output_byte[3:0];
|
||||
end else begin
|
||||
output_nibble[0] = output_byte[7];
|
||||
output_byte = {output_byte[6:0], 1'b0};
|
||||
end
|
||||
end else begin
|
||||
output_enable = 1'b0;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module ESP_PSRAM64H #(
|
||||
parameter integer ID = 0
|
||||
) (
|
||||
input wire sclk,
|
||||
input wire csn,
|
||||
inout wire [3:0] sio
|
||||
);
|
||||
localparam integer MEMORY_BYTES = 128 * 1024;
|
||||
localparam [7:0] CMD_READ = 8'h03;
|
||||
localparam [7:0] CMD_FAST_READ = 8'h0B;
|
||||
localparam [7:0] CMD_QUAD_READ = 8'hEB;
|
||||
localparam [7:0] CMD_WRITE = 8'h02;
|
||||
localparam [7:0] CMD_QUAD_WRITE = 8'h38;
|
||||
localparam [7:0] CMD_ENTER_QPI = 8'h35;
|
||||
localparam [7:0] CMD_RESET = 8'h99;
|
||||
localparam [7:0] CMD_READ_ID = 8'h9F;
|
||||
|
||||
reg [ 7:0] memory [0:MEMORY_BYTES - 1];
|
||||
reg [ 7:0] command;
|
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reg [23:0] address;
|
||||
reg [ 7:0] output_byte;
|
||||
reg [ 3:0] output_nibble;
|
||||
reg [ 2:0] bit_count;
|
||||
reg [ 2:0] nibble_count;
|
||||
reg [ 3:0] dummy_count;
|
||||
reg [ 2:0] state;
|
||||
reg qpi_mode;
|
||||
reg output_enable;
|
||||
reg output_quad;
|
||||
reg write_mode;
|
||||
|
||||
localparam [2:0] STATE_COMMAND = 3'd0;
|
||||
localparam [2:0] STATE_ADDRESS = 3'd1;
|
||||
localparam [2:0] STATE_DUMMY = 3'd2;
|
||||
localparam [2:0] STATE_READ = 3'd3;
|
||||
localparam [2:0] STATE_WRITE = 3'd4;
|
||||
|
||||
assign sio = output_enable ? (output_quad ? output_nibble : {2'bzz, output_nibble[1:0]}) : 4'bz;
|
||||
|
||||
initial begin
|
||||
command = 8'h00;
|
||||
address = 24'h000000;
|
||||
output_byte = 8'h00;
|
||||
output_nibble = 4'h0;
|
||||
bit_count = 3'd0;
|
||||
nibble_count = 3'd0;
|
||||
dummy_count = 4'd0;
|
||||
state = STATE_COMMAND;
|
||||
qpi_mode = 1'b1;
|
||||
output_enable = 1'b0;
|
||||
output_quad = 1'b0;
|
||||
write_mode = 1'b0;
|
||||
end
|
||||
|
||||
always @(negedge csn) begin
|
||||
state = STATE_COMMAND;
|
||||
bit_count = 3'd0;
|
||||
nibble_count = 3'd0;
|
||||
dummy_count = 4'd0;
|
||||
output_enable = 1'b0;
|
||||
output_quad = qpi_mode;
|
||||
write_mode = 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge sclk) begin
|
||||
if (!csn) begin
|
||||
case (state)
|
||||
STATE_COMMAND: begin
|
||||
if (qpi_mode) begin
|
||||
if (nibble_count == 3'd0) begin
|
||||
command[7:4] = sio;
|
||||
nibble_count = 3'd1;
|
||||
end else begin
|
||||
command[3:0] = sio;
|
||||
nibble_count = 3'd0;
|
||||
if ((command == CMD_RESET) || (command == CMD_ENTER_QPI)) begin
|
||||
state = STATE_READ;
|
||||
end else begin
|
||||
state = STATE_ADDRESS;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
command = {command[6:0], sio[0]};
|
||||
if (bit_count == 3'd7) begin
|
||||
bit_count = 3'd0;
|
||||
if ((command == CMD_RESET) || (command == CMD_ENTER_QPI)) begin
|
||||
state = STATE_READ;
|
||||
end else begin
|
||||
state = STATE_ADDRESS;
|
||||
end
|
||||
end else begin
|
||||
bit_count = bit_count + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
STATE_ADDRESS: begin
|
||||
if (qpi_mode) begin
|
||||
address = {address[19:0], sio};
|
||||
if (nibble_count == 3'd5) begin
|
||||
nibble_count = 3'd0;
|
||||
if (command == CMD_QUAD_READ) begin
|
||||
dummy_count = 4'd6;
|
||||
state = STATE_DUMMY;
|
||||
end else if ((command == CMD_READ_ID) || (command == CMD_READ) ||
|
||||
(command == CMD_FAST_READ)) begin
|
||||
output_byte = (command == CMD_READ_ID) ? 8'h00 : memory[address[16:0]];
|
||||
state = STATE_READ;
|
||||
end else begin
|
||||
write_mode = (command == CMD_QUAD_WRITE);
|
||||
state = STATE_WRITE;
|
||||
end
|
||||
end else begin
|
||||
nibble_count = nibble_count + 1'b1;
|
||||
end
|
||||
end else begin
|
||||
address = {address[22:0], sio[0]};
|
||||
if (bit_count == 3'd7) begin
|
||||
bit_count = 3'd0;
|
||||
output_byte = (command == CMD_READ_ID) ? 8'h00 : memory[address[16:0]];
|
||||
state = STATE_READ;
|
||||
end else begin
|
||||
bit_count = bit_count + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
STATE_DUMMY: begin
|
||||
if (dummy_count == 4'd1) begin
|
||||
output_byte = memory[address[16:0]];
|
||||
nibble_count = 3'd0;
|
||||
state = STATE_READ;
|
||||
end else begin
|
||||
dummy_count = dummy_count - 1'b1;
|
||||
end
|
||||
end
|
||||
STATE_READ: begin
|
||||
if (output_quad) begin
|
||||
if (nibble_count == 3'd1) begin
|
||||
nibble_count = 3'd0;
|
||||
address = address + 1'b1;
|
||||
output_byte = memory[address[16:0]+1'b1];
|
||||
end else begin
|
||||
nibble_count = nibble_count + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
STATE_WRITE: begin
|
||||
if (qpi_mode || write_mode) begin
|
||||
if (nibble_count == 3'd0) begin
|
||||
memory[address[16:0]][7:4] = sio;
|
||||
nibble_count = 3'd1;
|
||||
end else begin
|
||||
memory[address[16:0]][3:0] = sio;
|
||||
nibble_count = 3'd0;
|
||||
address = address + 1'b1;
|
||||
end
|
||||
end else begin
|
||||
memory[address[16:0]] = {memory[address[16:0]][6:0], sio[0]};
|
||||
end
|
||||
end
|
||||
default: state = STATE_COMMAND;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(negedge sclk) begin
|
||||
if (!csn && (state == STATE_READ)) begin
|
||||
output_enable = 1'b1;
|
||||
if (command == CMD_READ_ID) begin
|
||||
output_quad = qpi_mode;
|
||||
output_nibble = (address[2:0] == 3'd0) ? 4'h0 : (address[2:0] == 3'd1) ? 4'h5 : 4'h2;
|
||||
end else if (output_quad) begin
|
||||
output_nibble = (nibble_count == 3'd0) ? output_byte[7:4] : output_byte[3:0];
|
||||
end else begin
|
||||
output_nibble[1] = output_byte[7];
|
||||
output_byte = {output_byte[6:0], 1'b0};
|
||||
end
|
||||
end else begin
|
||||
output_enable = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge csn) begin
|
||||
output_enable = 1'b0;
|
||||
if (command == CMD_ENTER_QPI) qpi_mode = 1'b1;
|
||||
if (command == CMD_RESET) qpi_mode = 1'b0;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module sdr (
|
||||
inout wire [15:0] Dq,
|
||||
input wire [12:0] Addr,
|
||||
input wire [ 1:0] Ba,
|
||||
input wire Clk,
|
||||
input wire Cke,
|
||||
input wire Cs_n,
|
||||
input wire Ras_n,
|
||||
input wire Cas_n,
|
||||
input wire We_n,
|
||||
input wire [ 1:0] Dqm
|
||||
);
|
||||
reg [15:0] memory [0:65535];
|
||||
reg [12:0] active_row [ 0:3];
|
||||
reg [15:0] read_data;
|
||||
reg read_enable;
|
||||
integer index;
|
||||
|
||||
assign Dq = read_enable ? read_data : 16'bz;
|
||||
|
||||
initial begin
|
||||
read_enable = 1'b0;
|
||||
read_data = 16'h0000;
|
||||
for (index = 0; index < 4; index = index + 1) active_row[index] = 13'h0000;
|
||||
end
|
||||
|
||||
always @(posedge Clk) begin
|
||||
read_enable = 1'b0;
|
||||
if (Cke && !Cs_n) begin
|
||||
if (!Ras_n && Cas_n && We_n) begin
|
||||
active_row[Ba] = Addr;
|
||||
end else if (Ras_n && !Cas_n && !We_n) begin
|
||||
if (!Dqm[0]) memory[{Ba, active_row[Ba][7:0], Addr[5:0]}][7:0] = Dq[7:0];
|
||||
if (!Dqm[1]) memory[{Ba, active_row[Ba][7:0], Addr[5:0]}][15:8] = Dq[15:8];
|
||||
end else if (Ras_n && !Cas_n && We_n) begin
|
||||
read_data = memory[{Ba, active_row[Ba][7:0], Addr[5:0]}];
|
||||
read_enable = 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module AT24C04 (
|
||||
input wire WP,
|
||||
input wire SCL,
|
||||
inout wire SDA
|
||||
);
|
||||
assign SDA = 1'bz;
|
||||
endmodule
|
||||
|
||||
module dvp_camera (
|
||||
output wire pclk_o,
|
||||
output wire href_o,
|
||||
output wire vsync_o,
|
||||
output wire [7:0] dat_o
|
||||
);
|
||||
reg pclk;
|
||||
assign pclk_o = pclk;
|
||||
assign href_o = 1'b0;
|
||||
assign vsync_o = 1'b0;
|
||||
assign dat_o = 8'h00;
|
||||
initial pclk = 1'b0;
|
||||
always #5 pclk = ~pclk;
|
||||
endmodule
|
||||
@@ -1,120 +0,0 @@
|
||||
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
|
||||
// retroSoC is licensed under Mulan PSL v2.
|
||||
// You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
// You may obtain a copy of the Mulan PSL v2 at:
|
||||
// http://license.coscl.org.cn/MulanPSL2
|
||||
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
|
||||
// See the Mulan PSL v2 for more details.
|
||||
//
|
||||
// Xezim-only functional substitutes for the IHP130 SRAM wrappers.
|
||||
// The production RTL and the Icarus/VCS PDK filelists keep the original models.
|
||||
|
||||
module RM_IHPSG13_1P_1024x64_c2_bm_bist (
|
||||
input logic A_CLK,
|
||||
input logic A_MEN,
|
||||
input logic A_WEN,
|
||||
input logic A_REN,
|
||||
input logic [ 9:0] A_ADDR,
|
||||
input logic [63:0] A_DIN,
|
||||
input logic A_DLY,
|
||||
output logic [63:0] A_DOUT,
|
||||
input logic [63:0] A_BM,
|
||||
input logic A_BIST_CLK,
|
||||
input logic A_BIST_EN,
|
||||
input logic A_BIST_MEN,
|
||||
input logic A_BIST_WEN,
|
||||
input logic A_BIST_REN,
|
||||
input logic [ 9:0] A_BIST_ADDR,
|
||||
input logic [63:0] A_BIST_DIN,
|
||||
input logic [63:0] A_BIST_BM
|
||||
);
|
||||
logic [63:0] memory[0:1023];
|
||||
integer index;
|
||||
|
||||
always_ff @(posedge A_CLK) begin
|
||||
if (A_MEN && A_WEN) begin
|
||||
for (index = 0; index < 64; index = index + 1) begin
|
||||
if (A_BM[index]) begin
|
||||
memory[A_ADDR][index] <= A_DIN[index];
|
||||
end
|
||||
end
|
||||
end
|
||||
if (A_MEN && A_REN) begin
|
||||
A_DOUT <= memory[A_ADDR];
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module RM_IHPSG13_1P_4096x16_c3_bm_bist (
|
||||
input logic A_CLK,
|
||||
input logic A_MEN,
|
||||
input logic A_WEN,
|
||||
input logic A_REN,
|
||||
input logic [11:0] A_ADDR,
|
||||
input logic [15:0] A_DIN,
|
||||
input logic A_DLY,
|
||||
output logic [15:0] A_DOUT,
|
||||
input logic [15:0] A_BM,
|
||||
input logic A_BIST_CLK,
|
||||
input logic A_BIST_EN,
|
||||
input logic A_BIST_MEN,
|
||||
input logic A_BIST_WEN,
|
||||
input logic A_BIST_REN,
|
||||
input logic [11:0] A_BIST_ADDR,
|
||||
input logic [15:0] A_BIST_DIN,
|
||||
input logic [15:0] A_BIST_BM
|
||||
);
|
||||
logic [15:0] memory[0:4095];
|
||||
integer index;
|
||||
|
||||
always_ff @(posedge A_CLK) begin
|
||||
if (A_MEN && A_WEN) begin
|
||||
for (index = 0; index < 16; index = index + 1) begin
|
||||
if (A_BM[index]) begin
|
||||
memory[A_ADDR][index] <= A_DIN[index];
|
||||
end
|
||||
end
|
||||
end
|
||||
if (A_MEN && A_REN) begin
|
||||
A_DOUT <= memory[A_ADDR];
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module RM_IHPSG13_1P_4096x8_c3_bm_bist (
|
||||
input logic A_CLK,
|
||||
input logic A_MEN,
|
||||
input logic A_WEN,
|
||||
input logic A_REN,
|
||||
input logic [11:0] A_ADDR,
|
||||
input logic [ 7:0] A_DIN,
|
||||
input logic A_DLY,
|
||||
output logic [ 7:0] A_DOUT,
|
||||
input logic [ 7:0] A_BM,
|
||||
input logic A_BIST_CLK,
|
||||
input logic A_BIST_EN,
|
||||
input logic A_BIST_MEN,
|
||||
input logic A_BIST_WEN,
|
||||
input logic A_BIST_REN,
|
||||
input logic [11:0] A_BIST_ADDR,
|
||||
input logic [ 7:0] A_BIST_DIN,
|
||||
input logic [ 7:0] A_BIST_BM
|
||||
);
|
||||
logic [7:0] memory[0:4095];
|
||||
integer index;
|
||||
|
||||
always_ff @(posedge A_CLK) begin
|
||||
if (A_MEN && A_WEN) begin
|
||||
for (index = 0; index < 8; index = index + 1) begin
|
||||
if (A_BM[index]) begin
|
||||
memory[A_ADDR][index] <= A_DIN[index];
|
||||
end
|
||||
end
|
||||
end
|
||||
if (A_MEN && A_REN) begin
|
||||
A_DOUT <= memory[A_ADDR];
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
@@ -1,77 +0,0 @@
|
||||
CVC ?= cvc
|
||||
SV2V ?= sv2v
|
||||
|
||||
# Gate-level netlists have no usable delay data. Disable timing checks during
|
||||
# compilation while leaving unrelated CVC diagnostics visible.
|
||||
CVC_TIMING_OPTS ?= +nospecify +notimingchecks
|
||||
|
||||
NETLIST_PATH ?= $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.v
|
||||
|
||||
CVC_ROOT := $(SIM_BUILD_ROOT)
|
||||
CVC_NETL_DIR := $(NETLIST_SIM_ROOT)
|
||||
CVC_NETL_FLIST := $(CVC_NETL_DIR)/cvc.fl
|
||||
CVC_NETL_TB := $(CVC_NETL_DIR)/retrosoc_tb.v
|
||||
CVC_NETL_SIMV := $(CVC_NETL_DIR)/simv
|
||||
CVC_FILELIST := $(RTL_PATH)/script/gen_sim_filelist.py
|
||||
CVC_TB_CONVERT := $(RTL_PATH)/script/convt_sv2v.py
|
||||
CVC_FILELISTS := $(filter-out $(GENERATED_FL_DIR)/commonip.fl $(GENERATED_FL_DIR)/inc.fl,$(NET_FILELISTS))
|
||||
CVC_TB_FLIST := $(GENERATED_FL_DIR)/tb.fl
|
||||
CVC_TB_FILTERED_FLIST := $(CVC_NETL_DIR)/tb-cvc.fl
|
||||
CVC_TB_SOURCE := $(RTL_PATH)/dv/tb/retrosoc_tb.sv
|
||||
CVC_EXT_MODELS := $(RTL_PATH)/dv/xezim/external_memory_models.sv
|
||||
|
||||
$(CVC_TB_FILTERED_FLIST): $(FILELIST_STAMP) $(CVC_FILELIST) $(CVC_TB_FLIST) \
|
||||
$(CVC_TB_SOURCE) $(CVC_EXT_MODELS)
|
||||
@mkdir -p $(@D)
|
||||
python3 $(CVC_FILELIST) --format cvc --filelist $(CVC_TB_FLIST) \
|
||||
--exclude-pattern 'at24cxxx\.sv$$' --exclude-pattern 'w25q128jvxim\.sv$$' \
|
||||
--exclude-pattern 'ESP_PSRAM64H\.sv$$' --exclude-pattern 'sdr\.v$$' \
|
||||
--exclude-pattern 'DVP_CAMERA\.sv$$' --source $(CVC_EXT_MODELS) --output $@
|
||||
|
||||
$(CVC_NETL_TB): $(FILELIST_STAMP) $(CVC_TB_CONVERT) $(CVC_TB_FILTERED_FLIST) \
|
||||
$(GENERATED_FL_DIR)/def.fl $(GENERATED_FL_DIR)/inc.fl $(PIN_MAP_FILELIST)
|
||||
@mkdir -p $(@D)
|
||||
python3 $(CVC_TB_CONVERT) -f $(GENERATED_FL_DIR)/def.fl -f $(GENERATED_FL_DIR)/inc.fl \
|
||||
-f $(PIN_MAP_FILELIST) -f $(CVC_TB_FILTERED_FLIST) \
|
||||
--output $@ --sv2v $(SV2V)
|
||||
|
||||
$(CVC_NETL_FLIST): $(FILELIST_STAMP) $(CVC_FILELIST) $(CVC_FILELISTS) $(CVC_NETL_TB) $(NETLIST_PATH)
|
||||
@mkdir -p $(@D)
|
||||
python3 $(CVC_FILELIST) --format cvc \
|
||||
$(foreach filelist,$(CVC_FILELISTS),--filelist $(filelist)) \
|
||||
--source $(NETLIST_PATH) --source $(CVC_NETL_TB) --output $@
|
||||
|
||||
$(CVC_NETL_SIMV): $(CVC_NETL_FLIST) $(NETLIST_PATH)
|
||||
@mkdir -p $(@D)
|
||||
$(FLOW_PYTHON) $(ROOT_PATH)/scripts/run_flow.py --tool cvc \
|
||||
--log $(CVC_NETL_DIR)/compile.log --result $(CVC_NETL_DIR)/result-compile.json \
|
||||
--cwd $(CVC_NETL_DIR) -- $(CVC) -q -Ogate $(CVC_TIMING_OPTS) -o simv -f $<
|
||||
|
||||
netcomp comp: $(CVC_NETL_SIMV)
|
||||
|
||||
netsim: netcomp
|
||||
python3 $(RTL_PATH)/script/prepare_norflash.py --sim-dir $(CVC_NETL_DIR) \
|
||||
--firmware $(SW_BUILD_DIR)/$(SIM_FIRMWARE_NAME).hex
|
||||
$(FLOW_PYTHON) $(ROOT_PATH)/scripts/run_flow.py --tool cvc-sim --stream-bytes \
|
||||
--log $(CVC_NETL_DIR)/sim.log --result $(CVC_NETL_DIR)/result-sim.json \
|
||||
--cwd $(CVC_NETL_DIR) -- ./simv +sim_timeout=$(RTL_SIM_TIMEOUT) +wave_$(WAVE)
|
||||
$(FLOW_PYTHON) $(ROOT_PATH)/scripts/check_simulation.py --log $(CVC_NETL_DIR)/sim.log \
|
||||
--result $(CVC_NETL_DIR)/result-sim-check.json --require '$(SIM_SUCCESS_MARKER)'
|
||||
|
||||
sim:
|
||||
@echo "CVC backend supports synthesized-netlist simulation; use netcomp or netsim" >&2
|
||||
@exit 2
|
||||
|
||||
postcomp postsim:
|
||||
@echo "CVC backend does not support post-layout SDF simulation in this integration" >&2
|
||||
@exit 2
|
||||
|
||||
wave netwave:
|
||||
@echo "CVC wave viewing is not configured; use CVC waveform options explicitly"
|
||||
|
||||
clean:
|
||||
python3 $(ROOT_PATH)/scripts/clean.py --root $(ROOT_PATH) --path $(CVC_ROOT)
|
||||
|
||||
comp netcomp netsim: | manifest
|
||||
|
||||
.PHONY: comp netcomp sim netsim postcomp postsim wave netwave clean
|
||||
@@ -1,65 +0,0 @@
|
||||
XEZIM ?= xezim
|
||||
XEZIM_MAX_TIME ?= $(if $(filter -1,$(RTL_SIM_TIMEOUT)),100000,$(RTL_SIM_TIMEOUT))
|
||||
|
||||
XEZIM_ROOT := $(SIM_BUILD_ROOT)
|
||||
XEZIM_BEHV_DIR := $(XEZIM_ROOT)/behv
|
||||
XEZIM_BEHV_FLIST := $(XEZIM_BEHV_DIR)/xezim.fl
|
||||
XEZIM_BEHV_STAMP := $(XEZIM_BEHV_DIR)/compile.stamp
|
||||
XEZIM_FILELIST := $(RTL_PATH)/script/gen_sim_filelist.py
|
||||
XEZIM_TB_SOURCE := $(RTL_PATH)/dv/tb/retrosoc_tb.sv
|
||||
XEZIM_SRAM_MODEL := $(RTL_PATH)/dv/xezim/ihp130_sram_models.sv
|
||||
XEZIM_EXT_MODELS := $(RTL_PATH)/dv/xezim/external_memory_models.sv
|
||||
XEZIM_FILELISTS := $(filter-out $(PDK_FILELIST),$(RTL_FILELISTS)) $(GENERATED_FL_DIR)/tb.fl
|
||||
|
||||
ifeq ($(PDK), IHP130)
|
||||
else
|
||||
$(error Xezim backend currently supports PDK=IHP130 only)
|
||||
endif
|
||||
|
||||
$(XEZIM_BEHV_FLIST): $(MPW_VARIANT_STAMP) $(FILELIST_STAMP) $(XEZIM_FILELIST) $(XEZIM_FILELISTS) \
|
||||
$(XEZIM_TB_SOURCE) $(XEZIM_SRAM_MODEL) $(XEZIM_EXT_MODELS)
|
||||
@mkdir -p $(@D)
|
||||
python3 $(XEZIM_FILELIST) --format xezim \
|
||||
$(foreach filelist,$(XEZIM_FILELISTS),--filelist $(filelist)) \
|
||||
--define +define+PDK_BEHAV --define +define+FUNCTIONAL \
|
||||
--exclude-pattern 'at24cxxx\.sv$$' --exclude-pattern 'sdr\.v$$' \
|
||||
--exclude-pattern 'w25q128jvxim\.sv$$' \
|
||||
--exclude-pattern 'ESP_PSRAM64H\.sv$$' --exclude-pattern 'DVP_CAMERA\.sv$$' \
|
||||
--source $(XEZIM_SRAM_MODEL) --source $(XEZIM_EXT_MODELS) --output $@
|
||||
|
||||
$(XEZIM_BEHV_STAMP): $(XEZIM_BEHV_FLIST)
|
||||
@mkdir -p $(@D)
|
||||
$(FLOW_PYTHON) $(ROOT_PATH)/scripts/run_flow.py --tool xezim \
|
||||
--log $(XEZIM_BEHV_DIR)/compile.log --result $(XEZIM_BEHV_DIR)/result-compile.json \
|
||||
--cwd $(XEZIM_BEHV_DIR) -- $(XEZIM) --compile -s $(RTL_TOP) -f $<
|
||||
@touch $@
|
||||
|
||||
comp: $(XEZIM_BEHV_STAMP)
|
||||
|
||||
sim: comp
|
||||
python3 $(RTL_PATH)/script/prepare_norflash.py --sim-dir $(XEZIM_BEHV_DIR) \
|
||||
--firmware $(SW_BUILD_DIR)/$(SIM_FIRMWARE_NAME).hex
|
||||
$(FLOW_PYTHON) $(ROOT_PATH)/scripts/run_flow.py --tool xezim-sim --stream-bytes \
|
||||
--log $(XEZIM_BEHV_DIR)/sim.log --result $(XEZIM_BEHV_DIR)/result-sim.json \
|
||||
--cwd $(XEZIM_BEHV_DIR) -- $(XEZIM) --simulate -s $(RTL_TOP) -f $(XEZIM_BEHV_FLIST) \
|
||||
--max-time $(XEZIM_MAX_TIME)ns +sim_timeout=$(RTL_SIM_TIMEOUT) +wave_$(WAVE)
|
||||
$(FLOW_PYTHON) $(ROOT_PATH)/scripts/check_simulation.py --log $(XEZIM_BEHV_DIR)/sim.log \
|
||||
--result $(XEZIM_BEHV_DIR)/result-sim-check.json --require '$(SIM_SUCCESS_MARKER)'
|
||||
|
||||
netcomp netlcomp:
|
||||
@echo "Xezim backend supports RTL behavior simulation only; use SIMU=CVC or SIMU=IVERILOG for netlists" >&2
|
||||
@exit 2
|
||||
|
||||
netsim postsim:
|
||||
@echo "Xezim backend does not support netlist or post-layout simulation in this integration" >&2
|
||||
@exit 2
|
||||
|
||||
wave:
|
||||
@echo "Xezim wave viewing is not configured; use the generated simulator log"
|
||||
|
||||
clean:
|
||||
python3 $(ROOT_PATH)/scripts/clean.py --root $(ROOT_PATH) --path $(XEZIM_ROOT)
|
||||
|
||||
comp sim: | manifest
|
||||
|
||||
.PHONY: comp sim netcomp netlcomp netsim postsim wave clean
|
||||
@@ -1,79 +0,0 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
from __future__ import annotations
|
||||
|
||||
import argparse
|
||||
import re
|
||||
from pathlib import Path
|
||||
|
||||
from filelist import FileList, atomic_write, parse_filelists
|
||||
|
||||
|
||||
def parse_args() -> argparse.Namespace:
|
||||
parser = argparse.ArgumentParser(description="Generate a simulator filelist")
|
||||
parser.add_argument("--format", choices=("cvc", "xezim"), required=True)
|
||||
parser.add_argument("--filelist", action="append", type=Path, required=True)
|
||||
parser.add_argument("--source", action="append", type=Path, default=[])
|
||||
parser.add_argument("--define", action="append", default=[])
|
||||
parser.add_argument("--exclude-pattern", action="append", default=[])
|
||||
parser.add_argument("--drop-option", action="append", default=[])
|
||||
parser.add_argument("--output", type=Path, required=True)
|
||||
return parser.parse_args()
|
||||
|
||||
|
||||
def quote(value: str) -> str:
|
||||
if not any(character.isspace() for character in value):
|
||||
return value
|
||||
return '"' + value.replace("\\", "\\\\").replace('"', '\\"') + '"'
|
||||
|
||||
|
||||
def define_name(value: str) -> str:
|
||||
return value[len("+define+") :] if value.startswith("+define+") else value
|
||||
|
||||
|
||||
def as_tokens(filelist: FileList, simulator: str) -> list[str]:
|
||||
options = list(filelist.options)
|
||||
if simulator == "xezim":
|
||||
tokens: list[str] = [f"-D{define_name(value)}" for value in filelist.defines]
|
||||
tokens.extend(f"-I{quote(str(path))}" for path in filelist.incdirs)
|
||||
else:
|
||||
tokens = list(filelist.defines)
|
||||
tokens.extend(quote(f"+incdir+{path}") for path in filelist.incdirs)
|
||||
tokens.extend(
|
||||
token
|
||||
for path in filelist.library_files
|
||||
for token in ("-v", quote(str(path)))
|
||||
)
|
||||
tokens.extend(options)
|
||||
tokens.extend(quote(str(path)) for path in filelist.files)
|
||||
return tokens
|
||||
|
||||
|
||||
def main() -> int:
|
||||
args = parse_args()
|
||||
filelist = parse_filelists(path.resolve() for path in args.filelist)
|
||||
filelist.options = [
|
||||
option for option in filelist.options if option not in set(args.drop_option)
|
||||
]
|
||||
filelist.defines.extend(args.define)
|
||||
patterns = [re.compile(pattern) for pattern in args.exclude_pattern]
|
||||
if patterns:
|
||||
filelist.files = [
|
||||
path
|
||||
for path in filelist.files
|
||||
if not any(pattern.search(str(path)) for pattern in patterns)
|
||||
]
|
||||
filelist.library_files = [
|
||||
path
|
||||
for path in filelist.library_files
|
||||
if not any(pattern.search(str(path)) for pattern in patterns)
|
||||
]
|
||||
filelist.files.extend(path.resolve() for path in args.source)
|
||||
filelist.deduplicate()
|
||||
content = "\n".join(as_tokens(filelist, args.format)) + "\n"
|
||||
atomic_write(args.output.resolve(), content)
|
||||
return 0
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
raise SystemExit(main())
|
||||
@@ -13,11 +13,6 @@ entry point. It installs only the checksum-verified open-source tool bundles and
|
||||
hash-pinned Python dependencies; project-local PDK and source setup remains under
|
||||
the existing Make targets.
|
||||
|
||||
The optional `XEZIM` and `CVC` simulator backends are intentionally not part of
|
||||
that locked installer. `scripts/doctor.py` checks them when `SIMU=XEZIM` or
|
||||
`SIMU=CVC` is selected and resolves the executable from the corresponding
|
||||
`XEZIM` or `CVC` environment variable.
|
||||
|
||||
`publish_fatfs_artifact.sh` is the manual release helper for the lock-pinned
|
||||
FatFs R0.16 archive. It verifies the archive, GitHub authentication, release
|
||||
absence, and the published asset checksum before reporting the checksum-pinned
|
||||
|
||||
@@ -4,7 +4,6 @@ from __future__ import annotations
|
||||
|
||||
import argparse
|
||||
import json
|
||||
import os
|
||||
import shutil
|
||||
import subprocess
|
||||
import sys
|
||||
@@ -41,9 +40,6 @@ def version(executable: str) -> str | None:
|
||||
"iverilog": "-V",
|
||||
"vvp": "-V",
|
||||
"sta": "-version",
|
||||
"xezim": "-V",
|
||||
"cvc": "-h",
|
||||
"cvc64": "-h",
|
||||
}
|
||||
result = subprocess.run(
|
||||
[executable, options.get(name, "--version")],
|
||||
@@ -66,10 +62,6 @@ def main() -> int:
|
||||
tools.extend(("verilator", "c++"))
|
||||
elif args.simu == "VCS":
|
||||
tools.extend(("bsub", "vcs"))
|
||||
elif args.simu == "XEZIM":
|
||||
tools.append(os.environ.get("XEZIM", "xezim"))
|
||||
elif args.simu == "CVC":
|
||||
tools.append(os.environ.get("CVC", "cvc"))
|
||||
if args.synth == "YOSYS":
|
||||
tools.append("yosys")
|
||||
if args.sta == "OPENSTA":
|
||||
|
||||
@@ -667,14 +667,15 @@ def test_make_dry_run_and_validation_do_not_write_filelists(tmp_path: Path) -> N
|
||||
)
|
||||
assert build_state() == before
|
||||
|
||||
invalid = subprocess.run(
|
||||
["make", "SIMU=UNKNOWN", "help"],
|
||||
cwd=ROOT,
|
||||
text=True,
|
||||
capture_output=True,
|
||||
)
|
||||
assert invalid.returncode != 0
|
||||
assert "Invalid SIMU='UNKNOWN'" in invalid.stderr
|
||||
for simulator in ("UNKNOWN", "XEZIM", "CVC"):
|
||||
invalid = subprocess.run(
|
||||
["make", f"SIMU={simulator}", "help"],
|
||||
cwd=ROOT,
|
||||
text=True,
|
||||
capture_output=True,
|
||||
)
|
||||
assert invalid.returncode != 0
|
||||
assert f"Invalid SIMU='{simulator}'" in invalid.stderr
|
||||
|
||||
removed_core = subprocess.run(
|
||||
["make", "CORE=alternate", "config"],
|
||||
|
||||
@@ -1,79 +0,0 @@
|
||||
"""Tests for optional simulator backend wiring and filelist translation."""
|
||||
|
||||
from __future__ import annotations
|
||||
|
||||
import subprocess
|
||||
import sys
|
||||
from pathlib import Path
|
||||
|
||||
|
||||
ROOT = Path(__file__).resolve().parents[1]
|
||||
FILELIST_SCRIPT = ROOT / "rtl/mini/script/gen_sim_filelist.py"
|
||||
|
||||
|
||||
def run_filelist(tmp_path: Path, simulator: str) -> str:
|
||||
tmp_path.mkdir(parents=True, exist_ok=True)
|
||||
source = tmp_path / "design.sv"
|
||||
include = tmp_path / "include"
|
||||
include.mkdir()
|
||||
source.write_text("module top; endmodule\n", encoding="utf-8")
|
||||
base = tmp_path / "base.fl"
|
||||
base.write_text(
|
||||
"# comment\n+define+FEATURE=1\n+incdir+"
|
||||
+ str(include)
|
||||
+ "\n"
|
||||
+ str(source)
|
||||
+ "\n",
|
||||
encoding="utf-8",
|
||||
)
|
||||
output = tmp_path / f"{simulator}.fl"
|
||||
result = subprocess.run(
|
||||
[
|
||||
sys.executable,
|
||||
str(FILELIST_SCRIPT),
|
||||
"--format",
|
||||
simulator,
|
||||
"--filelist",
|
||||
str(base),
|
||||
"--define",
|
||||
"+define+EXTRA=1",
|
||||
"--exclude-pattern",
|
||||
"does-not-match",
|
||||
"--output",
|
||||
str(output),
|
||||
],
|
||||
cwd=ROOT,
|
||||
text=True,
|
||||
capture_output=True,
|
||||
check=False,
|
||||
)
|
||||
assert result.returncode == 0, result.stderr
|
||||
return output.read_text(encoding="utf-8")
|
||||
|
||||
|
||||
def test_simulator_filelist_formats_are_tool_specific(tmp_path: Path) -> None:
|
||||
xezim = run_filelist(tmp_path / "xezim", "xezim")
|
||||
cvc = run_filelist(tmp_path / "cvc", "cvc")
|
||||
|
||||
assert "-DFEATURE=1" in xezim
|
||||
assert "-DEXTRA=1" in xezim
|
||||
assert f"-I{(tmp_path / 'xezim/include').resolve()}" in xezim
|
||||
assert "+define+FEATURE=1" in cvc
|
||||
assert "+incdir+" in cvc
|
||||
assert "# comment" not in xezim
|
||||
assert "design.sv" in cvc
|
||||
|
||||
|
||||
def test_optional_simulators_do_not_replace_default_backend() -> None:
|
||||
makefile = (ROOT / "Makefile").read_text(encoding="utf-8")
|
||||
mini_makefile = (ROOT / "rtl/mini/Makefile").read_text(encoding="utf-8")
|
||||
cvc_makefile = (ROOT / "rtl/mini/mk/cvc.mk").read_text(encoding="utf-8")
|
||||
|
||||
assert "SIMU ?= VCS" in makefile
|
||||
assert "VALID_SIMU := VCS VERILATOR IVERILOG XEZIM CVC" in makefile
|
||||
assert "include $(RTL_PATH)/mk/xezim.mk" in mini_makefile
|
||||
assert "include $(RTL_PATH)/mk/cvc.mk" in mini_makefile
|
||||
assert "CVC_TIMING_OPTS ?= +nospecify +notimingchecks" in cvc_makefile
|
||||
assert "-- $(CVC) -q -Ogate $(CVC_TIMING_OPTS) -o simv" in cvc_makefile
|
||||
assert "-- ./simv +sim_timeout=$(RTL_SIM_TIMEOUT)" in cvc_makefile
|
||||
assert cvc_makefile.count("$(CVC_TIMING_OPTS)") == 1
|
||||
Reference in new issue
Block a user