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feat: align input parameters in ahbl2ribp, rib2ram, rib2ribp, rib_error_slave, and ribp_topology_tb modules

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maksyuki committed 2026-08-04 16:29:25 +08:00
1 parent a87236ae33
commit fc6a46c5ee
5 files changed
+52 -52
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rtl/mini/top/ahbl2ribp.sv
+1 -1
View File
@@ -12,7 +12,7 @@
// Management-core AHB-Lite to scalar RIBP bridge.
module ahbl2ribp (
ahbl_if.slave ahbl,
ahbl_if.slave ahbl,
ribp_if.master ribp
);
rtl/mini/top/rib2ram.sv
+4 -4
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@@ -11,10 +11,10 @@
`include "rib_defs.svh"
module rib2ram (
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib,
ram_if.master ram
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib,
ram_if.master ram
);
localparam int RSP_WIDTH = 39;
rtl/mini/top/rib2ribp.sv
+4 -4
View File
@@ -11,10 +11,10 @@
`include "rib_defs.svh"
module rib2ribp (
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib,
ribp_if.master ribp
input logic clk_i,
input logic rst_n_i,
rib_if.slave rib,
ribp_if.master ribp
);
localparam logic [2:0] FSM_CMD = 3'd0;
rtl/mini/top/rib_error_slave.sv
+3 -3
View File
@@ -9,9 +9,9 @@
// See the Mulan PSL v2 for more details.
module rib_error_slave (
input logic clk_i,
input logic rst_n_i,
input logic [2:0] error_code_i,
input logic clk_i,
input logic rst_n_i,
input logic [2:0] error_code_i,
rib_if.slave rib
);
tests/rtl/ribp_topology_tb.sv
+40 -40
View File
@@ -74,48 +74,48 @@ module ribp_topology_tb;
endtask
initial begin
ribp.valid = 1'b0;
ribp.addr = '0;
ribp.wdata = '0;
ribp.wstrb = '0;
ribp.valid = 1'b0;
ribp.addr = '0;
ribp.wdata = '0;
ribp.wstrb = '0;
u_uart_ribp_if.ready = 1'b1;
u_gpio_ribp_if.ready = 1'b1;
u_tim0_ribp_if.ready = 1'b1;
u_tim1_ribp_if.ready = 1'b1;
u_psram_ribp_if.ready = 1'b1;
u_spisd_ribp_if.ready = 1'b1;
u_i2c0_ribp_if.ready = 1'b1;
u_i2s_ribp_if.ready = 1'b1;
u_onewire_ribp_if.ready = 1'b1;
u_xpi_ribp_if.ready = 1'b1;
u_dma_ribp_if.ready = 1'b1;
u_sysctrl_ribp_if.ready = 1'b1;
u_clint_ribp_if.ready = 1'b1;
u_sdram_ribp_if.ready = 1'b1;
u_dvp_ribp_if.ready = 1'b1;
u_sdio_ribp_if.ready = 1'b1;
u_opipsram_ribp_if.ready = 1'b1;
u_i2c1_ribp_if.ready = 1'b1;
u_uart_ribp_if.ready = 1'b1;
u_gpio_ribp_if.ready = 1'b1;
u_tim0_ribp_if.ready = 1'b1;
u_tim1_ribp_if.ready = 1'b1;
u_psram_ribp_if.ready = 1'b1;
u_spisd_ribp_if.ready = 1'b1;
u_i2c0_ribp_if.ready = 1'b1;
u_i2s_ribp_if.ready = 1'b1;
u_onewire_ribp_if.ready = 1'b1;
u_xpi_ribp_if.ready = 1'b1;
u_dma_ribp_if.ready = 1'b1;
u_sysctrl_ribp_if.ready = 1'b1;
u_clint_ribp_if.ready = 1'b1;
u_sdram_ribp_if.ready = 1'b1;
u_dvp_ribp_if.ready = 1'b1;
u_sdio_ribp_if.ready = 1'b1;
u_opipsram_ribp_if.ready = 1'b1;
u_i2c1_ribp_if.ready = 1'b1;
u_uart_ribp_if.rdata = 32'h0000_0000;
u_gpio_ribp_if.rdata = 32'h1111_1111;
u_tim0_ribp_if.rdata = 32'h2222_2222;
u_tim1_ribp_if.rdata = 32'h3333_3333;
u_psram_ribp_if.rdata = 32'h4444_4444;
u_spisd_ribp_if.rdata = 32'h5555_5555;
u_i2c0_ribp_if.rdata = 32'h6666_6666;
u_i2s_ribp_if.rdata = 32'h7777_7777;
u_onewire_ribp_if.rdata = 32'h8888_8888;
u_xpi_ribp_if.rdata = 32'h9999_9999;
u_dma_ribp_if.rdata = 32'hAAAA_AAAA;
u_sysctrl_ribp_if.rdata = 32'hBBBB_BBBB;
u_clint_ribp_if.rdata = 32'hCCCC_CCCC;
u_sdram_ribp_if.rdata = 32'hDDDD_DDDD;
u_dvp_ribp_if.rdata = 32'hEEEE_EEEE;
u_sdio_ribp_if.rdata = 32'hF0F0_F0F0;
u_opipsram_ribp_if.rdata = 32'h0F0F_0F0F;
u_i2c1_ribp_if.rdata = 32'h1234_5678;
u_uart_ribp_if.rdata = 32'h0000_0000;
u_gpio_ribp_if.rdata = 32'h1111_1111;
u_tim0_ribp_if.rdata = 32'h2222_2222;
u_tim1_ribp_if.rdata = 32'h3333_3333;
u_psram_ribp_if.rdata = 32'h4444_4444;
u_spisd_ribp_if.rdata = 32'h5555_5555;
u_i2c0_ribp_if.rdata = 32'h6666_6666;
u_i2s_ribp_if.rdata = 32'h7777_7777;
u_onewire_ribp_if.rdata = 32'h8888_8888;
u_xpi_ribp_if.rdata = 32'h9999_9999;
u_dma_ribp_if.rdata = 32'hAAAA_AAAA;
u_sysctrl_ribp_if.rdata = 32'hBBBB_BBBB;
u_clint_ribp_if.rdata = 32'hCCCC_CCCC;
u_sdram_ribp_if.rdata = 32'hDDDD_DDDD;
u_dvp_ribp_if.rdata = 32'hEEEE_EEEE;
u_sdio_ribp_if.rdata = 32'hF0F0_F0F0;
u_opipsram_ribp_if.rdata = 32'h0F0F_0F0F;
u_i2c1_ribp_if.rdata = 32'h1234_5678;
u_uart_ribp_if.resp_err = 1'b0;
u_gpio_ribp_if.resp_err = 1'b0;