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https://github.com/retroSoC/retroSoC.git
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92 lines
2.3 KiB
Systemverilog
92 lines
2.3 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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module rib_error_slave (
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input logic clk_i,
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input logic rst_n_i,
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input logic [2:0] error_code_i,
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rib_if.slave rib
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);
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localparam logic [1:0] FSM_CMD = 2'd0;
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localparam logic [1:0] FSM_WDATA = 2'd1;
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localparam logic [1:0] FSM_RESP = 2'd2;
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logic [1:0] s_fsm_d, s_fsm_q;
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logic [1:0] s_len_q;
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logic [1:0] s_beat_d, s_beat_q;
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logic [2:0] s_error_code_q;
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assign rib.cmd_ready = s_fsm_q == FSM_CMD;
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assign rib.w_ready = s_fsm_q == FSM_WDATA;
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assign rib.rsp_valid = s_fsm_q == FSM_RESP;
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assign rib.rdata = '0;
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assign rib.resp_err = 1'b1;
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assign rib.resp_code = s_error_code_q;
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assign rib.rsp_beat = s_beat_q;
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assign rib.rsp_last = 1'b1;
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always_comb begin
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s_fsm_d = s_fsm_q;
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s_beat_d = s_beat_q;
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unique case (s_fsm_q)
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FSM_CMD: begin
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if (rib.cmd_valid) begin
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s_beat_d = '0;
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s_fsm_d = rib.cmd_write ? FSM_WDATA : FSM_RESP;
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end
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end
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FSM_WDATA: begin
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if (rib.w_valid) begin
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if (rib.wlast || (s_beat_q == s_len_q)) begin
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s_fsm_d = FSM_RESP;
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end else begin
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s_beat_d = s_beat_q + 1'b1;
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end
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end
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end
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FSM_RESP: begin
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if (rib.rsp_ready) begin
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s_fsm_d = FSM_CMD;
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end
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end
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default: s_fsm_d = FSM_CMD;
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endcase
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end
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dffr #(2) u_fsm_dffr (
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clk_i,
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rst_n_i,
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s_fsm_d,
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s_fsm_q
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);
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dffer #(2) u_len_dffer (
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clk_i,
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rst_n_i,
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rib.cmd_valid && rib.cmd_ready,
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rib.cmd_len,
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s_len_q
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);
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dffer #(3) u_error_code_dffer (
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clk_i,
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rst_n_i,
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rib.cmd_valid && rib.cmd_ready,
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error_code_i,
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s_error_code_q
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);
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dffr #(2) u_beat_dffr (
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clk_i,
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rst_n_i,
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s_beat_d,
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s_beat_q
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);
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endmodule
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